From nobody Thu Dec 18 15:44:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2443C6FD18 for ; Wed, 19 Apr 2023 22:20:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232918AbjDSWUt (ORCPT ); Wed, 19 Apr 2023 18:20:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232406AbjDSWUM (ORCPT ); Wed, 19 Apr 2023 18:20:12 -0400 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 711EDA5EF for ; Wed, 19 Apr 2023 15:19:03 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-63b46186c03so455443b3a.3 for ; Wed, 19 Apr 2023 15:19:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681942707; x=1684534707; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WztMTyUU5RnTeRMzQjXOG7tTAHmGJecGpWKfqq8b0LY=; b=JM/4VdTUHWchd0agtBcZMVxlzWz+xlNHvW3+YRV1BgFp8SzvOalMG8gKSVRQwN23lF /HaZUXiHN5WGp4Li2ns1uHUPekHEfh3C+xw1tqVd+IJGR2EtpE3yOA/YQtJ1ZYeUVJ/l 7gjUeS7TILHwQHaL9l5Fnqsci5dyPD6ZQhESjL0jYTR+yEk6eIszpIH5SlasnHwxJ7Ky wlJDpXRoqS0jyG2/jEwfH6PNHHxv4wzD8drzVC/Q8h9ghskwb1QRJA40nqZUrBtk1qK0 ooViUN4xyDeEoBWE1iz1aXlci22pk9Oc7YzeXphdmUjkGiDah9tsQrhCdZR8NGP6os1O 4yYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681942707; x=1684534707; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WztMTyUU5RnTeRMzQjXOG7tTAHmGJecGpWKfqq8b0LY=; b=lYLt3+G1jG1Ndnf4ZeYcTs7rCw6XBUMu1i5Vt7WH47kWd6r+tox+2lRQtDQHFBU13W VgxUuQ3D5GNm/Us5VFeNffhUoXQ47RUoAr4lufdlZtnYFgQVdaBvSsHNjgjZsH097oQN KSaXrELHFynhP2cSSI9V6bFtTOtx4E50gkmGl6Ye7mtAwWiWjJSj1pc9uHu4jjQqNs69 G5v5nRtDy2CcL+gITjqIEhbmb7ZcdujGhF71g2mRgdanVYNT/CkbcPDFyGh2NAIdZvdP iNE2XP6F7KRd1i4l1bw28WZjkzcJZT8vopldDL0ulpmBiIPT5sEhHNFxK6/29qroRw0e 8O7Q== X-Gm-Message-State: AAQBX9e5nUrQsih6BmruMVSIiFXcNg5w27ovIB6RQvSjCWaxXRgQ+4eQ HJWbmOe0Wda6RplVSvhrRZlYsdM3IUPS9tEWsjY= X-Google-Smtp-Source: AKy350am1y3CAd0kzsPnqccpnVuquygqNjOFE27i75PzlAcwaRULYItnkTY6+2qQuafZtBMoWXv5YA== X-Received: by 2002:a17:902:b087:b0:1a6:9363:1632 with SMTP id p7-20020a170902b08700b001a693631632mr6436484plr.25.1681942707075; Wed, 19 Apr 2023 15:18:27 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jn11-20020a170903050b00b00196807b5189sm11619190plb.292.2023.04.19.15.18.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 15:18:26 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Rajnesh Kanwal , Atish Patra , Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Suzuki K Poulose , Will Deacon , Marc Zyngier , Sean Christopherson , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Uladzislau Rezki Subject: [RFC 26/48] RISC-V: Add COVI extension definitions Date: Wed, 19 Apr 2023 15:16:54 -0700 Message-Id: <20230419221716.3603068-27-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Rajnesh Kanwal This patch adds the CoVE interrupt management extension(COVI) details to the sbi header file. Signed-off-by: Atish Patra Signed-off-by: Rajnesh Kanwal --- arch/riscv/include/asm/sbi.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index c5a5526..bbea922 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -33,6 +33,7 @@ enum sbi_ext_id { SBI_EXT_DBCN =3D 0x4442434E, SBI_EXT_NACL =3D 0x4E41434C, SBI_EXT_COVH =3D 0x434F5648, + SBI_EXT_COVI =3D 0x434F5649, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -369,6 +370,20 @@ enum sbi_ext_covh_fid { SBI_EXT_COVH_TVM_INITIATE_FENCE, }; =20 +enum sbi_ext_covi_fid { + SBI_EXT_COVI_TVM_AIA_INIT, + SBI_EXT_COVI_TVM_CPU_SET_IMSIC_ADDR, + SBI_EXT_COVI_TVM_CONVERT_IMSIC, + SBI_EXT_COVI_TVM_RECLAIM_IMSIC, + SBI_EXT_COVI_TVM_CPU_BIND_IMSIC, + SBI_EXT_COVI_TVM_CPU_UNBIND_IMSIC_BEGIN, + SBI_EXT_COVI_TVM_CPU_UNBIND_IMSIC_END, + SBI_EXT_COVI_TVM_CPU_INJECT_EXT_INTERRUPT, + SBI_EXT_COVI_TVM_REBIND_IMSIC_BEGIN, + SBI_EXT_COVI_TVM_REBIND_IMSIC_CLONE, + SBI_EXT_COVI_TVM_REBIND_IMSIC_END, +}; + enum sbi_cove_page_type { SBI_COVE_PAGE_4K, SBI_COVE_PAGE_2MB, @@ -409,6 +424,21 @@ struct sbi_cove_tvm_create_params { unsigned long tvm_state_addr; }; =20 +struct sbi_cove_tvm_aia_params { + /* The base address is the address of the IMSIC with group ID, hart ID, a= nd guest ID of 0 */ + uint64_t imsic_base_addr; + /* The number of group index bits in an IMSIC address */ + uint32_t group_index_bits; + /* The location of the group index in an IMSIC address. Must be >=3D 24i.= */ + uint32_t group_index_shift; + /* The number of hart index bits in an IMSIC address */ + uint32_t hart_index_bits; + /* The number of guest index bits in an IMSIC address. Must be >=3D log2(= guests/hart + 1) */ + uint32_t guest_index_bits; + /* The number of guest interrupt files to be implemented per vCPU */ + uint32_t guests_per_hart; +}; + #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f --=20 2.25.1