From nobody Thu Dec 18 15:44:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DF6CC77B73 for ; Wed, 19 Apr 2023 22:20:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232689AbjDSWUD (ORCPT ); Wed, 19 Apr 2023 18:20:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231950AbjDSWT1 (ORCPT ); Wed, 19 Apr 2023 18:19:27 -0400 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CCFE7297 for ; Wed, 19 Apr 2023 15:18:33 -0700 (PDT) Received: by mail-pg1-x52d.google.com with SMTP id 41be03b00d2f7-524b02cc166so64611a12.0 for ; Wed, 19 Apr 2023 15:18:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681942698; x=1684534698; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Pex4ariWnXDdKnos4XH43DasA78+EqfUbH0Wh8CR5w4=; b=di7chbqLiC3SvYTY8G+fGI2cGV6/NplXfCh5v5XyNgDlngesP2y27MIvOHwrp1X4yx 4JsJle4v6NILzYjrBdQfclQHMQ1y+XkUvrnKfQUj0Ry5xsz9RSAaP7xk6bNe/vd52w3q C3nd14GGW5Qj94glYyk3NSDPRmLJqvozvF8lGdcOkQJDY2HZ2XGm6lNAbX6/JmUwtYhH cJH7ZmbN28BevOjXzCzDy6LpP/+8QR1qPGxigpkkPQjHRv6qA67df2bzJD5EJMK27xPT x2yJWlQYdkRTzgVvhswp/3TbWfU5x7nor5CBTVJeRFUg+I3fFtPgIMfjV7YwcmwCLtW3 tRuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681942698; x=1684534698; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Pex4ariWnXDdKnos4XH43DasA78+EqfUbH0Wh8CR5w4=; b=OKn/DsRRd7BL1fRz9qssKqll3gqfpYrxe/r+gRXsDyb17AHLvF6TS/k96qD6hRFSRd ZC4oXm5GJuQUW3Fa23/upH5PA3gq3qAQaqgvMP2+pFHyXcP1NrvqPqfOGqEDNZthwTmD OcQ3nSqL84Gu6bznCGe2QWUvz2oQD47Vr10Bz48YiW+7SlgRzCvIT0KAJXXPJMbROoq/ DndlMAttwMJko+1dyqQIiqIJ5UGLBFCWS4P/w2Rr8E9UfFZ+hZN+nt9yzPsrJSRW1lvD VwV3o5zR/8On7TjDq8i99BAnsrX1f9d5QC5U+y+SrLXaoaN14lypMIU/uZu9OgXMKpfa 6u8w== X-Gm-Message-State: AAQBX9dbXyzSb1OK3VfvZnIWWWQf7L3wdEYgiLnyERybFNBdPAzrpwfN OH1nhOB3tkBKFjdI/2RNeQoCyNAdAUtHDgTHJvU= X-Google-Smtp-Source: AKy350bAGBT2wDySHdJsoaBivRKAhhoN6FGmg4/i0kk3x7CE/96pMKWgvriPwXlMHgJNkHUROr/6AQ== X-Received: by 2002:a17:903:1210:b0:1a6:4a64:4d27 with SMTP id l16-20020a170903121000b001a64a644d27mr7784281plh.40.1681942697893; Wed, 19 Apr 2023 15:18:17 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jn11-20020a170903050b00b00196807b5189sm11619190plb.292.2023.04.19.15.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 15:18:17 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Rajnesh Kanwal , Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Suzuki K Poulose , Will Deacon , Marc Zyngier , Sean Christopherson , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Uladzislau Rezki Subject: [RFC 22/48] RISC-V: KVM: Implement vcpu load/put functions for CoVE guests Date: Wed, 19 Apr 2023 15:16:50 -0700 Message-Id: <20230419221716.3603068-23-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The TSM takes care of most of the H extension CSR/fp save/restore for any guest running in CoVE. It may choose to do the fp save/restore lazily as well. The host has to do minimal operations such timer save/restore and interrupt state restore during vcpu load/put. Signed-off-by: Rajnesh Kanwal Signed-off-by: Atish Patra --- arch/riscv/kvm/cove.c | 12 ++++++++++-- arch/riscv/kvm/vcpu.c | 12 +++++++++++- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kvm/cove.c b/arch/riscv/kvm/cove.c index 87fa04b..c93de9b 100644 --- a/arch/riscv/kvm/cove.c +++ b/arch/riscv/kvm/cove.c @@ -139,12 +139,20 @@ __always_inline bool kvm_riscv_cove_enabled(void) =20 void kvm_riscv_cove_vcpu_load(struct kvm_vcpu *vcpu) { - /* TODO */ + kvm_riscv_vcpu_timer_restore(vcpu); } =20 void kvm_riscv_cove_vcpu_put(struct kvm_vcpu *vcpu) { - /* TODO */ + void *nshmem; + struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + + kvm_riscv_vcpu_timer_save(vcpu); + /* NACL is mandatory for CoVE */ + nshmem =3D nacl_shmem(); + + /* Only VSIE needs to be read to manage the interrupt stuff */ + csr->vsie =3D nacl_shmem_csr_read(nshmem, CSR_VSIE); } =20 int kvm_riscv_cove_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *r= un) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 8cf462c..3e04b78 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -972,6 +972,11 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) u64 henvcfg =3D kvm_riscv_vcpu_get_henvcfg(vcpu->arch.isa); struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; =20 + if (is_cove_vcpu(vcpu)) { + kvm_riscv_cove_vcpu_load(vcpu); + goto skip_load; + } + if (kvm_riscv_nacl_sync_csr_available()) { nshmem =3D nacl_shmem(); nacl_shmem_csr_write(nshmem, CSR_VSSTATUS, csr->vsstatus); @@ -1010,9 +1015,9 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cp= u) kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context); kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context, vcpu->arch.isa); - kvm_riscv_vcpu_aia_load(vcpu, cpu); =20 +skip_load: vcpu->cpu =3D cpu; } =20 @@ -1023,6 +1028,11 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) =20 vcpu->cpu =3D -1; =20 + if (is_cove_vcpu(vcpu)) { + kvm_riscv_cove_vcpu_put(vcpu); + return; + } + kvm_riscv_vcpu_aia_put(vcpu); =20 kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context, --=20 2.25.1