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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id t3-20020a5d5343000000b002c55521903bsm16304136wrv.51.2023.04.19.10.17.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 10:17:52 -0700 (PDT) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Peter Geis Cc: Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: rockchip: fix nEXTRST on SOQuartz Date: Wed, 19 Apr 2023 19:17:31 +0200 Message-Id: <20230419171731.28641-1-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In pre-production prototypes (of which I only know one person having one, Peter Geis), GPIO0 pin A5 was tied to the SDMMC power enable pin on the CM4 connector. On all production models, this is not the case; instead, this pin is used for the nEXTRST signal, and the SDMMC power enable pin is always pulled high. Since everyone currently using the SOQuartz device trees will want this change, it is made to the tree without splitting the trees into two separate ones of which users will then inevitably choose the wrong one. This fixes USB and PCIe on a wide variety of CM4IO-compatible boards which either rely on the 3.3V being there or use the nEXTRST signal. Fixes: 5859b5a9c3ac ("arm64: dts: rockchip: add SoQuartz CM4IO dts") Signed-off-by: Nicolas Frattaroli --- .../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 18 +++++++------ .../boot/dts/rockchip/rk3566-soquartz.dtsi | 25 ++++++++++--------- 2 files changed, 24 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/ar= m64/boot/dts/rockchip/rk3566-soquartz-cm4.dts index 263ce40770dd..cddf6cd2fecb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts @@ -28,6 +28,16 @@ vcc_5v: vcc-5v-regulator { regulator-max-microvolt =3D <5000000>; vin-supply =3D <&vcc12v_dcin>; }; + + vcc_sd_pwr: vcc-sd-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_sd_pwr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc3v3_sys>; + }; }; =20 /* phy for pcie */ @@ -130,13 +140,7 @@ &saradc { }; =20 &sdmmc0 { - vmmc-supply =3D <&sdmmc_pwr>; - status =3D "okay"; -}; - -&sdmmc_pwr { - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; + vmmc-supply =3D <&vcc_sd_pwr>; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64= /boot/dts/rockchip/rk3566-soquartz.dtsi index ce7165d7f1a1..f589a4fdaccb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -65,6 +65,17 @@ led_work: led-work { }; }; =20 + nextrst_pin: nextrst-pin-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nextrst_h>; + regulator-always-on; + regulator-boot-on; + regulator-name =3D "nextrst"; + }; + sdio_pwrseq: sdio-pwrseq { status =3D "okay"; compatible =3D "mmc-pwrseq-simple"; @@ -104,16 +115,6 @@ vcc3v3_sys: vcc3v3-sys-regulator { regulator-max-microvolt =3D <3300000>; vin-supply =3D <&vcc5v0_sys>; }; - - sdmmc_pwr: sdmmc-pwr-regulator { - compatible =3D "regulator-fixed"; - enable-active-high; - gpio =3D <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&sdmmc_pwr_h>; - regulator-name =3D "sdmmc_pwr"; - status =3D "disabled"; - }; }; =20 &cpu0 { @@ -539,8 +540,8 @@ wifi_enable_h: wifi-enable-h { }; }; =20 - sdmmc-pwr { - sdmmc_pwr_h: sdmmc-pwr-h { + nextrst { + nextrst_h: nextrst-h { rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; --=20 2.40.0