From nobody Tue Dec 16 11:45:05 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8813BC6FD18 for ; Wed, 19 Apr 2023 11:12:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232926AbjDSLMT (ORCPT ); Wed, 19 Apr 2023 07:12:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232957AbjDSLLW (ORCPT ); Wed, 19 Apr 2023 07:11:22 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D94813FBE for ; Wed, 19 Apr 2023 04:10:42 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-63b5c48ea09so2658986b3a.1 for ; Wed, 19 Apr 2023 04:10:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1681902637; x=1684494637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c7Svk0AxAB3qoYix/qOEG4Vz2rPPucsqQxdMzpYchZI=; b=XmTXt7ZqxWddAV0JDjC4c6Eovx0mOpcDKBV+L7pg9kHRvcw0NrF6W5p8otcbboa+62 0Yk50tsyKQO7E16Y/ShbQGi0tV2oXZlaNnHeVE6My6EBSsLfSGdR1+H6hWc/4acwEQ7I sWiwrUzhpp1UOdQZv3Ffz/odeJ0xUcVsv6OZr4R81gtBHSsPz8N3GNMSFdOKlQ1aHAs8 /spzVKy5R+TMO/mlwy+UzyNZCIWi2iWBDIZpNtT4Ax7/9NE7gFAnx/7iTw594j+hUdmv 76inOtM+g2caKo9rqPK7MQtjifRFGMhyGybonQmyu8ffgr+glE+3PiwJvmG3YUL2vKP6 mFvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681902637; x=1684494637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c7Svk0AxAB3qoYix/qOEG4Vz2rPPucsqQxdMzpYchZI=; b=Gr/LWDzMwrXAjSBUxbsEjQOM+ofwXJykELlF1L53RtBM2DcZM8K3LXpuUIjbkf/ToR PaDGVCnj9e4raCSGHKVYYqXpPt50UJevyMg1Uuha/KLLH+GEoKQ5l6DHDHjvJhR7Nr6q iANPQh+Tk5s+eZpYGG/59B8sX2VeZU5ykriap3JCHNQl1MXeGgCihlcA/xSIh/UDLs2w l+uNpNDwEwuxeSFcClANRixp/0JsFIxOiXC0yAFK8isUHl9u3KgfkHXC5YS+DlSftO86 z2IhiwGnuVfYJ50bz+AuxKvcQXqMZygk7pieKCoS49GpeGWz9Jb2ohchnnGGcLJGKhoB Rchg== X-Gm-Message-State: AAQBX9c07xgKk4N4bv8s4/lodpDzbL/iMg2fObclfNmivyg+CNX9SZwF AJy+/nZTCEVTrBtOiGLnrWxEPg== X-Google-Smtp-Source: AKy350Y+nSBqUtz+XvYHUUrNKxlm15TSYw6mypxGarQ1iC83U3uspOXzd41NldV5dyN0PmskVrA9XA== X-Received: by 2002:a17:903:294c:b0:1a6:ebc1:c54d with SMTP id li12-20020a170903294c00b001a6ebc1c54dmr4710186plb.30.1681902636996; Wed, 19 Apr 2023 04:10:36 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1800:f680:eaf2:1d7a:7338:16cb]) by smtp.gmail.com with ESMTPSA id g12-20020a1709026b4c00b001a24cded097sm11180774plt.236.2023.04.19.04.10.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 04:10:36 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 19/21] DO_NOT_MERGE riscv: dts: qemu: add dump from riscv-cbqri-rfc Date: Wed, 19 Apr 2023 04:11:09 -0700 Message-Id: <20230419111111.477118-20-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Dumped dtb from qemu branch riscv-cbqri-rfc which is on top of qemu master (tag: v8.0.0-rc4) with qemu/VERSION of 7.2.94 invoked with: qemu-system-riscv64 \ -M virt \ -nographic \ -smp 8 \ -bios output/images/fw_jump.elf \ -kernel $HOME/kernel/cbqri-linux/arch/riscv/boot/Image \ -append "root=3D/dev/vda ro" \ -drive file=3Doutput/images/rootfs.ext2,format=3Draw,id=3Dhd0 \ -device virtio-blk-device,drive=3Dhd0 \ -machine dumpdtb=3Dqemu.dtb Link: https://gitlab.baylibre.com/baylibre/qemu/-/tree/riscv-cbqri-rfc Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- Note: this is necessary as Qemu branch riscv-cbqri-rfc does not yet support generating a dtb with the nodes and properties needed for CBQRI controllers. Thus, those lines must be added in the next patch and an external dtb (qemu-virt-cbqri.dtb) built by Linux is used when invoking qemu-system-riscv64 arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts | 371 +++++++++++++++++++ 1 file changed, 371 insertions(+) create mode 100644 arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts diff --git a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts b/arch/riscv/boot= /dts/qemu/qemu-virt-cbqri.dts new file mode 100644 index 000000000000..400ed48a06af --- /dev/null +++ b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/dts-v1/; + +/ { + #address-cells =3D <0x02>; + #size-cells =3D <0x02>; + compatible =3D "riscv-virtio"; + model =3D "riscv-virtio,qemu"; + + fw-cfg@10100000 { + dma-coherent; + reg =3D <0x00 0x10100000 0x00 0x18>; + compatible =3D "qemu,fw-cfg-mmio"; + }; + + flash@20000000 { + bank-width =3D <0x04>; + reg =3D <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>; + compatible =3D "cfi-flash"; + }; + + chosen { + bootargs =3D "root=3D/dev/vda ro ftrace=3Dfunction_graph ftrace_filter= =3D\"*resctrl*,*qos*\""; + rng-seed =3D <0xb87c09c5 0xc8f0c713 0x9c217b2a 0xa6f44e14 0xb6e99df6 0x2= 05d482b 0x6d4c34f4 0x6466fc08>; + stdout-path =3D "/soc/serial@10000000"; + }; + + poweroff { + value =3D <0x5555>; + offset =3D <0x00>; + regmap =3D <0x12>; + compatible =3D "syscon-poweroff"; + }; + + reboot { + value =3D <0x7777>; + offset =3D <0x00>; + regmap =3D <0x12>; + compatible =3D "syscon-reboot"; + }; + + platform-bus@4000000 { + interrupt-parent =3D <0x11>; + ranges =3D <0x00 0x00 0x4000000 0x2000000>; + #address-cells =3D <0x01>; + #size-cells =3D <0x01>; + compatible =3D "qemu,platform\0simple-bus"; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x00 0x80000000 0x00 0x8000000>; + }; + + cpus { + #address-cells =3D <0x01>; + #size-cells =3D <0x00>; + timebase-frequency =3D <0x989680>; + + cpu@0 { + phandle =3D <0x0f>; + device_type =3D "cpu"; + reg =3D <0x00>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x10>; + }; + }; + + cpu@1 { + phandle =3D <0x0d>; + device_type =3D "cpu"; + reg =3D <0x01>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0e>; + }; + }; + + cpu@2 { + phandle =3D <0x0b>; + device_type =3D "cpu"; + reg =3D <0x02>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0c>; + }; + }; + + cpu@3 { + phandle =3D <0x09>; + device_type =3D "cpu"; + reg =3D <0x03>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0a>; + }; + }; + + cpu@4 { + phandle =3D <0x07>; + device_type =3D "cpu"; + reg =3D <0x04>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x08>; + }; + }; + + cpu@5 { + phandle =3D <0x05>; + device_type =3D "cpu"; + reg =3D <0x05>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x06>; + }; + }; + + cpu@6 { + phandle =3D <0x03>; + device_type =3D "cpu"; + reg =3D <0x06>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x04>; + }; + }; + + cpu@7 { + phandle =3D <0x01>; + device_type =3D "cpu"; + reg =3D <0x07>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x02>; + }; + }; + + cpu-map { + + cluster0 { + + core0 { + cpu =3D <0x0f>; + }; + + core1 { + cpu =3D <0x0d>; + }; + + core2 { + cpu =3D <0x0b>; + }; + + core3 { + cpu =3D <0x09>; + }; + + core4 { + cpu =3D <0x07>; + }; + + core5 { + cpu =3D <0x05>; + }; + + core6 { + cpu =3D <0x03>; + }; + + core7 { + cpu =3D <0x01>; + }; + }; + }; + }; + + soc { + #address-cells =3D <0x02>; + #size-cells =3D <0x02>; + compatible =3D "simple-bus"; + ranges; + + pmu { + riscv,event-to-mhpmcounters =3D <0x01 0x01 0x7fff9 0x02 0x02 0x7fffc 0x= 10019 0x10019 0x7fff8 0x1001b 0x1001b 0x7fff8 0x10021 0x10021 0x7fff8 0x00 = 0x00 0x00 0x00 0x00>; + compatible =3D "riscv,pmu"; + }; + + rtc@101000 { + interrupts =3D <0x0b>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x101000 0x00 0x1000>; + compatible =3D "google,goldfish-rtc"; + }; + + serial@10000000 { + interrupts =3D <0x0a>; + interrupt-parent =3D <0x11>; + clock-frequency =3D "\08@"; + reg =3D <0x00 0x10000000 0x00 0x100>; + compatible =3D "ns16550a"; + }; + + test@100000 { + phandle =3D <0x12>; + reg =3D <0x00 0x100000 0x00 0x1000>; + compatible =3D "sifive,test1\0sifive,test0\0syscon"; + }; + + pci@30000000 { + interrupt-map-mask =3D <0x1800 0x00 0x00 0x07>; + interrupt-map =3D <0x00 0x00 0x00 0x01 0x11 0x20 0x00 0x00 0x00 0x02 0x= 11 0x21 0x00 0x00 0x00 0x03 0x11 0x22 0x00 0x00 0x00 0x04 0x11 0x23 0x800 0= x00 0x00 0x01 0x11 0x21 0x800 0x00 0x00 0x02 0x11 0x22 0x800 0x00 0x00 0x03= 0x11 0x23 0x800 0x00 0x00 0x04 0x11 0x20 0x1000 0x00 0x00 0x01 0x11 0x22 0= x1000 0x00 0x00 0x02 0x11 0x23 0x1000 0x00 0x00 0x03 0x11 0x20 0x1000 0x00 = 0x00 0x04 0x11 0x21 0x1800 0x00 0x00 0x01 0x11 0x23 0x1800 0x00 0x00 0x02 0= x11 0x20 0x1800 0x00 0x00 0x03 0x11 0x21 0x1800 0x00 0x00 0x04 0x11 0x22>; + ranges =3D <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0= x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x0= 0 0x04 0x00>; + reg =3D <0x00 0x30000000 0x00 0x10000000>; + dma-coherent; + bus-range =3D <0x00 0xff>; + linux,pci-domain =3D <0x00>; + device_type =3D "pci"; + compatible =3D "pci-host-ecam-generic"; + #size-cells =3D <0x02>; + #interrupt-cells =3D <0x01>; + #address-cells =3D <0x03>; + }; + + virtio_mmio@10008000 { + interrupts =3D <0x08>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10008000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10007000 { + interrupts =3D <0x07>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10007000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10006000 { + interrupts =3D <0x06>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10006000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10005000 { + interrupts =3D <0x05>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10005000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10004000 { + interrupts =3D <0x04>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10004000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10003000 { + interrupts =3D <0x03>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10003000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10002000 { + interrupts =3D <0x02>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10002000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10001000 { + interrupts =3D <0x01>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10001000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + plic@c000000 { + phandle =3D <0x11>; + riscv,ndev =3D <0x5f>; + reg =3D <0x00 0xc000000 0x00 0x600000>; + interrupts-extended =3D <0x10 0x0b 0x10 0x09 0x0e 0x0b 0x0e 0x09 0x0c 0= x0b 0x0c 0x09 0x0a 0x0b 0x0a 0x09 0x08 0x0b 0x08 0x09 0x06 0x0b 0x06 0x09 0= x04 0x0b 0x04 0x09 0x02 0x0b 0x02 0x09>; + interrupt-controller; + compatible =3D "sifive,plic-1.0.0\0riscv,plic0"; + #address-cells =3D <0x00>; + #interrupt-cells =3D <0x01>; + }; + + clint@2000000 { + interrupts-extended =3D <0x10 0x03 0x10 0x07 0x0e 0x03 0x0e 0x07 0x0c 0= x03 0x0c 0x07 0x0a 0x03 0x0a 0x07 0x08 0x03 0x08 0x07 0x06 0x03 0x06 0x07 0= x04 0x03 0x04 0x07 0x02 0x03 0x02 0x07>; + reg =3D <0x00 0x2000000 0x00 0x10000>; + compatible =3D "sifive,clint0\0riscv,clint0"; + }; + }; +}; --=20 2.34.1