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Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf Signed-off-by: Kornel Dul=C4=99ba [dfustini: rebase from v6.0 to v6.3] Signed-off-by: Drew Fustini --- Note: - A version of this patch rebased on riscv/for-next was already submitted as an RFC to linux-riscv [1] with Message-ID: 20230410043646.3138446-1-dfustini@baylibre.com - This patch is included in this RFC series so as to provide a cohesive demonstration in one series. [1] https://lore.kernel.org/lkml/20230410043646.3138446-1-dfustini@baylibre= .com/ arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e3021b2590de..255c5c4d0a24 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -42,6 +42,8 @@ #define RISCV_ISA_EXT_ZBB 30 #define RISCV_ISA_EXT_ZICBOM 31 #define RISCV_ISA_EXT_ZIHINTPAUSE 32 +#define RISCV_ISA_EXT_SSQOSID 35 + =20 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 8400f0cc9704..d1441872f173 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -189,6 +189,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] =3D { __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(ssqosid, RISCV_ISA_EXT_SSQOSID), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 59d58ee0f68d..80317d2d3975 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -222,6 +222,7 @@ void __init riscv_fill_hwcap(void) } else { /* sorted alphabetically */ SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); + SET_ISA_EXT_MAP("ssqosid", RISCV_ISA_EXT_SSQOSID); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66101C77B73 for ; Wed, 19 Apr 2023 11:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232818AbjDSLKt (ORCPT ); Wed, 19 Apr 2023 07:10:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232840AbjDSLKk (ORCPT ); Wed, 19 Apr 2023 07:10:40 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4813414F51 for ; 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Wed, 19 Apr 2023 04:10:09 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 02/21] RISC-V: Add support for sqoscfg CSR Date: Wed, 19 Apr 2023 04:10:52 -0700 Message-Id: <20230419111111.477118-3-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the sqoscfg CSR defined in the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). The CSR contains two fields: - Resource Control ID (RCID) used determine resource allocation - Monitoring Counter ID (MCID) used to track resource usage Requests from a hart to shared resources like cache will be tagged with these IDs. This allows the usage of shared resources to be associated with the task currently running on the hart. A sqoscfg field is added to thread_struct and has the same format as the sqoscfg CSR. This allows the scheduler to set the hart's sqoscfg CSR to contain the RCID and MCID for the task that is being scheduled in. The sqoscfg CSR is only written to if the thread_struct.sqoscfg is different than the current value of the CSR. A per-cpu variable cpu_sqoscfg is used to mirror that state of the CSR. This is because access to L1D hot memory should be several times faster than a CSR read. Also, in the case of virtualization, accesses to this CSR are trapped in the hypervisor. Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf Co-developed-by: Kornel Dul=C4=99ba Signed-off-by: Kornel Dul=C4=99ba Signed-off-by: Drew Fustini --- Note: - A version of this patch rebased on riscv/for-next was already submitted as an RFC to linux-riscv [1] with Message-ID: 20230410043646.3138446-1-dfustini@baylibre.com - This patch is included in this RFC series so as to provide a cohesive demonstration in one series. [1] https://lore.kernel.org/lkml/20230410043646.3138446-1-dfustini@baylibre= .com/ arch/riscv/Kconfig | 19 ++++++++++++++ arch/riscv/include/asm/csr.h | 8 ++++++ arch/riscv/include/asm/processor.h | 3 +++ arch/riscv/include/asm/qos.h | 40 ++++++++++++++++++++++++++++++ arch/riscv/include/asm/switch_to.h | 2 ++ 5 files changed, 72 insertions(+) create mode 100644 arch/riscv/include/asm/qos.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c5e42cc37604..9d4c8c505191 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -398,6 +398,25 @@ config RISCV_ISA_C =20 If you don't know what to do here, say Y. =20 +config RISCV_ISA_SSQOSID + bool "Ssqosid extension support for supervisor mode Quality of Service ID" + default y + help + Adds support for the Ssqosid ISA extension (Supervisor-mode + Quality of Service ID). + + Ssqosid defines the sqoscfg CSR which allows the system to tag + the running process with RCID (Resource Control ID) and MCID + (Monitoring Counter ID). The RCID is used to determine resource + allocation. The MCID is used to track resource usage in event + counters. + + For example, a cache controller may use the RCID to apply a + cache partitioning scheme and use the MCID to track how much + cache a process, or a group of processes, is using. + + If you don't know what to do here, say Y. + config RISCV_ISA_SVPBMT bool "SVPBMT extension support" depends on 64BIT && MMU diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 0e571f6483d9..ab222ca15799 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -60,6 +60,13 @@ #define SATP_ASID_MASK _AC(0xFFFF, UL) #endif =20 +/* SQOSCFG fields */ +#define SQOSCFG_RCID_MASK _AC(0x00000FFF, UL) +#define SQOSCFG_MCID_MASK SQOSCFG_RCID_MASK +#define SQOSCFG_MCID_SHIFT 16 +#define SQOSCFG_MASK ((SQOSCFG_MCID_MASK << SQOSCFG_MCID_SHIFT) | \ + SQOSCFG_RCID_MASK) + /* Exception cause high bit - is an interrupt if set */ #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) =20 @@ -246,6 +253,7 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SATP 0x180 +#define CSR_SQOSCFG 0x181 =20 #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 94a0590c6971..724b2aa2732d 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -39,6 +39,9 @@ struct thread_struct { unsigned long s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; unsigned long bad_cause; +#ifdef CONFIG_RISCV_ISA_SSQOSID + u32 sqoscfg; +#endif }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h new file mode 100644 index 000000000000..297e7fb64d80 --- /dev/null +++ b/arch/riscv/include/asm/qos.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_QOS_H +#define _ASM_RISCV_QOS_H + +#ifdef CONFIG_RISCV_ISA_SSQOSID + +#include +#include + +#include +#include +#include + +/* cached value of sqoscfg csr for each cpu */ +static DEFINE_PER_CPU(u32, cpu_sqoscfg); + +static void __qos_sched_in(struct task_struct *task) +{ + u32 *cpu_sqoscfg_ptr =3D this_cpu_ptr(&cpu_sqoscfg); + u32 thread_sqoscfg; + + thread_sqoscfg =3D READ_ONCE(task->thread.sqoscfg); + + if (thread_sqoscfg !=3D *cpu_sqoscfg_ptr) { + *cpu_sqoscfg_ptr =3D thread_sqoscfg; + csr_write(CSR_SQOSCFG, thread_sqoscfg); + } +} + +static inline void qos_sched_in(struct task_struct *task) +{ + if (riscv_has_extension_likely(RISCV_ISA_EXT_SSQOSID)) + __qos_sched_in(task); +} +#else + +static inline void qos_sched_in(struct task_struct *task) {} + +#endif /* CONFIG_RISCV_ISA_SSQOSID */ +#endif /* _ASM_RISCV_QOS_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 60f8ca01d36e..75d9bfd766af 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -12,6 +12,7 @@ #include #include #include +#include =20 #ifdef CONFIG_FPU extern void __fstate_save(struct task_struct *save_to); @@ -79,6 +80,7 @@ do { \ if (has_fpu()) \ __switch_to_aux(__prev, __next); \ ((last) =3D __switch_to(__prev, __next)); \ + qos_sched_in(__next); \ } while (0) =20 #endif /* _ASM_RISCV_SWITCH_TO_H */ --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9793EC77B73 for ; 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charset="utf-8" Define data structure to represent the CBQRI properties that a driver for an CBQRI-capable controller would discover during probe. Each instance of a CBQRI-capable controller is added to a list that the RISC-V CBQRI resctrl implementation will consume. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- include/linux/riscv_qos.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 include/linux/riscv_qos.h diff --git a/include/linux/riscv_qos.h b/include/linux/riscv_qos.h new file mode 100644 index 000000000000..95016810b575 --- /dev/null +++ b/include/linux/riscv_qos.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __LINUX_RISCV_QOS_H +#define __LINUX_RISCV_QOS_H + +#include +#include + +#include + +enum cbqri_controller_type { + CBQRI_CONTROLLER_TYPE_CAPACITY, + CBQRI_CONTROLLER_TYPE_BANDWIDTH, + CBQRI_CONTROLLER_TYPE_UNKNOWN +}; + +struct cbqri_controller_info { + unsigned long addr; + unsigned long size; + enum cbqri_controller_type type; + u32 rcid_count; + u32 mcid_count; + struct list_head list; + + struct cache_controller { + int cache_level; + u32 cache_size; /* in bytes */ + struct cpumask cpu_mask; + } cache; +}; + +extern struct list_head cbqri_controllers; + +#endif /* __LINUX_RISCV_QOS_H */ --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71FCDC77B73 for ; Wed, 19 Apr 2023 11:11:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232881AbjDSLLD (ORCPT ); Wed, 19 Apr 2023 07:11:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232849AbjDSLKv (ORCPT ); Wed, 19 Apr 2023 07:10:51 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C645513F9A for ; Wed, 19 Apr 2023 04:10:15 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-63b73203e0aso15252473b3a.1 for ; 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charset="utf-8" Define data structures to store the capacity and bandwidth capabilities that are discovered for a CBQRI-capable controller. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/internal.h | 130 +++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 arch/riscv/kernel/qos/internal.h diff --git a/arch/riscv/kernel/qos/internal.h b/arch/riscv/kernel/qos/inter= nal.h new file mode 100644 index 000000000000..e07d7f92e206 --- /dev/null +++ b/arch/riscv/kernel/qos/internal.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_RISCV_QOS_INTERNAL_H +#define _ASM_RISCV_QOS_INTERNAL_H + +#include + +#define CBQRI_CC_CAPABILITIES_OFF 0 +#define CBQRI_CC_MON_CTL_OFF 8 +#define CBQRI_CC_MON_CTL_VAL_OFF 16 +#define CBQRI_CC_ALLOC_CTL_OFF 24 +#define CBQRI_CC_BLOCK_MASK_OFF 32 + +#define CBQRI_BC_CAPABILITIES_OFF 0 +#define CBQRI_BC_MON_CTL_OFF 8 +#define CBQRI_BC_MON_CTR_VAL_OFF 16 +#define CBQRI_BC_ALLOC_CTL_OFF 24 +#define CBQRI_BC_BW_ALLOC_OFF 32 + +#define CBQRI_CC_CAPABILITIES_VER_MINOR_MASK GENMASK(3, 0) +#define CBQRI_CC_CAPABILITIES_VER_MAJOR_MASK GENMASK(7, 4) + +#define CBQRI_CC_CAPABILITIES_FRCID_MASK 0x1 +#define CBQRI_CC_CAPABILITIES_FRCID_SHIFT 24 + +#define CBQRI_CC_CAPABILITIES_NCBLKS_SHIFT 8 +#define CBQRI_CC_CAPABILITIES_NCBLKS_MASK 0xFFFF + +#define CBQRI_BC_CAPABILITIES_VER_MINOR_MASK GENMASK(3, 0) +#define CBQRI_BC_CAPABILITIES_VER_MAJOR_MASK GENMASK(7, 4) + +#define CBQRI_BC_CAPABILITIES_NBWBLKS_SHIFT 8 +#define CBQRI_BC_CAPABILITIES_NBWBLKS_MASK 0xFFFF +#define CBQRI_BC_CAPABILITIES_MRBWB_SHIFT 32 +#define CBQRI_BC_CAPABILITIES_MRBWB_MASK 0xFFFF + +#define CBQRI_CONTROL_REGISTERS_BUSY_SHIFT 39 +#define CBQRI_CONTROL_REGISTERS_BUSY_MASK 0x01 +#define CBQRI_CONTROL_REGISTERS_STATUS_SHIFT 32 +#define CBQRI_CONTROL_REGISTERS_STATUS_MASK 0x7F +#define CBQRI_CONTROL_REGISTERS_OP_SHIFT 0 +#define CBQRI_CONTROL_REGISTERS_OP_MASK 0x1F +#define CBQRI_CONTROL_REGISTERS_AT_SHIFT 5 +#define CBQRI_CONTROL_REGISTERS_AT_MASK 0x07 +#define CBQRI_CONTROL_REGISTERS_AT_DATA 0 +#define CBQRI_CONTROL_REGISTERS_AT_CODE 1 +#define CBQRI_CONTROL_REGISTERS_RCID_SHIFT 8 +#define CBQRI_CONTROL_REGISTERS_RCID_MASK 0xFFF +#define CBQRI_CONTROL_REGISTERS_RBWB_SHIFT 0 +#define CBQRI_CONTROL_REGISTERS_RBWB_MASK 0xFF + +#define CBQRI_CC_MON_CTL_OP_CONFIG_EVENT 1 +#define CBQRI_CC_MON_CTL_OP_READ_COUNTER 2 +#define CBQRI_CC_MON_CTL_STATUS_SUCCESS 1 + +#define CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT 1 +#define CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT 2 +#define CBQRI_CC_ALLOC_CTL_OP_FLUSH_RCID 3 +#define CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS 1 + +#define CBQRI_BC_MON_CTL_OP_CONFIG_EVENT 1 +#define CBQRI_BC_MON_CTL_OP_READ_COUNTER 2 +#define CBQRI_BC_MON_CTL_STATUS_SUCCESS 1 + +#define CBQRI_BC_ALLOC_CTL_OP_CONFIG_LIMIT 1 +#define CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT 2 +#define CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS 1 + +/* Capacity Controller hardware capabilities */ +/* from qemu/include/hw/riscv/cbqri.h */ +struct riscv_cbqri_capacity_caps { + u16 ncblks; + u16 cache_level; + u32 blk_size; + + bool supports_alloc_at_data; + bool supports_alloc_at_code; + + bool supports_alloc_op_config_limit; + bool supports_alloc_op_read_limit; + bool supports_alloc_op_flush_rcid; + + bool supports_mon_at_data; + bool supports_mon_at_code; + + bool supports_mon_op_config_event; + bool supports_mon_op_read_counter; + + bool supports_mon_evt_id_none; + bool supports_mon_evt_id_occupancy; +}; + +/* Bandwidth Controller hardware capabilities */ +/* from qemu/include/hw/riscv/cbqri.h */ +struct riscv_cbqri_bandwidth_caps { + u16 nbwblks; /* number of bandwidth block */ + u16 mrbwb; /* max reserved bw blocks */ + + bool supports_alloc_at_data; + bool supports_alloc_at_code; + + bool supports_alloc_op_config_limit; + bool supports_alloc_op_read_limit; + + bool supports_mon_at_data; + bool supports_mon_at_code; + + bool supports_mon_op_config_event; + bool supports_mon_op_read_counter; + + bool supports_mon_evt_id_none; + bool supports_mon_evt_id_rdwr_count; + bool supports_mon_evt_id_rdonly_count; + bool supports_mon_evt_id_wronly_count; +}; + +struct cbqri_controller { + struct cbqri_controller_info *ctrl_info; + void __iomem *base; + + int ver_major; + int ver_minor; + + struct riscv_cbqri_bandwidth_caps bc; + struct riscv_cbqri_capacity_caps cc; + + bool alloc_capable; + bool mon_capable; +}; + +#endif /* _ASM_RISCV_QOS_INTERNAL_H */ --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C136C77B75 for ; Wed, 19 Apr 2023 11:11:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232895AbjDSLLF (ORCPT ); Wed, 19 Apr 2023 07:11:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232867AbjDSLLB (ORCPT ); Wed, 19 Apr 2023 07:11:01 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD2BF7A88 for ; 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Wed, 19 Apr 2023 04:10:16 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 05/21] RISC-V: QoS: define prototypes for resctrl interface Date: Wed, 19 Apr 2023 04:10:55 -0700 Message-Id: <20230419111111.477118-6-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Define the prototypes for the resctrl interface functions that are implemented on RISC-V. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- include/linux/riscv_qos.h | 58 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/include/linux/riscv_qos.h b/include/linux/riscv_qos.h index 95016810b575..537e503a8e99 100644 --- a/include/linux/riscv_qos.h +++ b/include/linux/riscv_qos.h @@ -3,6 +3,7 @@ #ifndef __LINUX_RISCV_QOS_H #define __LINUX_RISCV_QOS_H =20 +#include #include #include =20 @@ -31,4 +32,61 @@ struct cbqri_controller_info { =20 extern struct list_head cbqri_controllers; =20 +bool resctrl_arch_alloc_capable(void); +bool resctrl_arch_mon_capable(void); +bool resctrl_arch_is_llc_occupancy_enabled(void); +bool resctrl_arch_is_mbm_local_enabled(void); +bool resctrl_arch_is_mbm_total_enabled(void); + +struct rdt_resource; +/* + * Note about terminology between x86 (Intel RDT/AMD QoS) and RISC-V: + * CLOSID on x86 is RCID on RISC-V + * RMID on x86 is MCID on RISC-V + * CDP on x86 is AT (access type) on RISC-V + */ +bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level ignored); +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid); +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid= ); +int resctrl_arch_mon_ctx_alloc_no_wait(struct rdt_resource *r, int evtid); +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, int evtid, int ctx); +void resctrl_arch_reset_resources(void); +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid); +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid); +int resctrl_arch_set_cdp_enabled(enum resctrl_res_level ignored, bool ena= ble); +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32= rmid); +void resctrl_arch_set_cpu_default_closid(int cpu, u32 closid); +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 pmg= ); +u32 resctrl_arch_system_num_rmid_idx(void); +void resctrl_sched_in(void); + +static inline bool resctrl_arch_event_is_free_running(enum resctrl_event_i= d evt) +{ + /* must be true for resctrl L3 monitoring files to be created */ + return true; +} + +static inline unsigned int resctrl_arch_round_mon_val(unsigned int val) +{ + return val; +} + +/* Pseudo lock is not supported on RISC-V */ +static inline int resctrl_arch_pseudo_lock_fn(void *_plr) { return 0; } +static inline int resctrl_arch_measure_l2_residency(void *_plr) { return 0= ; } +static inline int resctrl_arch_measure_l3_residency(void *_plr) { return 0= ; } +static inline int resctrl_arch_measure_cycles_lat_fn(void *_plr) { return = 0; } +static inline u64 resctrl_arch_get_prefetch_disable_bits(void) { return 0;= } + +/* Not needed for RISC-V */ +bool resctrl_arch_match_iommu_closid(struct iommu_group *group, u32 closid= ); +bool resctrl_arch_match_iommu_closid_rmid(struct iommu_group *group, u32 c= losid, u32 rmid); +int resctrl_arch_set_iommu_closid_rmid(struct iommu_group *group, u32 clo= sid, u32 rmid); + +/* Not needed for RISC-V */ +static inline void resctrl_arch_enable_mon(void) { } +static inline void resctrl_arch_disable_mon(void) { } +static inline void resctrl_arch_enable_alloc(void) { } +static inline void resctrl_arch_disable_alloc(void) { } + #endif /* __LINUX_RISCV_QOS_H */ --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D237EC77B73 for ; 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charset="utf-8" Define data structures to encapsulate the resctrl resource and domain structures. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/internal.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/riscv/kernel/qos/internal.h b/arch/riscv/kernel/qos/inter= nal.h index e07d7f92e206..a3ed98ce5dd6 100644 --- a/arch/riscv/kernel/qos/internal.h +++ b/arch/riscv/kernel/qos/internal.h @@ -65,6 +65,11 @@ #define CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT 2 #define CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS 1 =20 +int qos_resctrl_setup(void); +void qos_resctrl_exit(void); +int qos_resctrl_online_cpu(unsigned int cpu); +int qos_resctrl_offline_cpu(unsigned int cpu); + /* Capacity Controller hardware capabilities */ /* from qemu/include/hw/riscv/cbqri.h */ struct riscv_cbqri_capacity_caps { @@ -127,4 +132,26 @@ struct cbqri_controller { bool mon_capable; }; =20 +struct cbqri_resctrl_res { + struct rdt_resource resctrl_res; + struct cbqri_controller controller; + u32 max_rcid; + u32 max_mcid; +}; + +struct cbqri_resctrl_dom { + struct rdt_domain resctrl_dom; + // NCBLKS is 16 bit which is 2^16 =3D 65536 + // If each bit is a block, then cc_block_mask could 1024 times 64 byte + u64 cbm; + u64 rbwb; + u64 *ctrl_val; + struct cbqri_controller *hw_ctrl; +}; + +struct cbqri_config { + u64 cbm; /* capacity block mask */ + u64 rbwb; /* reserved bandwidth blocks */ +}; + #endif /* _ASM_RISCV_QOS_INTERNAL_H */ --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AD65C6FD18 for ; Wed, 19 Apr 2023 11:11:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232877AbjDSLLT (ORCPT ); Wed, 19 Apr 2023 07:11:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232897AbjDSLLG (ORCPT ); Wed, 19 Apr 2023 07:11:06 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B7AA13C02 for ; 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Wed, 19 Apr 2023 04:10:19 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 07/21] RISC-V: QoS: add resctrl interface for CBQRI controllers Date: Wed, 19 Apr 2023 04:10:57 -0700 Message-Id: <20230419111111.477118-8-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add interface for CBQRI controller drivers to make use of the resctrl filesystem. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/qos_resctrl.c | 1231 +++++++++++++++++++++++++++ 1 file changed, 1231 insertions(+) create mode 100644 arch/riscv/kernel/qos/qos_resctrl.c diff --git a/arch/riscv/kernel/qos/qos_resctrl.c b/arch/riscv/kernel/qos/qo= s_resctrl.c new file mode 100644 index 000000000000..f4116d9a9f04 --- /dev/null +++ b/arch/riscv/kernel/qos/qos_resctrl.c @@ -0,0 +1,1231 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2023 Rivos Inc. + +#define pr_fmt(fmt) "qos: resctrl: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include "internal.h" + +#define MAX_CONTROLLERS 6 +static struct cbqri_resctrl_res cbqri_resctrl_resources[RDT_NUM_RESOURCES]; +/* + * The size of the controllers array reflects that number of CBQRI control= lers + * (3x capacity, 3x bandwidth) in the hypothetical SoC that Qemu implement= s for + * the CBQRI proof-of-concept. + * + * The proper solution will involve dynamically allocating cbqri_controller + * structures and adding them to a list of controllers. This avoids having= to + * make assumptions about the system. + */ +static struct cbqri_controller controllers[MAX_CONTROLLERS]; +static int found_controllers; + +static bool exposed_alloc_capable; +static bool exposed_mon_capable; +/* CDP (code data prioritization) on x86 is AT (access type) on RISC-V */ +static bool exposed_cdp_l2_capable; +static bool exposed_cdp_l3_capable; +static bool is_cdp_l2_enabled; +static bool is_cdp_l3_enabled; + +/* used by resctrl_arch_system_num_rmid_idx() */ +static u32 max_rmid; + +LIST_HEAD(cbqri_controllers); + +static int qos_wait_busy_flag(struct cbqri_controller *ctrl, int reg_offse= t); + +bool resctrl_arch_alloc_capable(void) +{ + return exposed_alloc_capable; +} + +bool resctrl_arch_mon_capable(void) +{ + return exposed_mon_capable; +} + +bool resctrl_arch_is_mbm_local_enabled(void) +{ + /* + * Seems to be the bandwidth between a L2 cache and L3 cache + * according to Intel resctrl implementation. There is no meaning + * in supporting such stat when we use resctrl MON_DATA feature + * to support CBQRI bandwidth monitoring. + */ + return false; +} + +bool resctrl_arch_is_mbm_total_enabled(void) +{ + return true; +} + +bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level rid) +{ + switch (rid) { + case RDT_RESOURCE_L2: + return is_cdp_l2_enabled; + + case RDT_RESOURCE_L3: + return is_cdp_l3_enabled; + + default: + return false; + } +} + +int resctrl_arch_set_cdp_enabled(enum resctrl_res_level rid, bool enable) +{ + switch (rid) { + case RDT_RESOURCE_L2: + if (!exposed_cdp_l2_capable) + return -ENODEV; + is_cdp_l2_enabled =3D enable; + break; + + case RDT_RESOURCE_L3: + if (!exposed_cdp_l3_capable) + return -ENODEV; + is_cdp_l3_enabled =3D enable; + break; + + default: + return -ENODEV; + } + + return 0; +} + +bool resctrl_arch_is_llc_occupancy_enabled(void) +{ + /* + * There is no occupancy in CBQRI bandwidth controller (resctrl MON_DATA + * was the only available way to implement RISC-V memory monitoring). + * As we need occupancy for CBQRI capacity controller, this global + * setting is true, but the ll_occupancy files of CBQRI bandwidth + * controllers will return an error. + */ + return true; +} + +/* + * Note about terminology between x86 (Intel RDT/AMD QoS) and RISC-V: + * CLOSID on x86 is RCID on RISC-V + * RMID on x86 is MCID on RISC-V + */ +u32 resctrl_arch_get_num_closid(struct rdt_resource *res) +{ + struct cbqri_resctrl_res *hw_res; + + hw_res =3D container_of(res, struct cbqri_resctrl_res, resctrl_res); + + return hw_res->max_rcid; +} + +u32 resctrl_arch_system_num_rmid_idx(void) +{ + return max_rmid; +} + +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid) +{ + return rmid; +} + +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid) +{ + *closid =3D ((u32)~0); /* refer to X86_RESCTRL_BAD_CLOSID */ + *rmid =3D idx; +} + +/* RISC-V resctrl interface does not maintain a default sqoscfg value for = a given CPU */ +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 rmi= d) { } + +void resctrl_sched_in(void) +{ + qos_sched_in(current); +} + +void resctrl_arch_sync_cpu_defaults(void *info) +{ + resctrl_sched_in(); +} + +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32= rmid) +{ + u32 sqoscfg; + + WARN_ON_ONCE((closid & SQOSCFG_RCID_MASK) !=3D closid); + WARN_ON_ONCE((rmid & SQOSCFG_MCID_MASK) !=3D rmid); + + sqoscfg =3D rmid << SQOSCFG_MCID_SHIFT; + sqoscfg |=3D closid; + WRITE_ONCE(tsk->thread.sqoscfg, sqoscfg); +} + +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid) +{ + u32 sqoscfg; + bool match; + + sqoscfg =3D READ_ONCE(tsk->thread.sqoscfg); + match =3D (sqoscfg & SQOSCFG_RCID_MASK) =3D=3D closid; + return match; +} + +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid) +{ + u32 tsk_rmid; + + tsk_rmid =3D READ_ONCE(tsk->thread.sqoscfg); + tsk_rmid >>=3D SQOSCFG_MCID_SHIFT; + tsk_rmid &=3D SQOSCFG_MCID_MASK; + + return tsk_rmid =3D=3D rmid; +} + +struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) +{ + if (l >=3D RDT_NUM_RESOURCES) + return NULL; + + return &cbqri_resctrl_resources[l].resctrl_res; +} + +struct rdt_domain *resctrl_arch_find_domain(struct rdt_resource *r, int id) +{ + struct rdt_domain *domain; + struct list_head *l; + + list_for_each(l, &r->domains) { + domain =3D list_entry(l, struct rdt_domain, list); + if (id =3D=3D domain->id) + return domain; + } + + return NULL; +} + +void resctrl_arch_reset_resources(void) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +int resctrl_arch_mon_ctx_alloc_no_wait(struct rdt_resource *r, int evtid) +{ + /* RISC-V can always read an rmid, nothing needs allocating */ + return 0; +} + +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, int evtid, int ctx) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt) +{ + return false; +} + +int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain *d, + u32 closid, u32 rmid, enum resctrl_event_id eventid, + u64 *val, int arch_mon_ctx) +{ + /* + * The current Qemu implementation of CBQRI capacity and bandwidth + * controllers do not emulate the utilization of resources over + * time. Therefore, Qemu currently sets the invalid bit in + * cc_mon_ctr_val and bc_mon_ctr_val, and there is no meaningful + * value other than 0 to return for reading an RMID (e.g. MCID in + * CBQRI terminology) + */ + + return 0; +} + +void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_domain *d, + u32 closid, u32 rmid, enum resctrl_event_id eventid) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +void resctrl_arch_mon_event_config_read(void *info) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +void resctrl_arch_mon_event_config_write(void *info) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_domain= *d) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +/* Set capacity block mask (cc_block_mask) */ +static void cbqri_set_cbm(struct cbqri_controller *ctrl, u64 cbm) +{ + int reg_offset; + u64 reg; + + reg_offset =3D CBQRI_CC_BLOCK_MASK_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + + reg =3D cbm; + iowrite64(reg, ctrl->base + reg_offset); + + reg =3D ioread64(ctrl->base + reg_offset); +} + +/* Set the Rbwb (reserved bandwidth blocks) field in bc_bw_alloc */ +static void cbqri_set_rbwb(struct cbqri_controller *ctrl, u64 rbwb) +{ + int reg_offset; + u64 reg; + + reg_offset =3D CBQRI_BC_BW_ALLOC_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + reg |=3D rbwb & CBQRI_CONTROL_REGISTERS_RBWB_MASK; + iowrite64(reg, ctrl->base + reg_offset); +} + +/* Get the Rbwb (reserved bandwidth blocks) field in bc_bw_alloc */ +static u64 cbqri_get_rbwb(struct cbqri_controller *ctrl) +{ + int reg_offset; + u64 reg; + + reg_offset =3D CBQRI_BC_BW_ALLOC_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + reg &=3D CBQRI_CONTROL_REGISTERS_RBWB_MASK; + + return reg; +} + +static int qos_wait_busy_flag(struct cbqri_controller *ctrl, int reg_offse= t) +{ + unsigned long timeout =3D jiffies + (HZ / 10); /* Timeout after 100ms */ + u64 reg; + int busy; + + while (time_before(jiffies, timeout)) { + reg =3D ioread64(ctrl->base + reg_offset); + busy =3D (reg >> CBQRI_CONTROL_REGISTERS_BUSY_SHIFT) & + CBQRI_CONTROL_REGISTERS_BUSY_MASK; + if (!busy) + return 0; + } + + pr_warn("%s(): busy timeout", __func__); + return -EIO; +} + +/* Perform operation on capacity controller */ +static int do_capacity_alloc_op(struct cbqri_controller *ctrl, int operati= on, + enum resctrl_conf_type type, int rcid) +{ + int reg_offset =3D CBQRI_CC_ALLOC_CTL_OFF; + int status; + u64 reg; + + reg =3D ioread64(ctrl->base + reg_offset); + reg &=3D ~(CBQRI_CONTROL_REGISTERS_OP_MASK << CBQRI_CONTROL_REGISTERS_OP_= SHIFT); + reg |=3D (operation & CBQRI_CONTROL_REGISTERS_OP_MASK) << + CBQRI_CONTROL_REGISTERS_OP_SHIFT; + reg &=3D ~(CBQRI_CONTROL_REGISTERS_RCID_MASK << + CBQRI_CONTROL_REGISTERS_RCID_SHIFT); + reg |=3D (rcid & CBQRI_CONTROL_REGISTERS_RCID_MASK) << + CBQRI_CONTROL_REGISTERS_RCID_SHIFT; + + /* CBQRI capacity AT is only supported on caches for now */ + if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY && + ((ctrl->ctrl_info->cache.cache_level =3D=3D 2 && is_cdp_l2_enabled) || + (ctrl->ctrl_info->cache.cache_level =3D=3D 3 && is_cdp_l3_enabled))) { + reg &=3D ~(CBQRI_CONTROL_REGISTERS_AT_MASK << + CBQRI_CONTROL_REGISTERS_AT_SHIFT); + switch (type) { + case CDP_CODE: + reg |=3D (CBQRI_CONTROL_REGISTERS_AT_CODE & + CBQRI_CONTROL_REGISTERS_AT_MASK) << + CBQRI_CONTROL_REGISTERS_AT_SHIFT; + break; + case CDP_DATA: + default: + reg |=3D (CBQRI_CONTROL_REGISTERS_AT_DATA & + CBQRI_CONTROL_REGISTERS_AT_MASK) << + CBQRI_CONTROL_REGISTERS_AT_SHIFT; + break; + } + } + + iowrite64(reg, ctrl->base + reg_offset); + + if (qos_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when executing the operation", __func__); + return -EIO; + } + + reg =3D ioread64(ctrl->base + reg_offset); + status =3D (reg >> CBQRI_CONTROL_REGISTERS_STATUS_SHIFT) & + CBQRI_CONTROL_REGISTERS_STATUS_MASK; + if (status !=3D 1) { + pr_err("%s(): operation %d failed: status=3D%d", __func__, operation, st= atus); + return -EIO; + } + + return 0; +} + +/* Perform operation on bandwidth controller */ +static int do_bandwidth_alloc_op(struct cbqri_controller *ctrl, int operat= ion, int rcid) +{ + int reg_offset =3D CBQRI_BC_ALLOC_CTL_OFF; + int status; + u64 reg; + + reg =3D ioread64(ctrl->base + reg_offset); + reg &=3D ~(CBQRI_CONTROL_REGISTERS_OP_MASK << CBQRI_CONTROL_REGISTERS_OP_= SHIFT); + reg |=3D (operation & CBQRI_CONTROL_REGISTERS_OP_MASK) << + CBQRI_CONTROL_REGISTERS_OP_SHIFT; + reg &=3D ~(CBQRI_CONTROL_REGISTERS_RCID_MASK << CBQRI_CONTROL_REGISTERS_R= CID_SHIFT); + reg |=3D (rcid & CBQRI_CONTROL_REGISTERS_RCID_MASK) << + CBQRI_CONTROL_REGISTERS_RCID_SHIFT; + iowrite64(reg, ctrl->base + reg_offset); + + if (qos_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when executing the operation", __func__); + return -EIO; + } + + reg =3D ioread64(ctrl->base + reg_offset); + status =3D (reg >> CBQRI_CONTROL_REGISTERS_STATUS_SHIFT) & + CBQRI_CONTROL_REGISTERS_STATUS_MASK; + if (status !=3D 1) { + pr_err("%s(): operation %d failed with status =3D %d", + __func__, operation, status); + return -EIO; + } + + return 0; +} + +static int cbqri_apply_bw_config(struct cbqri_resctrl_dom *hw_dom, u32 clo= sid, + enum resctrl_conf_type type, struct cbqri_config *cfg) +{ + struct cbqri_controller *ctrl =3D hw_dom->hw_ctrl; + int ret =3D 0; + u64 rbwb; + + if (cfg->cbm !=3D hw_dom->ctrl_val[closid]) { + /* Store the new rbwb in the ctrl_val array for this closid in this doma= in */ + hw_dom->ctrl_val[closid] =3D cfg->rbwb; + + /* set reserved bandwidth blocks */ + cbqri_set_rbwb(ctrl, cfg->rbwb); + /* get reserved bandwidth blocks */ + rbwb =3D cbqri_get_rbwb(ctrl); + + /* Capacity config limit operation for RCID (closid) */ + ret =3D do_capacity_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT, t= ype, closid); + if (ret < 0) { + pr_err("%s(): operation failed: ret =3D %d", __func__, ret); + return ret; + } + + /* Clear rbwb before read limit to verify op works*/ + cbqri_set_rbwb(ctrl, 0); + + /* Bandwidth allocation read limit operation for RCID (closid) to verify= */ + ret =3D do_capacity_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, typ= e, closid); + if (ret < 0) { + pr_err("%s(): operation failed: ret =3D %d", __func__, ret); + return ret; + } + + /* Read capacity block mask for RCID (closid) to verify */ + rbwb =3D cbqri_get_rbwb(ctrl); + } + + return ret; +} + +static int cbqri_apply_cache_config(struct cbqri_resctrl_dom *hw_dom, u32 = closid, + enum resctrl_conf_type type, struct cbqri_config *cfg) +{ + struct cbqri_controller *ctrl =3D hw_dom->hw_ctrl; + int reg_offset, err =3D 0; + u64 reg; + + if (cfg->cbm !=3D hw_dom->ctrl_val[closid]) { + /* store the new cbm in the ctrl_val array for this closid in this domai= n */ + hw_dom->ctrl_val[closid] =3D cfg->cbm; + + /* set capacity block mask (cc_block_mask) */ + cbqri_set_cbm(ctrl, cfg->cbm); + + /* Capacity config limit operation for RCID (closid) */ + err =3D do_capacity_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT, t= ype, closid); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return err; + } + + /* clear cc_block_mask before read limit to verify op works*/ + cbqri_set_cbm(ctrl, 0); + + /* Capacity read limit operation for RCID (closid) to verify */ + err =3D do_capacity_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, typ= e, closid); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return err; + } + + /* Read capacity block mask for RCID (closid) to verify */ + reg_offset =3D CBQRI_CC_BLOCK_MASK_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + } + + return err; +} + +int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_domain *d, + u32 closid, enum resctrl_conf_type t, u32 cfg_val) +{ + struct cbqri_resctrl_res *res; + struct cbqri_resctrl_dom *dom; + struct cbqri_config cfg; + int err =3D 0; + + res =3D container_of(r, struct cbqri_resctrl_res, resctrl_res); + dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_dom); + + if (!r->alloc_capable) + return -EINVAL; + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + cfg.cbm =3D cfg_val; + err =3D cbqri_apply_cache_config(dom, closid, t, &cfg); + break; + case RDT_RESOURCE_MBA: + cfg.rbwb =3D cfg_val; + err =3D cbqri_apply_bw_config(dom, closid, t, &cfg); + break; + default: + return -EINVAL; + } + + return err; +} + +int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid) +{ + struct resctrl_staged_config *cfg; + enum resctrl_conf_type t; + struct rdt_domain *d; + int err =3D 0; + + list_for_each_entry(d, &r->domains, list) { + for (t =3D 0; t < CDP_NUM_TYPES; t++) { + cfg =3D &d->staged_config[t]; + if (!cfg->have_new_ctrl) + continue; + err =3D resctrl_arch_update_one(r, d, closid, t, cfg->new_ctrl); + if (err) { + pr_debug("%s(): return err=3D%d", __func__, err); + return err; + } + } + } + return err; +} + +u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_domain *d, + u32 closid, enum resctrl_conf_type type) +{ + struct cbqri_resctrl_res *hw_res; + struct cbqri_resctrl_dom *hw_dom; + struct cbqri_controller *ctrl; + int reg_offset; + int err; + u64 reg; + + hw_res =3D container_of(r, struct cbqri_resctrl_res, resctrl_res); + hw_dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_dom); + + ctrl =3D hw_dom->hw_ctrl; + + if (!r->alloc_capable) + return -EINVAL; + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + + /* Clear cc_block_mask before read limit operation */ + cbqri_set_cbm(ctrl, 0); + + /* Capacity read limit operation for RCID (closid) */ + err =3D do_capacity_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, typ= e, closid); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return -EIO; + } + + /* Read capacity block mask for RCID (closid) */ + reg_offset =3D CBQRI_CC_BLOCK_MASK_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + + /* Update the config value for the closid in this domain */ + hw_dom->ctrl_val[closid] =3D reg; + + return hw_dom->ctrl_val[closid]; + + case RDT_RESOURCE_MBA: + + /* Capacity read limit operation for RCID (closid) */ + err =3D do_bandwidth_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, cl= osid); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return -EIO; + } + + hw_dom->ctrl_val[closid] =3D cbqri_get_rbwb(ctrl); + + return hw_dom->ctrl_val[closid]; + + default: + return -EINVAL; + } +} + +static int qos_discover_controller_feature(struct cbqri_controller *ctrl, + int reg_offset, + int operation, + int *status, + bool *access_type_supported) +{ + u64 reg, saved_reg; + int at; + + /* Keep the initial register value to preserve the WPRI fields */ + reg =3D ioread64(ctrl->base + reg_offset); + saved_reg =3D reg; + + /* Execute the requested operation to find if the register is implemented= */ + reg &=3D ~(CBQRI_CONTROL_REGISTERS_OP_MASK << CBQRI_CONTROL_REGISTERS_OP_= SHIFT); + reg |=3D (operation & CBQRI_CONTROL_REGISTERS_OP_MASK) << CBQRI_CONTROL_R= EGISTERS_OP_SHIFT; + iowrite64(reg, ctrl->base + reg_offset); + if (qos_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when executing the operation", __func__); + return -EIO; + } + + /* Get the operation status */ + reg =3D ioread64(ctrl->base + reg_offset); + *status =3D (reg >> CBQRI_CONTROL_REGISTERS_STATUS_SHIFT) & + CBQRI_CONTROL_REGISTERS_STATUS_MASK; + + /* + * Check for the AT support if the register is implemented + * (if not, the status value will remain 0) + */ + if (*status !=3D 0) { + /* Set the AT field to a valid value */ + reg =3D saved_reg; + reg &=3D ~(CBQRI_CONTROL_REGISTERS_AT_MASK << CBQRI_CONTROL_REGISTERS_AT= _SHIFT); + reg |=3D CBQRI_CONTROL_REGISTERS_AT_CODE << CBQRI_CONTROL_REGISTERS_AT_S= HIFT; + iowrite64(reg, ctrl->base + reg_offset); + if (qos_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when setting AT field", __func__); + return -EIO; + } + + /* + * If the AT field value has been reset to zero, + * then the AT support is not present + */ + reg =3D ioread64(ctrl->base + reg_offset); + at =3D (reg >> CBQRI_CONTROL_REGISTERS_AT_SHIFT) & CBQRI_CONTROL_REGISTE= RS_AT_MASK; + if (at =3D=3D CBQRI_CONTROL_REGISTERS_AT_CODE) + *access_type_supported =3D true; + else + *access_type_supported =3D false; + } + + /* Restore the original register value */ + iowrite64(saved_reg, ctrl->base + reg_offset); + if (qos_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when restoring the original register value", = __func__); + return -EIO; + } + + return 0; +} + +/* + * Note: for the purposes of the CBQRI proof-of-concept, debug logging + * has been left in this function that discovers the properties of CBQRI + * capable controllers in the system. pr_debug calls would be removed + * before submitting non-RFC patches. + */ +static int qos_resctrl_discover_controller(struct cbqri_controller_info *c= trl_info, + struct cbqri_controller *ctrl) +{ + int err =3D 0, status; + u64 reg; + + pr_debug("controller info: type=3D%d addr=3D0x%lx size=3D%lu max-rcid=3D%= u max-mcid=3D%u", + ctrl_info->type, ctrl_info->addr, ctrl_info->size, + ctrl_info->rcid_count, ctrl_info->mcid_count); + + /* max_rmid is used by resctrl_arch_system_num_rmid_idx() */ + max_rmid =3D ctrl_info->mcid_count; + + ctrl->ctrl_info =3D ctrl_info; + + /* Try to access the memory-mapped CBQRI registers */ + if (!request_mem_region(ctrl_info->addr, ctrl_info->size, "cbqri_controll= er")) { + pr_debug("%s(): return %d", __func__, err); + return err; + } + ctrl->base =3D ioremap(ctrl_info->addr, ctrl_info->size); + if (!ctrl->base) { + pr_debug("%s(): goto err_release_mem_region", __func__); + goto err_release_mem_region; + } + + ctrl->alloc_capable =3D false; + ctrl->mon_capable =3D false; + + /* Discover capacity allocation and monitoring features */ + if (ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY) { + pr_debug("probe capacity controller"); + + /* Make sure the register is implemented */ + reg =3D ioread64(ctrl->base + CBQRI_CC_CAPABILITIES_OFF); + if (reg =3D=3D 0) { + err =3D -ENODEV; + goto err_iounmap; + } + + ctrl->ver_minor =3D reg & CBQRI_CC_CAPABILITIES_VER_MINOR_MASK; + ctrl->ver_major =3D reg & CBQRI_CC_CAPABILITIES_VER_MAJOR_MASK; + + ctrl->cc.supports_alloc_op_flush_rcid =3D (reg >> CBQRI_CC_CAPABILITIES_= FRCID_SHIFT) + & CBQRI_CC_CAPABILITIES_FRCID_MASK; + + ctrl->cc.ncblks =3D (reg >> CBQRI_CC_CAPABILITIES_NCBLKS_SHIFT) & + CBQRI_CC_CAPABILITIES_NCBLKS_MASK; + + /* Calculate size of capacity block in bytes */ + ctrl->cc.blk_size =3D ctrl_info->cache.cache_size / ctrl->cc.ncblks; + ctrl->cc.cache_level =3D ctrl_info->cache.cache_level; + + pr_debug("version=3D%d.%d ncblks=3D%d blk_size=3D%d cache_level=3D%d", + ctrl->ver_major, ctrl->ver_minor, + ctrl->cc.ncblks, ctrl->cc.blk_size, ctrl->cc.cache_level); + + /* Discover monitoring features */ + err =3D qos_discover_controller_feature(ctrl, CBQRI_CC_MON_CTL_OFF, + CBQRI_CC_MON_CTL_OP_READ_COUNTER, + &status, &ctrl->cc.supports_mon_at_code); + if (err) { + pr_err("%s() failed to discover cc_mon_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_CC_MON_CTL_STATUS_SUCCESS) { + pr_debug("cc_mon_ctl is supported"); + ctrl->cc.supports_mon_op_config_event =3D true; + ctrl->cc.supports_mon_op_read_counter =3D true; + ctrl->mon_capable =3D true; + } else { + pr_debug("cc_mon_ctl is NOT supported"); + ctrl->cc.supports_mon_op_config_event =3D false; + ctrl->cc.supports_mon_op_read_counter =3D false; + ctrl->mon_capable =3D false; + } + /* + * AT data is "always" supported as it has the same value + * than when AT field is not supported. + */ + ctrl->cc.supports_mon_at_data =3D true; + pr_debug("supports_mon_at_data: %d, supports_mon_at_code: %d", + ctrl->cc.supports_mon_at_data, ctrl->cc.supports_mon_at_code); + + /* Discover allocation features */ + err =3D qos_discover_controller_feature(ctrl, CBQRI_CC_ALLOC_CTL_OFF, + CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, + &status, &ctrl->cc.supports_alloc_at_code); + if (err) { + pr_err("%s() failed to discover cc_alloc_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS) { + pr_debug("cc_alloc_ctl is supported"); + ctrl->cc.supports_alloc_op_config_limit =3D true; + ctrl->cc.supports_alloc_op_read_limit =3D true; + ctrl->alloc_capable =3D true; + exposed_alloc_capable =3D true; + } else { + pr_debug("cc_alloc_ctl is NOT supported"); + ctrl->cc.supports_alloc_op_config_limit =3D false; + ctrl->cc.supports_alloc_op_read_limit =3D false; + ctrl->alloc_capable =3D false; + } + /* + * AT data is "always" supported as it has the same value + * than when AT field is not supported + */ + ctrl->cc.supports_alloc_at_data =3D true; + pr_debug("supports_alloc_at_data: %d, supports_alloc_at_code: %d", + ctrl->cc.supports_alloc_at_data, + ctrl->cc.supports_alloc_at_code); + } else if (ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) { + pr_debug("probe bandwidth controller"); + + /* Make sure the register is implemented */ + reg =3D ioread64(ctrl->base + CBQRI_BC_CAPABILITIES_OFF); + if (reg =3D=3D 0) { + err =3D -ENODEV; + goto err_iounmap; + } + + ctrl->ver_minor =3D reg & CBQRI_BC_CAPABILITIES_VER_MINOR_MASK; + ctrl->ver_major =3D reg & CBQRI_BC_CAPABILITIES_VER_MAJOR_MASK; + + ctrl->bc.nbwblks =3D (reg >> CBQRI_BC_CAPABILITIES_NBWBLKS_SHIFT) & + CBQRI_BC_CAPABILITIES_NBWBLKS_MASK; + ctrl->bc.mrbwb =3D (reg >> CBQRI_BC_CAPABILITIES_MRBWB_SHIFT) & + CBQRI_BC_CAPABILITIES_MRBWB_MASK; + + pr_debug("version=3D%d.%d nbwblks=3D%d mrbwb=3D%d", + ctrl->ver_major, ctrl->ver_minor, + ctrl->bc.nbwblks, ctrl->bc.mrbwb); + + // Discover monitoring features + err =3D qos_discover_controller_feature(ctrl, CBQRI_BC_MON_CTL_OFF, + CBQRI_BC_MON_CTL_OP_READ_COUNTER, + &status, &ctrl->bc.supports_mon_at_code); + if (err) { + pr_err("%s() failed to discover bc_mon_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_BC_MON_CTL_STATUS_SUCCESS) { + pr_debug("bc_mon_ctl is supported"); + ctrl->bc.supports_mon_op_config_event =3D true; + ctrl->bc.supports_mon_op_read_counter =3D true; + ctrl->mon_capable =3D true; + exposed_mon_capable =3D true; + } else { + pr_debug("bc_mon_ctl is NOT supported"); + ctrl->bc.supports_mon_op_config_event =3D false; + ctrl->bc.supports_mon_op_read_counter =3D false; + ctrl->mon_capable =3D false; + } + // AT data is "always" supported as it has the same value + // than when AT field is not supported + ctrl->bc.supports_mon_at_data =3D true; + pr_debug("supports_mon_at_data: %d, supports_mon_at_code: %d", + ctrl->bc.supports_mon_at_data, ctrl->bc.supports_mon_at_code); + + // Discover allocation features + err =3D qos_discover_controller_feature(ctrl, CBQRI_BC_ALLOC_CTL_OFF, + CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT, + &status, &ctrl->bc.supports_alloc_at_code); + if (err) { + pr_err("%s() failed to discover bc_alloc_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS) { + pr_debug("bc_alloc_ctl is supported"); + ctrl->bc.supports_alloc_op_config_limit =3D true; + ctrl->bc.supports_alloc_op_read_limit =3D true; + ctrl->alloc_capable =3D true; + exposed_alloc_capable =3D true; + } else { + pr_debug("bc_alloc_ctl is NOT supported"); + ctrl->bc.supports_alloc_op_config_limit =3D false; + ctrl->bc.supports_alloc_op_read_limit =3D false; + ctrl->alloc_capable =3D false; + } + + /* + * AT data is "always" supported as it has the same value + * than when AT field is not supported + */ + ctrl->bc.supports_alloc_at_data =3D true; + pr_debug("supports_alloc_at_data: %d, supports_alloc_at_code: %d", + ctrl->bc.supports_alloc_at_data, ctrl->bc.supports_alloc_at_code); + } else { + pr_err("controller type is UNKNOWN"); + err =3D -ENODEV; + goto err_release_mem_region; + } + + return 0; + +err_iounmap: + pr_err("%s(): err_iounmap", __func__); + iounmap(ctrl->base); + +err_release_mem_region: + pr_err("%s(): err_release_mem_region", __func__); + release_mem_region(ctrl_info->addr, ctrl_info->size); + + return err; +} + +static struct rdt_domain *qos_new_domain(struct cbqri_controller *ctrl) +{ + struct cbqri_resctrl_dom *hw_dom; + struct rdt_domain *domain; + + hw_dom =3D kzalloc(sizeof(*hw_dom), GFP_KERNEL); + if (!hw_dom) + return NULL; + + /* associate this cbqri_controller with the domain */ + hw_dom->hw_ctrl =3D ctrl; + + /* the rdt_domain struct from inside the cbqri_resctrl_dom struct */ + domain =3D &hw_dom->resctrl_dom; + + INIT_LIST_HEAD(&domain->list); + + return domain; +} + +static int qos_bw_blocks_to_percentage(struct cbqri_controller *ctrl, int = blocks) +{ + int percentage; + + if (ctrl->ctrl_info->type !=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) + return -1; + + blocks *=3D 100; + percentage =3D blocks / ctrl->bc.nbwblks; + if (blocks % ctrl->bc.nbwblks) + percentage++; + + return percentage; +} + +static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain = *d) +{ + struct cbqri_resctrl_res *hw_res; + struct cbqri_resctrl_dom *hw_dom; + u64 *dc; + int i; + + hw_res =3D container_of(r, struct cbqri_resctrl_res, resctrl_res); + hw_dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_dom); + + dc =3D kmalloc_array(hw_res->max_rcid, sizeof(*hw_dom->ctrl_val), + GFP_KERNEL); + if (!dc) + return -ENOMEM; + + hw_dom->ctrl_val =3D dc; + + for (i =3D 0; i < hw_res->max_rcid; i++, dc++) + *dc =3D r->default_ctrl; + + /* + * The Qemu implementation for the CBQRI proof-of-concept has + * known reset values for all registers. A proper solution would + * be to perform a CONFIG_LIMIT operation to set the default for + * each RCID + */ + return 0; +} + +static int qos_resctrl_add_controller_domain(struct cbqri_controller *ctrl= , int *id) +{ + struct rdt_domain *domain, *mon_domain =3D NULL; + struct cbqri_resctrl_res *cbqri_res =3D NULL; + struct cbqri_resctrl_dom *hw_dom_to_free; + struct rdt_resource *res; + int internal_id =3D *id; + int err; + + domain =3D qos_new_domain(ctrl); + if (!domain) + return -ENOSPC; + + if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY) { + cpumask_copy(&domain->cpu_mask, &ctrl->ctrl_info->cache.cpu_mask); + + if (ctrl->ctrl_info->cache.cache_level =3D=3D 2) { + cbqri_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_L2]; + cbqri_res->max_rcid =3D ctrl->ctrl_info->rcid_count; + cbqri_res->max_mcid =3D ctrl->ctrl_info->mcid_count; + res =3D &cbqri_res->resctrl_res; + res->num_rmid =3D ctrl->ctrl_info->mcid_count; + res->fflags =3D RFTYPE_RES_CACHE; + res->rid =3D RDT_RESOURCE_L2; + res->name =3D "L2"; + res->alloc_capable =3D ctrl->alloc_capable; + res->mon_capable =3D ctrl->mon_capable; + res->format_str =3D "%d=3D%0*x"; + res->cache_level =3D 2; + res->data_width =3D 3; + res->cache.arch_has_sparse_bitmaps =3D false; + res->cache.arch_has_per_cpu_cfg =3D false; + res->cache.shareable_bits =3D 0x000; + res->cache.min_cbm_bits =3D 1; + res->cache.cbm_len =3D ctrl->cc.ncblks; + res->default_ctrl =3D BIT_MASK(ctrl->cc.ncblks) - 1; + } else if (ctrl->ctrl_info->cache.cache_level =3D=3D 3) { + cbqri_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_L3]; + cbqri_res->max_rcid =3D ctrl->ctrl_info->rcid_count; + cbqri_res->max_mcid =3D ctrl->ctrl_info->mcid_count; + res =3D &cbqri_res->resctrl_res; + res->num_rmid =3D ctrl->ctrl_info->mcid_count; + res->fflags =3D RFTYPE_RES_CACHE; + res->rid =3D RDT_RESOURCE_L3; + res->name =3D "L3"; + res->cache_level =3D 3; + res->alloc_capable =3D ctrl->alloc_capable; + res->mon_capable =3D ctrl->mon_capable; + res->format_str =3D "%d=3D%0*x"; + res->data_width =3D 4; + res->cache.arch_has_sparse_bitmaps =3D false; + res->cache.arch_has_per_cpu_cfg =3D false; + res->cache.shareable_bits =3D 0x000; + res->cache.min_cbm_bits =3D 1; + res->cache.cbm_len =3D ctrl->cc.ncblks; + res->default_ctrl =3D BIT_MASK(ctrl->cc.ncblks) - 1; + } else { + pr_err("%s(): unknown cache level %d", __func__, + ctrl->ctrl_info->cache.cache_level); + err =3D -ENODEV; + goto err_free_domain; + } + } else if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) { + if (ctrl->alloc_capable) { + cbqri_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_MBA]; + cbqri_res->max_rcid =3D ctrl->ctrl_info->rcid_count; + cbqri_res->max_mcid =3D ctrl->ctrl_info->mcid_count; + res =3D &cbqri_res->resctrl_res; + res->num_rmid =3D ctrl->ctrl_info->mcid_count; + res->fflags =3D RFTYPE_RES_MB; + res->rid =3D RDT_RESOURCE_MBA; + res->name =3D "MB"; + res->alloc_capable =3D ctrl->alloc_capable; + /* + * MBA resource is only for allocation and + * monitoring can only be done with L3 resource + */ + res->mon_capable =3D false; + res->format_str =3D "%d=3D%*u"; + res->data_width =3D 4; + /* + * MBA schemata expects percentage so convert + * maximum reserved bw blocks to percentage + */ + res->default_ctrl =3D qos_bw_blocks_to_percentage(ctrl, ctrl->bc.mrbwb); + /* + * Use values from 0 to MBA_MAX instead of power of two values, + * see Intel System Programming Guide manual section 18.19.7.2 + */ + res->membw.delay_linear =3D true; + res->membw.arch_needs_linear =3D true; + /* Disable non-linear values support */ + res->membw.throttle_mode =3D THREAD_THROTTLE_UNDEFINED; + // The minimum percentage allowed by the CBQRI spec + res->membw.min_bw =3D 1; + res->membw.bw_gran =3D 1; + } + + /* + * Monitoring is not possible with Intel MBA resource, + * so add a L3 domain if monitoring is supported by the CBQRI + * bandwidth controller. + */ + if (ctrl->mon_capable) { + struct cbqri_resctrl_res *mon_cbqri_res; + + mon_cbqri_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_L3]; + mon_domain =3D qos_new_domain(ctrl); + if (!domain) + goto err_free_mon_domain; + + /* + * For CBQRI, any cpu (technically a hart in RISC-V terms) + * can access the memory-mapped registers of any CBQRI + * controller in the system. Thus it does not matter for + * RISC-V which cpu runs the resctrl code. + */ + cpumask_setall(&domain->cpu_mask); + + err =3D domain_setup_ctrlval(&mon_cbqri_res->resctrl_res, mon_domain); + if (err) + goto err_free_mon_domain; + + mon_domain->id =3D internal_id; + internal_id++; + list_add_tail(&mon_domain->list, &mon_cbqri_res->resctrl_res.domains); + err =3D resctrl_online_domain(res, mon_domain); + if (err) { + pr_debug("%s(): BW monitoring domain online failed", __func__); + goto err_free_mon_domain; + } + } + } else { + pr_err("%s(): unknown resource %d", __func__, ctrl->ctrl_info->type); + err =3D -ENODEV; + goto err_free_domain; + } + + domain->id =3D internal_id; + err =3D domain_setup_ctrlval(res, domain); + if (err) + goto err_free_mon_domain; + + if (cbqri_res) { + list_add_tail(&domain->list, &cbqri_res->resctrl_res.domains); + *id =3D internal_id; + err =3D resctrl_online_domain(res, domain); + if (err) { + pr_debug("%s(): failed to online cbqri_res domain", __func__); + goto err_free_domain; + } + } + + return 0; + +err_free_mon_domain: + if (!mon_domain) { + /* + * mon_domain is a struct rdt_domain which is a member of + * struct cbqri_resctrl_dom. That cbqri_resctrl_dom was + * allocated in qos_new_domain() and must be freed. + */ + hw_dom_to_free =3D container_of(mon_domain, struct cbqri_resctrl_dom, re= sctrl_dom); + kfree(hw_dom_to_free); + } + +err_free_domain: + /* similar to err_free_mon_domain but the ptr is 'domain' instead */ + hw_dom_to_free =3D container_of(domain, struct cbqri_resctrl_dom, resctrl= _dom); + kfree(hw_dom_to_free); + + return err; +} + +static int qos_resctrl_setup_resources(void) +{ + struct rdt_domain *domain, *domain_temp; + struct cbqri_controller_info *ctrl_info; + struct cbqri_controller *ctrl; + struct cbqri_resctrl_res *res; + int err =3D 0, i, id =3D 0; + + list_for_each_entry(ctrl_info, &cbqri_controllers, list) { + err =3D qos_resctrl_discover_controller(ctrl_info, &controllers[found_co= ntrollers]); + if (err) { + pr_err("%s(): qos_resctrl_discover_controller failed (%d)", __func__, e= rr); + goto err_unmap_controllers; + } + + found_controllers++; + if (found_controllers > MAX_CONTROLLERS) { + pr_warn("%s(): increase MAX_CONTROLLERS value", __func__); + break; + } + } + + for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { + res =3D &cbqri_resctrl_resources[i]; + INIT_LIST_HEAD(&res->resctrl_res.domains); + INIT_LIST_HEAD(&res->resctrl_res.evt_list); + res->resctrl_res.rid =3D i; + } + + for (i =3D 0; i < found_controllers; i++) { + ctrl =3D &controllers[i]; + err =3D qos_resctrl_add_controller_domain(ctrl, &id); + if (err) { + pr_err("%s(): failed to add controller domain (%d)", __func__, err); + goto err_free_controllers_list; + } + id++; + + /* + * CDP (code data prioritization) on x86 is similar to + * the AT (access type) field in CBQRI. CDP only supports + * caches so this must be a CBQRI capacity controller. + */ + if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY && + ctrl->cc.supports_alloc_at_code && + ctrl->cc.supports_alloc_at_data) { + if (ctrl->ctrl_info->cache.cache_level =3D=3D 2) + exposed_cdp_l2_capable =3D true; + else + exposed_cdp_l3_capable =3D true; + } + } + + pr_debug("exposed_alloc_capable =3D %d", exposed_alloc_capable); + pr_debug("exposed_mon_capable =3D %d", exposed_mon_capable); + pr_debug("exposed_cdp_l2_capable =3D %d", exposed_cdp_l2_capable); + pr_debug("exposed_cdp_l3_capable =3D %d", exposed_cdp_l3_capable); + return 0; + +err_free_controllers_list: + for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { + res =3D &cbqri_resctrl_resources[i]; + list_for_each_entry_safe(domain, domain_temp, &res->resctrl_res.domains,= list) { + kfree(domain); + } + } + +err_unmap_controllers: + for (i =3D 0; i < found_controllers; i++) { + iounmap(controllers[i].base); + release_mem_region(controllers[i].ctrl_info->addr, controllers[i].ctrl_i= nfo->size); + } + + return err; +} + +int qos_resctrl_setup(void) +{ + s32 err; + + err =3D qos_resctrl_setup_resources(); + if (err) { + pr_err("%s() failed with error %d\n", __func__, err); + return err; + } + + err =3D resctrl_init(); + + return err; +} + +int qos_resctrl_online_cpu(unsigned int cpu) +{ + return resctrl_online_cpu(cpu); +} + +int qos_resctrl_offline_cpu(unsigned int cpu) +{ + resctrl_offline_cpu(cpu); + return 0; +} --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7385CC77B75 for ; Wed, 19 Apr 2023 11:11:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232956AbjDSLLW (ORCPT ); Wed, 19 Apr 2023 07:11:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232903AbjDSLLI (ORCPT ); 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charset="utf-8" The generic resctrl header include/linux/resctrl.h includes asm/resctrl.h when CONFIG_ARCH_HAS_CPU_RESCTRL is set. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/include/asm/resctrl.h | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 arch/riscv/include/asm/resctrl.h diff --git a/arch/riscv/include/asm/resctrl.h b/arch/riscv/include/asm/resc= trl.h new file mode 100644 index 000000000000..7d247d87dab9 --- /dev/null +++ b/arch/riscv/include/asm/resctrl.h @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0B2DC77B73 for ; Wed, 19 Apr 2023 11:11:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232971AbjDSLL0 (ORCPT ); Wed, 19 Apr 2023 07:11:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232879AbjDSLLK (ORCPT ); Wed, 19 Apr 2023 07:11:10 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A45A13F9C for ; Wed, 19 Apr 2023 04:10:29 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1a80d827179so10132295ad.3 for ; Wed, 19 Apr 2023 04:10:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1681902623; x=1684494623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Eblfm/T6iTpx+B5jQxcafLiaSwdeB6MwJNMx1053fIM=; b=DeZfx01ZX7Sehx3CCekOj5Wmh5/0E6L27Vt1u0RCG6Af7W4Ww6d99E98VCdUMc5ILQ ppeTAQ4ynNy3TiNv6XuWSxIGB7HqcDqzwIX1tzEXE/xJHgae/7yiQ786zEhoR6k3gOvX L8RXwIuD/Bcpb+fx+/tEgYMPtOMn/5RGiZHZQSsVTwbwnESwjJZgQKjJgS+CYdiWmv/X sTlTz+tcJxIHBX9j344JEvQHen6NftYor8JECB66GT3RicUQttnGHRgNi5k9OBP15w4r +bm2YkMfwA9+FPgWxfcfMf6baW+J4rq9LuYDUDbRWAWXCt8WxTxt6hmZHGKv+vMZxzEt z6Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681902623; x=1684494623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Eblfm/T6iTpx+B5jQxcafLiaSwdeB6MwJNMx1053fIM=; b=XdFMMr2YsKNNzYQHqbxeYASfGeAwxhvJn9goi5e8jGYw/uRvUJ07CtBryCh1wKnU6z 7NrwQf/dr3XkkV8M1n9LNU2aBWdgz6VXi5W+YH9DGv7LdTYmRvwCx/7AWthR8SyF7vLq vtS7AhrP2OcJCf73HLak15pV7FAA/TdnpCg+/+1V04sTrOQ41IHvQ55WLh/wG2uoFHq5 ctDsN/UwfM1Ddygs9BX/P88ziy4Gwua5X6E0AE0vYI0SLWO+VPANnwUtoVE8XSQ1ryio ysVIBWLIubW7CZS/rOu6JuYB3frAm8fG/DzaQnvDJaeXVjl8/csObE+g8SvXQfUdXe51 1L9g== X-Gm-Message-State: AAQBX9dss5o5dCndAvwPBhTKEqKj46AImUER6KGjlqOVEPAinSqM94kE hEUlLQdoDWwP8b0/oapC+Ib8Zo4PQd+ASze/z5Y= X-Google-Smtp-Source: AKy350bJa8ymH8vz3WwMTgd0nDwI9tA5BpeE2IV7rV3XHn6aSE8c09ru5XOxb+Nqph2c5N8uPATfhA== X-Received: by 2002:a17:902:ab81:b0:1a6:4e7b:7037 with SMTP id f1-20020a170902ab8100b001a64e7b7037mr4418984plr.69.1681902623318; Wed, 19 Apr 2023 04:10:23 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1800:f680:eaf2:1d7a:7338:16cb]) by smtp.gmail.com with ESMTPSA id g12-20020a1709026b4c00b001a24cded097sm11180774plt.236.2023.04.19.04.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 04:10:22 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 09/21] RISC-V: QoS: add late_initcall to setup resctrl interface Date: Wed, 19 Apr 2023 04:10:59 -0700 Message-Id: <20230419111111.477118-10-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add late_initcall which checks if the Ssqosid extension is present, and if so, calls resctrl setup and sets cpu hotplug state to "qos:online". Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/qos.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 arch/riscv/kernel/qos/qos.c diff --git a/arch/riscv/kernel/qos/qos.c b/arch/riscv/kernel/qos/qos.c new file mode 100644 index 000000000000..0b5fde06cbe1 --- /dev/null +++ b/arch/riscv/kernel/qos/qos.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2023 Rivos Inc. + +#include +#include +#include +#include +#include + +#include +#include + +#include "internal.h" + +static int __init qos_arch_late_init(void) +{ + int err; + + if (!riscv_isa_extension_available(NULL, SSQOSID)) + return -ENODEV; + + err =3D qos_resctrl_setup(); + if (err !=3D 0) + return err; + + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "qos:online", qos_resctrl_online_c= pu, + qos_resctrl_offline_cpu); + + return err; +} +late_initcall(qos_arch_late_init); --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95491C77B75 for ; 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charset="utf-8" Make CONFIG_RISCV_ISA_SSQOSID select the config options for resctrl: ARCH_HAS_CPU_RESCTRL and RESCTRL_FS Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9d4c8c505191..683349c2e809 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -401,6 +401,9 @@ config RISCV_ISA_C config RISCV_ISA_SSQOSID bool "Ssqosid extension support for supervisor mode Quality of Service ID" default y + select ARCH_HAS_CPU_RESCTRL + select RESCTRL_FS + select MISC_FILESYSTEMS help Adds support for the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43812C77B73 for ; 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Wed, 19 Apr 2023 04:10:26 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1800:f680:eaf2:1d7a:7338:16cb]) by smtp.gmail.com with ESMTPSA id g12-20020a1709026b4c00b001a24cded097sm11180774plt.236.2023.04.19.04.10.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 04:10:25 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 11/21] RISC-V: QoS: add to build when CONFIG_RISCV_ISA_SSQOSID set Date: Wed, 19 Apr 2023 04:11:01 -0700 Message-Id: <20230419111111.477118-12-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the sqoscfg CSR handling and the resctrl interface to the build when CONFIG_RISCV_ISA_SSQOSID is set. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/Makefile | 2 ++ arch/riscv/kernel/qos/Makefile | 2 ++ 2 files changed, 4 insertions(+) create mode 100644 arch/riscv/kernel/qos/Makefile diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 4cf303a779ab..57d57e430fb9 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -89,3 +89,5 @@ obj-$(CONFIG_EFI) +=3D efi.o obj-$(CONFIG_COMPAT) +=3D compat_syscall_table.o obj-$(CONFIG_COMPAT) +=3D compat_signal.o obj-$(CONFIG_COMPAT) +=3D compat_vdso/ + +obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos/ diff --git a/arch/riscv/kernel/qos/Makefile b/arch/riscv/kernel/qos/Makefile new file mode 100644 index 000000000000..9ed0c13a854d --- /dev/null +++ b/arch/riscv/kernel/qos/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos.o qos_resctrl.o --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89A6CC6FD18 for ; Wed, 19 Apr 2023 11:11:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233027AbjDSLLp (ORCPT ); Wed, 19 Apr 2023 07:11:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232917AbjDSLLT (ORCPT ); Wed, 19 Apr 2023 07:11:19 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B539D13C23 for ; Wed, 19 Apr 2023 04:10:37 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1a526aa3dd5so36470825ad.3 for ; Wed, 19 Apr 2023 04:10:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1681902627; x=1684494627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IeP1c5FHkO2iYuai0o4JGoTDumRIxR3IsfyyPznXUZQ=; b=koEw/uiEXJ4P6r+2zoaiHPM5ok/d28q5pyhF5LbHc6I1XBnEv7ikHPdbKOO5lffn/K pKDES30EiXACKywfHsDUvjjt0cOPKfvLpyg9IeEb5NLAba+5aa/Q/MLSvGSDEPWntDpi abS8us22/q+V5R+SCMXTfaaDbuG1buySAT/syibcEKpDziulkNwfG1g/R2vwvlaUG+P7 fl09D+ZXUj4CtB6cdojZ/MWvx8OjwgAgpdsksCYdzZrmbJqBWSzxhAdKGStPebuYbxLb xjGTza0fpYTfOqnhex0mFm1BxYCeEx7xKzQ1po6NxzdlGYosdnG647RnUtd+HmnyvEj7 uvrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681902627; x=1684494627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IeP1c5FHkO2iYuai0o4JGoTDumRIxR3IsfyyPznXUZQ=; b=lftrJp8u2BSGvcuIbEoM/G/a+5IproN+BNi2Vile958YREEK3QWcxqW5nkGTbH2/ds mxxQWfdeaQNAKYJvjt4MXm29UQHkr48cZXYyhCijG5IpQuEPUpEx1mMSVD+zjZVplJZp JC/4FOL67gV4n/qdNVoSx7MuJBIBzd/r3BRj1dIzkqbczkBDd7Z+7E7acAtqK35l5D3/ 6V5/QHA2ZxZBG3c8nCbV0oSsFxPKAP79mOE2GpYd9Ao300IMn5GX972cWlC/g1gEtx4B wUPcLDR2IM6xv+vB71t11tS0fwzwvaf75YNZqUZdPKQnAeA5p+rsDIem56TZSXr2fYTy Qawg== X-Gm-Message-State: AAQBX9eeUUP8fvlmxg0HloDePV7c5y75ND2xsYk7J38u46L0azULsZqn CXsidOAjT6y7jQ1M42WuZ95VwQ== X-Google-Smtp-Source: AKy350as/KHWHZ+shgMkN9Cq1xyi0sRUDBIGVeroXLacVjHMk99lR8iksTM1dFoEjEk5V5sXMqlvAA== X-Received: by 2002:a17:903:11cf:b0:1a6:81bd:c4d9 with SMTP id q15-20020a17090311cf00b001a681bdc4d9mr5507947plh.39.1681902627683; Wed, 19 Apr 2023 04:10:27 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1800:f680:eaf2:1d7a:7338:16cb]) by smtp.gmail.com with ESMTPSA id g12-20020a1709026b4c00b001a24cded097sm11180774plt.236.2023.04.19.04.10.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 04:10:27 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 12/21] dt-bindings: riscv: add riscv,cbqri bindings Date: Wed, 19 Apr 2023 04:11:02 -0700 Message-Id: <20230419111111.477118-13-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document properties that can be used in the bindings for controllers that implement the RISC-V CBQRI specification. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- .../bindings/riscv/riscv,cbqri.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml diff --git a/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml b/Doc= umentation/devicetree/bindings/riscv/riscv,cbqri.yaml new file mode 100644 index 000000000000..3f017c6b1fb1 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/riscv,cbqri.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Capacity and Bandwidth Register Interface (CBQRI) properties + +description: | + Common properties for cache and memory controllers that implement the + RISC-V CBQRI specification: + https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf + +maintainers: + - Drew Fustini + +properties: + riscv,cbqri-rcid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The maximum number of RCIDs the controller supports + + riscv,cbqri-mcid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The maximum number of MCIDs the controller supports + +additionalProperties: true + +... --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7033C6FD18 for ; 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Wed, 19 Apr 2023 04:10:29 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1800:f680:eaf2:1d7a:7338:16cb]) by smtp.gmail.com with ESMTPSA id g12-20020a1709026b4c00b001a24cded097sm11180774plt.236.2023.04.19.04.10.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 04:10:28 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 13/21] DO_NOT_MERGE dt-bindings: add foobar vendor-prefix Date: Wed, 19 Apr 2023 04:11:03 -0700 Message-Id: <20230419111111.477118-14-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add prefix for an example SoC vendor whose designs include controllers that implement CBQRI. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index ed64e06ecca4..426f4eef06eb 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -470,6 +470,8 @@ patternProperties: description: Shenzhen Fly Young Technology Co.,LTD. "^fii,.*": description: Foxconn Industrial Internet + "^foobar,.*": + description: Foobar Systems "^firefly,.*": description: Firefly "^focaltech,.*": --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99702C6FD18 for ; Wed, 19 Apr 2023 11:11:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233064AbjDSLL4 (ORCPT ); Wed, 19 Apr 2023 07:11:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232949AbjDSLLU (ORCPT ); Wed, 19 Apr 2023 07:11:20 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6193B13F9F for ; Wed, 19 Apr 2023 04:10:38 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-63b73203e0aso15253989b3a.1 for ; Wed, 19 Apr 2023 04:10:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1681902630; x=1684494630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z6zQom7c9ZPxaL0AlvEMhKoZ47HVwA0KXR3RYZHyFgk=; b=way4ScdIS96YRKdHcgBpyse+tOSSXOie7JmzQ3ruykWd+bvImdobFO37hhT77+L3/U kaqojTkCN3wGLtbhwA90MgVOAgFVGf4Dedela1TNzHBvJRZjXQSXWFwPwduhVj6TPdzX GIc+Nuk7F+h6MKBmdyl2qvDlk02/j2I47Ppo5mo1ZpuQIvpD572EFN7U+sOSUY8XSxOw WOi4FCrreEQEdHwpWijIg+JK2+Lnl3ALjpm7l3mTxtaHBsOCVR7Bn5fo01aFxF/GJUow MnGtG2IiDAagEyhqLKjTxyj+uGdYLVG4BA2My74jN6jA7ZYKA/Gg5Wy1kJphb7t+NVe8 GiJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681902630; x=1684494630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z6zQom7c9ZPxaL0AlvEMhKoZ47HVwA0KXR3RYZHyFgk=; b=Fw6yQt10IeI7NtFy+ZHFZSQ3V6hWjQpRbrL/3ftJRYBKF0BGxeZzGpbx9L3l1zKc5a r79WBkjbVPppV0tCtcRQm/qGiPS35/8TmPqlPT8efRJMYGvtL+6NZM2pNh1IaY1EEQSP a1UrNUD52AnH/gw7m6s107Tl+WBRc+sz8sXS6/b6iwmgR2EEBXRTMaJINUCp0cgSiv9U 7N638RPC/l+kbgQRHi97hCuLfP9AcLR+FAZR7UeEW1b8hHGwDuMh2+a/0cHMaiJ6Epd4 EnsGm+rGLle0UrcRlDSK6VjUnXCVvHz1RwtW0KlLNwn+MpfpIHVcZlr8E0Qv//4vLuX3 hcSQ== X-Gm-Message-State: AAQBX9frQqR6Y8662fCT5ZaCPk1aXUm7yW3pet4rBFhn8GAeU8dwGKYF j2qtgUERXCGaipORU5yy9IGmlQ== X-Google-Smtp-Source: AKy350ZMyASO/6WHrB2YnJ1c5qAAic0H4uqyutx85aVkcy8OYWscNutmT//7hNt7yI5Yb0peas0zAA== X-Received: by 2002:a17:902:dad0:b0:1a2:a904:c42e with SMTP id q16-20020a170902dad000b001a2a904c42emr1574829plx.24.1681902630432; Wed, 19 Apr 2023 04:10:30 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1800:f680:eaf2:1d7a:7338:16cb]) by smtp.gmail.com with ESMTPSA id g12-20020a1709026b4c00b001a24cded097sm11180774plt.236.2023.04.19.04.10.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 04:10:29 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 14/21] DO_NOT_MERGE dt-bindings: soc: add Foobar SoC cache controller Date: Wed, 19 Apr 2023 04:11:04 -0700 Message-Id: <20230419111111.477118-15-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bindings for an example SoC cache controller that implements CBQRI. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- .../soc/foobar/foobar,cache-controller.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/foobar/foobar,cac= he-controller.yaml diff --git a/Documentation/devicetree/bindings/soc/foobar/foobar,cache-cont= roller.yaml b/Documentation/devicetree/bindings/soc/foobar/foobar,cache-con= troller.yaml new file mode 100644 index 000000000000..6348483bbe09 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/foobar/foobar,cache-controller.= yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/foobar/foobar,cache-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Foobar SoC Cache Controller + +maintainers: + - Drew Fustini + +description: + Foobar SoC cache controller implements the RISC-V CBQRI interface for + capacity allocaiton and usage monitoring. + +allOf: + - $ref: /schemas/cache-controller.yaml# + - $ref: /schemas/riscv/riscv,cbqri.yaml# + +properties: + compatible: + items: + - const: foobar,cache-controller + reg: + maxItems: 1 + description: A memory region containing registers as defined in CBQRI = spec + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + + cache-controller@fff12000 { + compatible =3D "foobar,cache-controller"; + reg =3D <0xfff12000 0x2000>; + cache-level =3D <2>; + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + +... --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB91CC77B75 for ; Wed, 19 Apr 2023 11:12:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232449AbjDSLME (ORCPT ); Wed, 19 Apr 2023 07:12:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232953AbjDSLLV (ORCPT ); Wed, 19 Apr 2023 07:11:21 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70E6E13FAD for ; Wed, 19 Apr 2023 04:10:40 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1a52667955dso35501915ad.1 for ; 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charset="utf-8" Add bindings for an example SoC memory controller that implements CBQRI. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- .../soc/foobar/foobar,memory-controller.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/foobar/foobar,mem= ory-controller.yaml diff --git a/Documentation/devicetree/bindings/soc/foobar/foobar,memory-con= troller.yaml b/Documentation/devicetree/bindings/soc/foobar/foobar,memory-c= ontroller.yaml new file mode 100644 index 000000000000..859ee52680d5 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/foobar/foobar,memory-controller= .yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/foobar/foobar,memory-controller.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Foobar SoC Memory Controller + +maintainers: + - Drew Fustini + +description: + Foobar SoC memory controller implements the RISC-V CBQRI interface for + capacity allocaiton and usage monitoring. + +allOf: + - $ref: /schemas/riscv/riscv,cbqri.yaml# + +properties: + compatible: + items: + - const: foobar,memory-controller + reg: + maxItems: 1 + description: A memory region containing registers as defined in CBQRI = spec + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + + memory-controller@fff12000 { + compatible =3D "foobar,memory-controller"; + reg =3D <0xfff12000 0x2000>; + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + +... --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31CFAC77B73 for ; Wed, 19 Apr 2023 11:12:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233069AbjDSLMA (ORCPT ); Wed, 19 Apr 2023 07:12:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232950AbjDSLLV (ORCPT ); Wed, 19 Apr 2023 07:11:21 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7103913FAE for ; Wed, 19 Apr 2023 04:10:40 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1a667067275so25322215ad.1 for ; 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charset="utf-8" Add example driver for a cache controller that implements CBQRI. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/soc/foobar/foobar_cbqri_cache.c | 110 ++++++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 drivers/soc/foobar/foobar_cbqri_cache.c diff --git a/drivers/soc/foobar/foobar_cbqri_cache.c b/drivers/soc/foobar/f= oobar_cbqri_cache.c new file mode 100644 index 000000000000..e880488243d8 --- /dev/null +++ b/drivers/soc/foobar/foobar_cbqri_cache.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Foobar Systems CBQRI cache controller + */ + +#define pr_fmt(fmt) "foobar-cache: " fmt + +#include +#include +#include + +static const struct of_device_id foobar_cbqri_cache_ids[] =3D { + { .compatible =3D "foobar,cache-controller" }, + { } +}; + +static int __init foobar_cbqri_cache_init(void) +{ + struct device_node *np; + int err; + u32 value; + struct cbqri_controller_info *ctrl_info; + + for_each_matching_node(np, foobar_cbqri_cache_ids) { + if (!of_device_is_available(np)) { + of_node_put(np); + continue; + } + + ctrl_info =3D kzalloc(sizeof(*ctrl_info), GFP_KERNEL); + if (!ctrl_info) + goto err_node_put; + ctrl_info->type =3D CBQRI_CONTROLLER_TYPE_CAPACITY; + + err =3D of_property_read_u32_index(np, "reg", 1, &value); + if (err) { + pr_err("Failed to read reg base address (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->addr =3D value; + + err =3D of_property_read_u32_index(np, "reg", 3, &value); + if (err) { + pr_err("Failed to read reg size (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->size =3D value; + + err =3D of_property_read_u32(np, "cache-level", &value); + if (err) { + pr_err("Failed to read cache level (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->cache.cache_level =3D value; + + err =3D of_property_read_u32(np, "cache-size", &value); + if (err) { + pr_err("Failed to read cache size (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->cache.cache_size =3D value; + + err =3D of_property_read_u32(np, "riscv,cbqri-rcid", &value); + if (err) { + pr_err("Failed to read RCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->rcid_count =3D value; + + err =3D of_property_read_u32(np, "riscv,cbqri-mcid", &value); + if (err) { + pr_err("Failed to read MCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->mcid_count =3D value; + + /* + * For CBQRI, any cpu (technically a hart in RISC-V terms) + * can access the memory-mapped registers of any CBQRI + * controller in the system. Therefore, set the CPU mask + * to 'FF' to allow all 8 cores in the example Foobar SoC + */ + err =3D cpumask_parse("FF", &ctrl_info->cache.cpu_mask); + if (err) { + pr_err("Failed to convert cores mask string to cpumask (%d)", err); + goto err_kfree_ctrl_info; + } + + of_node_put(np); + + pr_debug("addr=3D0x%lx max-rcid=3D%u max-mcid=3D%u level=3D%d size=3D%u", + ctrl_info->addr, ctrl_info->rcid_count, ctrl_info->mcid_count, + ctrl_info->cache.cache_level, ctrl_info->cache.cache_size); + + /* Fill the list shared with RISC-V QoS resctrl */ + INIT_LIST_HEAD(&ctrl_info->list); + list_add_tail(&ctrl_info->list, &cbqri_controllers); + } + + return 0; + +err_kfree_ctrl_info: + kfree(ctrl_info); + +err_node_put: + of_node_put(np); + + return err; +} +device_initcall(foobar_cbqri_cache_init); --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D104C77B73 for ; Wed, 19 Apr 2023 11:12:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233008AbjDSLMI (ORCPT ); Wed, 19 Apr 2023 07:12:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232954AbjDSLLV (ORCPT ); Wed, 19 Apr 2023 07:11:21 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D090DA256 for ; Wed, 19 Apr 2023 04:10:40 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1a6ebc66ca4so14849545ad.3 for ; Wed, 19 Apr 2023 04:10:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1681902634; x=1684494634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8VRpPNkDuAyz+Ft5imrcs9KDU5p5mtKUYR9cIj3QRd4=; b=x/8pGfsLNTo4M60IL76aQ5x040uI2InLj1/EScIFp6VYlhbjP5l3eNVgN+y4avjRTt H5fzYWvVhJT2Rq7bzjd2zo6SGa9b70+iPd7q+BYZOfnbxUKSB2gBI+v9EID/w220Xv6A ogg1jlEVmqJYIyFKd2qTHBIQq91+m87zuaTfEpDGjS4JjD5plCp7XDP57KjGuKZ+kOiN SVYdRu2DZSdcypVQLwcCpNb8l4lKH0jilJ++oP1hk4KiAaDnMtqJcq8eN39x6hZzCeaP j6FiQUn7+p1qacItyHJxcwZOT4dU4m7qvkAF3FVlQoqYsjD4V5HP3V7p3ikdeOowNAkl 8kWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681902634; x=1684494634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8VRpPNkDuAyz+Ft5imrcs9KDU5p5mtKUYR9cIj3QRd4=; b=UJDqwXHbQyurQINW5R0/7MTORD3H4DlttpBM9b8kk3HMN08fDkwfW1dKsBRbCH2dDB cqSStq8HzBDUqttLGn/Z+PI7g3k6a3nW91u98ZPUbRrTynjZeyT1Hc2PKMZGlJKgkEN1 /RsN7xpD0PQygAO5i2a6RUwyDdk4K6IObXHAodeyst7dqLZYXYH87CZ5WdUiMvISIWpl yTg1Z4KoVLhU9K+2FDQ6I5TX5XcCAhGjAjx2JecsrNhF94bhnEA9WYktL/EFU97tu+im +16kDREF7nmRToPb+ZOy8MpMokdjhaUCwANuzujdjLZBGKZ+IwRvleXddqEHfvJrP0We 3gWg== X-Gm-Message-State: AAQBX9fImShDoODop+gI/LxVGChbBsmjewnvwMPCpq1HA1w2rwSEYKKO sNSVLvuJ6XXFbbFGElAV6evUFQ== X-Google-Smtp-Source: AKy350boG05NBC+OyMdfVB4g1lkdqwK+pdBb8M8du2YV2tJ6Pxg4DvMv0hsz2y7ET8IQwFhAUURrrw== X-Received: by 2002:a17:902:db0f:b0:1a1:a9a4:ba26 with SMTP id m15-20020a170902db0f00b001a1a9a4ba26mr5908976plx.8.1681902634412; Wed, 19 Apr 2023 04:10:34 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1800:f680:eaf2:1d7a:7338:16cb]) by smtp.gmail.com with ESMTPSA id g12-20020a1709026b4c00b001a24cded097sm11180774plt.236.2023.04.19.04.10.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 04:10:33 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 17/21] DO_NOT_MERGE soc: add Foobar SoC memory controller driver Date: Wed, 19 Apr 2023 04:11:07 -0700 Message-Id: <20230419111111.477118-18-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add example driver for a SoC memory controller that implements CBQRI. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/soc/foobar/foobar_cbqri_memory.c | 83 ++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 drivers/soc/foobar/foobar_cbqri_memory.c diff --git a/drivers/soc/foobar/foobar_cbqri_memory.c b/drivers/soc/foobar/= foobar_cbqri_memory.c new file mode 100644 index 000000000000..0a0c542a25e1 --- /dev/null +++ b/drivers/soc/foobar/foobar_cbqri_memory.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Foobar Systems CBQRI memory controller + */ + +#define pr_fmt(fmt) "foobar-mem: " fmt + +#include +#include +#include + +static const struct of_device_id foobar_cbqri_memory_ids[] =3D { + { .compatible =3D "foobar,memory-controller" }, + { } +}; + +static int __init foobar_cbqri_memory_init(void) +{ + struct device_node *np; + int err; + u32 value; + struct cbqri_controller_info *ctrl_info; + + for_each_matching_node(np, foobar_cbqri_memory_ids) { + if (!of_device_is_available(np)) { + of_node_put(np); + continue; + } + + ctrl_info =3D kzalloc(sizeof(*ctrl_info), GFP_KERNEL); + if (!ctrl_info) + goto err_node_put; + ctrl_info->type =3D CBQRI_CONTROLLER_TYPE_BANDWIDTH; + + err =3D of_property_read_u32_index(np, "reg", 1, &value); + if (err) { + pr_err("Failed to read reg base address (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->addr =3D value; + + err =3D of_property_read_u32_index(np, "reg", 3, &value); + if (err) { + pr_err("Failed to read reg size (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->size =3D value; + + err =3D of_property_read_u32(np, "riscv,cbqri-rcid", &value); + if (err) { + pr_err("Failed to read RCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->rcid_count =3D value; + + err =3D of_property_read_u32(np, "riscv,cbqri-mcid", &value); + if (err) { + pr_err("Failed to read MCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->mcid_count =3D value; + + of_node_put(np); + + pr_debug("addr=3D0x%lx max-rcid=3D%u max-mcid=3D%u", ctrl_info->addr, + ctrl_info->rcid_count, ctrl_info->mcid_count); + + /* Fill the list shared with RISC-V QoS resctrl */ + INIT_LIST_HEAD(&ctrl_info->list); + list_add_tail(&ctrl_info->list, &cbqri_controllers); + } + + return 0; + +err_kfree_ctrl_info: + kfree(ctrl_info); + +err_node_put: + of_node_put(np); + + return err; +} +device_initcall(foobar_cbqri_memory_init); --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05D19C6FD18 for ; Wed, 19 Apr 2023 11:12:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232711AbjDSLMP (ORCPT ); Wed, 19 Apr 2023 07:12:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232890AbjDSLLV (ORCPT ); Wed, 19 Apr 2023 07:11:21 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7982713FB9 for ; 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Wed, 19 Apr 2023 04:10:35 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 18/21] DO_NOT_MERGE soc: build Foobar SoC drivers Date: Wed, 19 Apr 2023 04:11:08 -0700 Message-Id: <20230419111111.477118-19-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Foobar SoC cache and memory controller drivers to the build. The hypothetical Foobar SoC serves as an example of an SoC with controllers that implement the RISC-V Capacity and Bandwidth QoS Register Interface (CBQRI) specification. Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/foobar/Kconfig | 21 +++++++++++++++++++++ drivers/soc/foobar/Makefile | 4 ++++ 4 files changed, 27 insertions(+) create mode 100644 drivers/soc/foobar/Kconfig create mode 100644 drivers/soc/foobar/Makefile diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 4e176280113a..8578f8c607ff 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -8,6 +8,7 @@ source "drivers/soc/aspeed/Kconfig" source "drivers/soc/atmel/Kconfig" source "drivers/soc/bcm/Kconfig" source "drivers/soc/canaan/Kconfig" +source "drivers/soc/foobar/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/fujitsu/Kconfig" source "drivers/soc/imx/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 3b0f9fb3b5c8..37a77c2dab94 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -11,6 +11,7 @@ obj-y +=3D bcm/ obj-$(CONFIG_SOC_CANAAN) +=3D canaan/ obj-$(CONFIG_ARCH_DOVE) +=3D dove/ obj-$(CONFIG_MACH_DOVE) +=3D dove/ +obj-y +=3D foobar/ obj-y +=3D fsl/ obj-y +=3D fujitsu/ obj-$(CONFIG_ARCH_GEMINI) +=3D gemini/ diff --git a/drivers/soc/foobar/Kconfig b/drivers/soc/foobar/Kconfig new file mode 100644 index 000000000000..4548e822357e --- /dev/null +++ b/drivers/soc/foobar/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0 + +config FOOBAR_CBQRI_CACHE + bool "Foobar cache controller for RISC-V CBQRI testing" + default y + help + Support the cache controller in a hypothetical "Foobar" SoC that + implements the RISC-V Capacity and Bandwidth QoS Register Interface + (CBQRI) specification. + + If you do not care about testing RISC-V CBQRI, then choose 'N'. + +config FOOBAR_CBQRI_MEMORY + bool "Foobar memory controller for RISC-V CBQRI testing" + default y + help + Support the memory controller in a hypothetical "Foobar" SoC that + implements the RISC-V Capacity and Bandwidth QoS Register Interface + (CBQRI) specification. + + If you do not care about testing RISC-V CBQRI, then choose 'N'. diff --git a/drivers/soc/foobar/Makefile b/drivers/soc/foobar/Makefile new file mode 100644 index 000000000000..e4f34058e39e --- /dev/null +++ b/drivers/soc/foobar/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_FOOBAR_CBQRI_CACHE) +=3D foobar_cbqri_cache.o +obj-$(CONFIG_FOOBAR_CBQRI_MEMORY) +=3D foobar_cbqri_memory.o --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8813BC6FD18 for ; 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charset="utf-8" Dumped dtb from qemu branch riscv-cbqri-rfc which is on top of qemu master (tag: v8.0.0-rc4) with qemu/VERSION of 7.2.94 invoked with: qemu-system-riscv64 \ -M virt \ -nographic \ -smp 8 \ -bios output/images/fw_jump.elf \ -kernel $HOME/kernel/cbqri-linux/arch/riscv/boot/Image \ -append "root=3D/dev/vda ro" \ -drive file=3Doutput/images/rootfs.ext2,format=3Draw,id=3Dhd0 \ -device virtio-blk-device,drive=3Dhd0 \ -machine dumpdtb=3Dqemu.dtb Link: https://gitlab.baylibre.com/baylibre/qemu/-/tree/riscv-cbqri-rfc Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- Note: this is necessary as Qemu branch riscv-cbqri-rfc does not yet support generating a dtb with the nodes and properties needed for CBQRI controllers. Thus, those lines must be added in the next patch and an external dtb (qemu-virt-cbqri.dtb) built by Linux is used when invoking qemu-system-riscv64 arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts | 371 +++++++++++++++++++ 1 file changed, 371 insertions(+) create mode 100644 arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts diff --git a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts b/arch/riscv/boot= /dts/qemu/qemu-virt-cbqri.dts new file mode 100644 index 000000000000..400ed48a06af --- /dev/null +++ b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/dts-v1/; + +/ { + #address-cells =3D <0x02>; + #size-cells =3D <0x02>; + compatible =3D "riscv-virtio"; + model =3D "riscv-virtio,qemu"; + + fw-cfg@10100000 { + dma-coherent; + reg =3D <0x00 0x10100000 0x00 0x18>; + compatible =3D "qemu,fw-cfg-mmio"; + }; + + flash@20000000 { + bank-width =3D <0x04>; + reg =3D <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>; + compatible =3D "cfi-flash"; + }; + + chosen { + bootargs =3D "root=3D/dev/vda ro ftrace=3Dfunction_graph ftrace_filter= =3D\"*resctrl*,*qos*\""; + rng-seed =3D <0xb87c09c5 0xc8f0c713 0x9c217b2a 0xa6f44e14 0xb6e99df6 0x2= 05d482b 0x6d4c34f4 0x6466fc08>; + stdout-path =3D "/soc/serial@10000000"; + }; + + poweroff { + value =3D <0x5555>; + offset =3D <0x00>; + regmap =3D <0x12>; + compatible =3D "syscon-poweroff"; + }; + + reboot { + value =3D <0x7777>; + offset =3D <0x00>; + regmap =3D <0x12>; + compatible =3D "syscon-reboot"; + }; + + platform-bus@4000000 { + interrupt-parent =3D <0x11>; + ranges =3D <0x00 0x00 0x4000000 0x2000000>; + #address-cells =3D <0x01>; + #size-cells =3D <0x01>; + compatible =3D "qemu,platform\0simple-bus"; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x00 0x80000000 0x00 0x8000000>; + }; + + cpus { + #address-cells =3D <0x01>; + #size-cells =3D <0x00>; + timebase-frequency =3D <0x989680>; + + cpu@0 { + phandle =3D <0x0f>; + device_type =3D "cpu"; + reg =3D <0x00>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x10>; + }; + }; + + cpu@1 { + phandle =3D <0x0d>; + device_type =3D "cpu"; + reg =3D <0x01>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0e>; + }; + }; + + cpu@2 { + phandle =3D <0x0b>; + device_type =3D "cpu"; + reg =3D <0x02>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0c>; + }; + }; + + cpu@3 { + phandle =3D <0x09>; + device_type =3D "cpu"; + reg =3D <0x03>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0a>; + }; + }; + + cpu@4 { + phandle =3D <0x07>; + device_type =3D "cpu"; + reg =3D <0x04>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x08>; + }; + }; + + cpu@5 { + phandle =3D <0x05>; + device_type =3D "cpu"; + reg =3D <0x05>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x06>; + }; + }; + + cpu@6 { + phandle =3D <0x03>; + device_type =3D "cpu"; + reg =3D <0x06>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x04>; + }; + }; + + cpu@7 { + phandle =3D <0x01>; + device_type =3D "cpu"; + reg =3D <0x07>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa =3D "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zaw= rs_zba_zbb_zbc_zbs_ssqosid_sstc_svadu"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x02>; + }; + }; + + cpu-map { + + cluster0 { + + core0 { + cpu =3D <0x0f>; + }; + + core1 { + cpu =3D <0x0d>; + }; + + core2 { + cpu =3D <0x0b>; + }; + + core3 { + cpu =3D <0x09>; + }; + + core4 { + cpu =3D <0x07>; + }; + + core5 { + cpu =3D <0x05>; + }; + + core6 { + cpu =3D <0x03>; + }; + + core7 { + cpu =3D <0x01>; + }; + }; + }; + }; + + soc { + #address-cells =3D <0x02>; + #size-cells =3D <0x02>; + compatible =3D "simple-bus"; + ranges; + + pmu { + riscv,event-to-mhpmcounters =3D <0x01 0x01 0x7fff9 0x02 0x02 0x7fffc 0x= 10019 0x10019 0x7fff8 0x1001b 0x1001b 0x7fff8 0x10021 0x10021 0x7fff8 0x00 = 0x00 0x00 0x00 0x00>; + compatible =3D "riscv,pmu"; + }; + + rtc@101000 { + interrupts =3D <0x0b>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x101000 0x00 0x1000>; + compatible =3D "google,goldfish-rtc"; + }; + + serial@10000000 { + interrupts =3D <0x0a>; + interrupt-parent =3D <0x11>; + clock-frequency =3D "\08@"; + reg =3D <0x00 0x10000000 0x00 0x100>; + compatible =3D "ns16550a"; + }; + + test@100000 { + phandle =3D <0x12>; + reg =3D <0x00 0x100000 0x00 0x1000>; + compatible =3D "sifive,test1\0sifive,test0\0syscon"; + }; + + pci@30000000 { + interrupt-map-mask =3D <0x1800 0x00 0x00 0x07>; + interrupt-map =3D <0x00 0x00 0x00 0x01 0x11 0x20 0x00 0x00 0x00 0x02 0x= 11 0x21 0x00 0x00 0x00 0x03 0x11 0x22 0x00 0x00 0x00 0x04 0x11 0x23 0x800 0= x00 0x00 0x01 0x11 0x21 0x800 0x00 0x00 0x02 0x11 0x22 0x800 0x00 0x00 0x03= 0x11 0x23 0x800 0x00 0x00 0x04 0x11 0x20 0x1000 0x00 0x00 0x01 0x11 0x22 0= x1000 0x00 0x00 0x02 0x11 0x23 0x1000 0x00 0x00 0x03 0x11 0x20 0x1000 0x00 = 0x00 0x04 0x11 0x21 0x1800 0x00 0x00 0x01 0x11 0x23 0x1800 0x00 0x00 0x02 0= x11 0x20 0x1800 0x00 0x00 0x03 0x11 0x21 0x1800 0x00 0x00 0x04 0x11 0x22>; + ranges =3D <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0= x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x0= 0 0x04 0x00>; + reg =3D <0x00 0x30000000 0x00 0x10000000>; + dma-coherent; + bus-range =3D <0x00 0xff>; + linux,pci-domain =3D <0x00>; + device_type =3D "pci"; + compatible =3D "pci-host-ecam-generic"; + #size-cells =3D <0x02>; + #interrupt-cells =3D <0x01>; + #address-cells =3D <0x03>; + }; + + virtio_mmio@10008000 { + interrupts =3D <0x08>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10008000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10007000 { + interrupts =3D <0x07>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10007000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10006000 { + interrupts =3D <0x06>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10006000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10005000 { + interrupts =3D <0x05>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10005000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10004000 { + interrupts =3D <0x04>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10004000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10003000 { + interrupts =3D <0x03>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10003000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10002000 { + interrupts =3D <0x02>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10002000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10001000 { + interrupts =3D <0x01>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10001000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + plic@c000000 { + phandle =3D <0x11>; + riscv,ndev =3D <0x5f>; + reg =3D <0x00 0xc000000 0x00 0x600000>; + interrupts-extended =3D <0x10 0x0b 0x10 0x09 0x0e 0x0b 0x0e 0x09 0x0c 0= x0b 0x0c 0x09 0x0a 0x0b 0x0a 0x09 0x08 0x0b 0x08 0x09 0x06 0x0b 0x06 0x09 0= x04 0x0b 0x04 0x09 0x02 0x0b 0x02 0x09>; + interrupt-controller; + compatible =3D "sifive,plic-1.0.0\0riscv,plic0"; + #address-cells =3D <0x00>; + #interrupt-cells =3D <0x01>; + }; + + clint@2000000 { + interrupts-extended =3D <0x10 0x03 0x10 0x07 0x0e 0x03 0x0e 0x07 0x0c 0= x03 0x0c 0x07 0x0a 0x03 0x0a 0x07 0x08 0x03 0x08 0x07 0x06 0x03 0x06 0x07 0= x04 0x03 0x04 0x07 0x02 0x03 0x02 0x07>; + reg =3D <0x00 0x2000000 0x00 0x10000>; + compatible =3D "sifive,clint0\0riscv,clint0"; + }; + }; +}; --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 194E5C6FD18 for ; Wed, 19 Apr 2023 11:12:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233099AbjDSLML (ORCPT ); Wed, 19 Apr 2023 07:12:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232958AbjDSLLW (ORCPT ); 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Wed, 19 Apr 2023 04:10:37 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 20/21] DO_NOT_MERGE riscv: dts: qemu: add cbqri-capable controllers Date: Wed, 19 Apr 2023 04:11:10 -0700 Message-Id: <20230419111111.477118-21-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add nodes to for CBQRI-capable cache and memory controllers. This is necessary as the qemu branch riscv-cbqri-rfc (based on v8.0.0-rc4) does not yet support generating a dtb with the nodes and properties needed for CBQRI controllers. Thus, an external dtb (qemu-virt-cbqri.dtb) built by Linux is used when invoking qemu-system-riscv64: qemu-system-riscv64 \ -M virt \ -nographic \ -smp 8 \ -bios output/images/fw_jump.elf \ -kernel ${LINUX}/arch/riscv/boot/Image \ -dtb ${LINUX}/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dtb \ -append "root=3D/dev/vda ro" \ -drive file=3Doutput/images/rootfs.ext2,format=3Draw,id=3Dhd0 \ -device virtio-blk-device,drive=3Dhd0 \ Link: https://gitlab.baylibre.com/baylibre/qemu/-/tree/riscv-cbqri-rfc Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts | 59 ++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts b/arch/riscv/boot= /dts/qemu/qemu-virt-cbqri.dts index 400ed48a06af..2c4ddc4271cc 100644 --- a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts +++ b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts @@ -367,5 +367,64 @@ clint@2000000 { reg =3D <0x00 0x2000000 0x00 0x10000>; compatible =3D "sifive,clint0\0riscv,clint0"; }; + + cluster0_l2: controller@4820000 { + compatible =3D "foobar,cache-controller"; + reg =3D <0x0 0x4820000 0x0 0x1000>; /* 4KB at 0x04820000 */ + cache-unified; + cache-line-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1000>; + cache-size =3D <768000>; /* 750 KiB */ + next-level-cache =3D <&shared_llc>; + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + + cluster1_l2: controller@4821000 { + compatible =3D "foobar,cache-controller"; + reg =3D <0x0 0x4821000 0x0 0x1000>; /* 4KB at 0x04821000 */ + cache-unified; + cache-line-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1000>; + cache-size =3D <768000>; /* 750 KiB */ + next-level-cache =3D <&shared_llc>; + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + + shared_llc: controller@482b000 { + compatible =3D "foobar,cache-controller"; + reg =3D <0x0 0x482b000 0x0 0x1000>; /* 4KB at 0x0482B000 */ + cache-unified; + cache-line-size =3D <64>; + cache-level =3D <3>; + cache-sets =3D <4096>; + cache-size =3D <3145728>; /* 3 MiB */ + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + + mem0: controller@4828000 { + compatible =3D "foobar,memory-controller"; + reg =3D <0x0 0x4828000 0x0 0x1000>; /* 4KB at 0x04828000 */ + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + + mem1: controller@4829000 { + compatible =3D "foobar,memory-controller"; + reg =3D <0x0 0x4829000 0x0 0x1000>; /* 4KB at 0x04829000 */ + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + + mem2: controller@482a000 { + compatible =3D "foobar,memory-controller"; + reg =3D <0x0 0x482a000 0x0 0x1000>; /* 4KB at 0x0482A000 */ + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; }; }; --=20 2.34.1 From nobody Tue Dec 16 08:52:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CEF3C6FD18 for ; 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Wed, 19 Apr 2023 04:10:39 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1800:f680:eaf2:1d7a:7338:16cb]) by smtp.gmail.com with ESMTPSA id g12-20020a1709026b4c00b001a24cded097sm11180774plt.236.2023.04.19.04.10.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 04:10:38 -0700 (PDT) From: Drew Fustini To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Conor Dooley , Ved Shanbhogue , =?UTF-8?q?Kornel=20Dul=C4=99ba?= , Adrien Ricciardi , Nicolas Pitre , Fenghua Yu , Reinette Chatre , Babu Moger , Peter Newman , x86@kernel.org, Rob Herring , James Morse Cc: Drew Fustini Subject: [RFC PATCH 21/21] DO_NOT_MERGE riscv: dts: build qemu virt device tree Date: Wed, 19 Apr 2023 04:11:11 -0700 Message-Id: <20230419111111.477118-22-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com> References: <20230419111111.477118-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the device tree for the qemu virt machine to the build. The resulting dtb will be consumed by qemu-system-riscv64. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/qemu/Makefile | 3 +++ 2 files changed, 4 insertions(+) create mode 100644 arch/riscv/boot/dts/qemu/Makefile diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f0d9f89054f8..74d99d28522f 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -5,5 +5,6 @@ subdir-y +=3D starfive subdir-y +=3D canaan subdir-y +=3D microchip subdir-y +=3D renesas +subdir-y +=3D qemu =20 obj-$(CONFIG_BUILTIN_DTB) :=3D $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/qemu/Makefile b/arch/riscv/boot/dts/qemu/M= akefile new file mode 100644 index 000000000000..07252b4ff455 --- /dev/null +++ b/arch/riscv/boot/dts/qemu/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_VIRT) +=3D qemu-virt-cbqri.dtb +obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) --=20 2.34.1