From nobody Wed Dec 17 17:00:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6168CC77B73 for ; Wed, 19 Apr 2023 06:17:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231963AbjDSGRq (ORCPT ); Wed, 19 Apr 2023 02:17:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231779AbjDSGR3 (ORCPT ); Wed, 19 Apr 2023 02:17:29 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D2B75276; Tue, 18 Apr 2023 23:17:27 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HFj2022684; Wed, 19 Apr 2023 01:17:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681885035; bh=OXCA3LIay5KHENJF7Dc2nVxwrTCC4FSZPftHlfXQhNA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gUPHjFpCzrxKbwf5KWG0shB5O9SF8pgie2YQEJs9/0MeuAP1fw7KexW3/KQntJNU2 VBIs5ikgf95RwlulLlR/64RN4n22nn+tmD932F4gvq9kmzD6Gb6fcyhKmh+qe8ov3/ n4nr3m5khxpCOsFpsuaiyjAB44PfVuBmwiK8aZRo= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33J6HF17125772 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Apr 2023 01:17:15 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 19 Apr 2023 01:17:15 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 19 Apr 2023 01:17:15 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33J6HE9Q045442; Wed, 19 Apr 2023 01:17:15 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , Subject: [PATCH v3 3/5] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes Date: Wed, 19 Apr 2023 11:47:08 +0530 Message-ID: <20230419061710.290068-4-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419061710.290068-1-j-choudhary@ti.com> References: <20230419061710.290068-1-j-choudhary@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli J784S4 SoC has 4 Serdes instances along with their respective WIZ instances. Add device-tree nodes for them and disable them by default. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 171 +++++++++++++++++++++ 1 file changed, 171 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 8bd8aebebe1c..51aa476dedba 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -7,6 +7,15 @@ =20 #include #include +#include +#include + +/ { + serdes_refclk: serdes-refclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + }; +}; =20 &cbass_main { msmc_ram: sram@70000000 { @@ -440,6 +449,168 @@ main_sdhci1: mmc@4fb0000 { status =3D "disabled"; }; =20 + serdes_wiz0: wiz@5060000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 404 2>, <&k3_clks 404 6>, <&k3_clks 404 5>, <&serde= s_refclk>; + clock-names =3D "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks =3D <&k3_clks 404 6>; + assigned-clock-parents =3D <&k3_clks 404 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x5060000 0x00 0x5060000 0x10000>; + + status =3D "disabled"; + + serdes0: serdes@5060000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05060000 0x010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz0 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 404 6>, + <&k3_clks 404 6>, + <&k3_clks 404 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + + status =3D "disabled"; + }; + }; + + serdes_wiz1: wiz@5070000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 405 2>, <&k3_clks 405 6>, <&k3_clks 405 5>, <&serde= s_refclk>; + clock-names =3D "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks =3D <&k3_clks 405 6>; + assigned-clock-parents =3D <&k3_clks 405 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x05070000 0x00 0x05070000 0x10000>; + + status =3D "disabled"; + + serdes1: serdes@5070000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05070000 0x010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz1 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 405 6>, + <&k3_clks 405 6>, + <&k3_clks 405 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + + status =3D "disabled"; + }; + }; + + serdes_wiz2: wiz@5020000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 406 2>, <&k3_clks 406 6>, <&k3_clks 406 5>, <&serde= s_refclk>; + clock-names =3D "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks =3D <&k3_clks 406 6>; + assigned-clock-parents =3D <&k3_clks 406 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x05020000 0x00 0x05020000 0x10000>; + + status =3D "disabled"; + + serdes2: serdes@5020000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05020000 0x010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz2 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 406 6>, + <&k3_clks 406 6>, + <&k3_clks 406 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + + status =3D "disabled"; + }; + }; + + serdes_wiz4: wiz@5050000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 407 2>, <&k3_clks 407 6>, <&k3_clks 407 5>, <&serde= s_refclk>; + clock-names =3D "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk"; + assigned-clocks =3D <&k3_clks 407 6>; + assigned-clock-parents =3D <&k3_clks 407 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x05050000 0x00 0x05050000 0x10000>, + <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ + + status =3D "disabled"; + + serdes4: serdes@5050000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05050000 0x010000>, + <0x0a030a00 0x40>; /* DPTX PHY */ + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz4 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 407 6>, + <&k3_clks 407 6>, + <&k3_clks 407 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + + status =3D "disabled"; + }; + }; + main_navss: bus@30000000 { compatible =3D "simple-bus"; #address-cells =3D <2>; --=20 2.25.1