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charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230419062755epcas2p43a1127f4bb28cf1cf3f42e5d3cc597cd References: <20230419060639.38853-1-jaewon02.kim@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Interrupt based pio mode is supported to reduce CPU load. If transfer size is larger than 32 byte, it is processed using interrupt. Signed-off-by: Jaewon Kim --- drivers/spi/spi-s3c64xx.c | 82 ++++++++++++++++++++++++++++++++------- 1 file changed, 67 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index cf3060b2639b..ce1afb9a4ed4 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -58,6 +58,8 @@ #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) +#define S3C64XX_SPI_MODE_RX_RDY_LVL GENMASK(16, 11) +#define S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT 11 #define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) @@ -114,6 +116,8 @@ =20 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT =20 +#define S3C64XX_SPI_POLLING_SIZE 32 + #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) #define is_polling(x) (x->cntrlr_info->polling) =20 @@ -552,10 +556,11 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_dr= iver_data *sdd, } =20 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, - struct spi_transfer *xfer) + struct spi_transfer *xfer, int use_irq) { void __iomem *regs =3D sdd->regs; unsigned long val; + unsigned long time; u32 status; int loops; u32 cpy_len; @@ -563,17 +568,24 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_dr= iver_data *sdd, int ms; u32 tx_time; =20 - /* sleep during signal transfer time */ - status =3D readl(regs + S3C64XX_SPI_STATUS); - if (RX_FIFO_LVL(status, sdd) < xfer->len) { - tx_time =3D (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed; - usleep_range(tx_time / 2, tx_time); - } - /* millisecs to xfer 'len' bytes @ 'cur_speed' */ ms =3D xfer->len * 8 * 1000 / sdd->cur_speed; ms +=3D 10; /* some tolerance */ =20 + if (use_irq) { + val =3D msecs_to_jiffies(ms); + time =3D wait_for_completion_timeout(&sdd->xfer_completion, val); + if (!time) + return -EIO; + } else { + /* sleep during signal transfer time */ + status =3D readl(regs + S3C64XX_SPI_STATUS); + if (RX_FIFO_LVL(status, sdd) < xfer->len) { + tx_time =3D (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed; + usleep_range(tx_time / 2, tx_time); + } + } + val =3D msecs_to_loops(ms); do { cpu_relax(); @@ -737,10 +749,13 @@ static int s3c64xx_spi_transfer_one(struct spi_master= *master, void *rx_buf =3D NULL; int target_len =3D 0, origin_len =3D 0; int use_dma =3D 0; + int use_irq =3D 0; int status; u32 speed; u8 bpw; unsigned long flags; + u32 rdy_lv; + u32 val; =20 reinit_completion(&sdd->xfer_completion); =20 @@ -761,17 +776,46 @@ static int s3c64xx_spi_transfer_one(struct spi_master= *master, sdd->rx_dma.ch && sdd->tx_dma.ch) { use_dma =3D 1; =20 - } else if (xfer->len > fifo_len) { + } else if (xfer->len >=3D fifo_len) { tx_buf =3D xfer->tx_buf; rx_buf =3D xfer->rx_buf; origin_len =3D xfer->len; - target_len =3D xfer->len; - if (xfer->len > fifo_len) - xfer->len =3D fifo_len; + xfer->len =3D fifo_len - 1; } =20 do { + /* transfer size is greater than 32, change to IRQ mode */ + if (xfer->len > S3C64XX_SPI_POLLING_SIZE) + use_irq =3D 1; + + if (use_irq) { + reinit_completion(&sdd->xfer_completion); + + rdy_lv =3D xfer->len; + /* Setup RDY_FIFO trigger Level + * RDY_LVL =3D + * fifo_lvl up to 64 byte -> N bytes + * 128 byte -> RDY_LVL * 2 bytes + * 256 byte -> RDY_LVL * 4 bytes + */ + if (fifo_len =3D=3D 128) + rdy_lv /=3D 2; + else if (fifo_len =3D=3D 256) + rdy_lv /=3D 4; + + val =3D readl(sdd->regs + S3C64XX_SPI_MODE_CFG); + val &=3D ~S3C64XX_SPI_MODE_RX_RDY_LVL; + val |=3D (rdy_lv << S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT); + writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG); + + /* Enable FIFO_RDY_EN IRQ */ + val =3D readl(sdd->regs + S3C64XX_SPI_INT_EN); + writel((val | S3C64XX_SPI_INT_RX_FIFORDY_EN), + sdd->regs + S3C64XX_SPI_INT_EN); + + } + spin_lock_irqsave(&sdd->lock, flags); =20 /* Pending only which is to be done */ @@ -793,7 +837,7 @@ static int s3c64xx_spi_transfer_one(struct spi_master *= master, if (use_dma) status =3D s3c64xx_wait_for_dma(sdd, xfer); else - status =3D s3c64xx_wait_for_pio(sdd, xfer); + status =3D s3c64xx_wait_for_pio(sdd, xfer, use_irq); =20 if (status) { dev_err(&spi->dev, @@ -832,8 +876,8 @@ static int s3c64xx_spi_transfer_one(struct spi_master *= master, if (xfer->rx_buf) xfer->rx_buf +=3D xfer->len; =20 - if (target_len > fifo_len) - xfer->len =3D fifo_len; + if (target_len >=3D fifo_len) + xfer->len =3D fifo_len - 1; else xfer->len =3D target_len; } @@ -1003,6 +1047,14 @@ static irqreturn_t s3c64xx_spi_irq(int irq, void *da= ta) dev_err(&spi->dev, "TX underrun\n"); } =20 + if (val & S3C64XX_SPI_ST_RX_FIFORDY) { + complete(&sdd->xfer_completion); + /* No pending clear irq, turn-off INT_EN_RX_FIFO_RDY */ + val =3D readl(sdd->regs + S3C64XX_SPI_INT_EN); + writel((val & ~S3C64XX_SPI_INT_RX_FIFORDY_EN), + sdd->regs + S3C64XX_SPI_INT_EN); + } + /* Clear the pending irq by setting and then clearing it */ writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); --=20 2.17.1