From nobody Wed Dec 17 15:08:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0240AC77B7A for ; Wed, 19 Apr 2023 03:57:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232063AbjDSD47 convert rfc822-to-8bit (ORCPT ); Tue, 18 Apr 2023 23:56:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231667AbjDSD4x (ORCPT ); Tue, 18 Apr 2023 23:56:53 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC7075FFE; Tue, 18 Apr 2023 20:56:51 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 6B8F724E1B5; Wed, 19 Apr 2023 11:56:50 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:50 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:49 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , Hal Feng , , , Subject: [RESEND v2 1/6] dt-bindings: power: Add JH7110 AON PMU support Date: Tue, 18 Apr 2023 20:56:41 -0700 Message-ID: <20230419035646.43702-2-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419035646.43702-1-changhuang.liang@starfivetech.com> References: <20230419035646.43702-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add AON PMU for StarFive JH7110 SoC, it can be used to turn on/off DPHY rx/tx power switch, and it don't need the properties of reg and interrupts. Signed-off-by: Changhuang Liang --- .../bindings/power/starfive,jh7110-pmu.yaml | 15 +++++++++++++-- include/dt-bindings/power/starfive,jh7110-pmu.h | 3 +++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.ya= ml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml index 98eb8b4110e7..c50507c38e14 100644 --- a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml +++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml @@ -8,6 +8,7 @@ title: StarFive JH7110 Power Management Unit =20 maintainers: - Walker Chen + - Changhuang Liang =20 description: | StarFive JH7110 SoC includes support for multiple power domains which ca= n be @@ -17,6 +18,7 @@ properties: compatible: enum: - starfive,jh7110-pmu + - starfive,jh7110-aon-pmu =20 reg: maxItems: 1 @@ -29,10 +31,19 @@ properties: =20 required: - compatible - - reg - - interrupts - "#power-domain-cells" =20 +allOf: + - if: + properties: + compatible: + contains: + const: starfive,jh7110-pmu + then: + required: + - reg + - interrupts + additionalProperties: false =20 examples: diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-b= indings/power/starfive,jh7110-pmu.h index 132bfe401fc8..0bfd6700c144 100644 --- a/include/dt-bindings/power/starfive,jh7110-pmu.h +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -14,4 +14,7 @@ #define JH7110_PD_ISP 5 #define JH7110_PD_VENC 6 =20 +#define JH7110_PD_DPHY_TX 0 +#define JH7110_PD_DPHY_RX 1 + #endif --=20 2.25.1 From nobody Wed Dec 17 15:08:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B52AC6FD18 for ; Wed, 19 Apr 2023 03:57:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232156AbjDSD5D convert rfc822-to-8bit (ORCPT ); Tue, 18 Apr 2023 23:57:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231797AbjDSD4x (ORCPT ); Tue, 18 Apr 2023 23:56:53 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C1FD5FC4; Tue, 18 Apr 2023 20:56:52 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 2B7CA24E01C; Wed, 19 Apr 2023 11:56:51 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:51 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:50 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , Hal Feng , , , Subject: [RESEND v2 2/6] soc: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Date: Tue, 18 Apr 2023 20:56:42 -0700 Message-ID: <20230419035646.43702-3-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419035646.43702-1-changhuang.liang@starfivetech.com> References: <20230419035646.43702-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Using ARCH_FOO symbol is preferred than SOC_FOO. Reviewed-by: Conor Dooley Reviewed-by: Walker Chen Signed-off-by: Changhuang Liang --- drivers/soc/starfive/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig index bdb96dc4c989..1e9b0c414fec 100644 --- a/drivers/soc/starfive/Kconfig +++ b/drivers/soc/starfive/Kconfig @@ -3,8 +3,8 @@ config JH71XX_PMU bool "Support PMU for StarFive JH71XX Soc" depends on PM - depends on SOC_STARFIVE || COMPILE_TEST - default SOC_STARFIVE + depends on ARCH_STARFIVE || COMPILE_TEST + default ARCH_STARFIVE select PM_GENERIC_DOMAINS help Say 'y' here to enable support power domain support. --=20 2.25.1 From nobody Wed Dec 17 15:08:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8019CC77B73 for ; Wed, 19 Apr 2023 03:57:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232242AbjDSD5I convert rfc822-to-8bit (ORCPT ); Tue, 18 Apr 2023 23:57:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231902AbjDSD4z (ORCPT ); Tue, 18 Apr 2023 23:56:55 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A0715FD1; Tue, 18 Apr 2023 20:56:53 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 3EF1524E2AF; Wed, 19 Apr 2023 11:56:52 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:52 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:50 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , Hal Feng , , , Subject: [RESEND v2 3/6] soc: starfive: Modify ioremap to regmap Date: Tue, 18 Apr 2023 20:56:43 -0700 Message-ID: <20230419035646.43702-4-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419035646.43702-1-changhuang.liang@starfivetech.com> References: <20230419035646.43702-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Modify ioremap to regmap which can be compatible with the syscon interface, such as: struct regmap *syscon_node_to_regmap(struct device_node *np) Convenient introduction of syscon operation. Signed-off-by: Changhuang Liang --- drivers/soc/starfive/jh71xx_pmu.c | 43 +++++++++++++++++-------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71x= x_pmu.c index 7d5f50d71c0d..306218c83691 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -6,13 +6,13 @@ */ =20 #include -#include -#include +#include #include #include #include #include #include +#include #include =20 /* register offset */ @@ -59,7 +59,7 @@ struct jh71xx_pmu_match_data { struct jh71xx_pmu { struct device *dev; const struct jh71xx_pmu_match_data *match_data; - void __iomem *base; + struct regmap *base; struct generic_pm_domain **genpd; struct genpd_onecell_data genpd_data; int irq; @@ -75,11 +75,14 @@ struct jh71xx_pmu_dev { static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= *is_on) { struct jh71xx_pmu *pmu =3D pmd->pmu; + unsigned int val; =20 if (!mask) return -EINVAL; =20 - *is_on =3D readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask; + regmap_read(pmu->base, JH71XX_PMU_CURR_POWER_MODE, &val); + + *is_on =3D val & mask; =20 return 0; } @@ -130,7 +133,7 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *= pmd, u32 mask, bool on) encourage_hi =3D JH71XX_PMU_SW_ENCOURAGE_DIS_HI; } =20 - writel(mask, pmu->base + mode); + regmap_write(pmu->base, mode, mask); =20 /* * 2.Write SW encourage command sequence to the Software Encourage Reg (o= ffset 0x44) @@ -140,21 +143,21 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev= *pmd, u32 mask, bool on) * Then write the lower bits of the command sequence, followed by the u= pper * bits. The sequence differs between powering on & off a domain. */ - writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE); - writel(encourage_lo, pmu->base + JH71XX_PMU_SW_ENCOURAGE); - writel(encourage_hi, pmu->base + JH71XX_PMU_SW_ENCOURAGE); + regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, JH71XX_PMU_SW_ENCOURAGE_= ON); + regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, encourage_lo); + regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, encourage_hi); =20 spin_unlock_irqrestore(&pmu->lock, flags); =20 /* Wait for the power domain bit to be enabled / disabled */ if (on) { - ret =3D readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE, - val, val & mask, - 1, JH71XX_PMU_TIMEOUT_US); + ret =3D regmap_read_poll_timeout_atomic(pmu->base, JH71XX_PMU_CURR_POWER= _MODE, + val, val & mask, + 1, JH71XX_PMU_TIMEOUT_US); } else { - ret =3D readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE, - val, !(val & mask), - 1, JH71XX_PMU_TIMEOUT_US); + ret =3D regmap_read_poll_timeout_atomic(pmu->base, JH71XX_PMU_CURR_POWER= _MODE, + val, !(val & mask), + 1, JH71XX_PMU_TIMEOUT_US); } =20 if (ret) { @@ -190,14 +193,14 @@ static void jh71xx_pmu_int_enable(struct jh71xx_pmu *= pmu, u32 mask, bool enable) unsigned long flags; =20 spin_lock_irqsave(&pmu->lock, flags); - val =3D readl(pmu->base + JH71XX_PMU_TIMER_INT_MASK); + regmap_read(pmu->base, JH71XX_PMU_TIMER_INT_MASK, &val); =20 if (enable) val &=3D ~mask; else val |=3D mask; =20 - writel(val, pmu->base + JH71XX_PMU_TIMER_INT_MASK); + regmap_write(pmu->base, JH71XX_PMU_TIMER_INT_MASK, val); spin_unlock_irqrestore(&pmu->lock, flags); } =20 @@ -206,7 +209,7 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *= data) struct jh71xx_pmu *pmu =3D data; u32 val; =20 - val =3D readl(pmu->base + JH71XX_PMU_INT_STATUS); + regmap_read(pmu->base, JH71XX_PMU_INT_STATUS, &val); =20 if (val & JH71XX_PMU_INT_SEQ_DONE) dev_dbg(pmu->dev, "sequence done.\n"); @@ -220,8 +223,8 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *= data) dev_err(pmu->dev, "p-channel fail event.\n"); =20 /* clear interrupts */ - writel(val, pmu->base + JH71XX_PMU_INT_STATUS); - writel(val, pmu->base + JH71XX_PMU_EVENT_STATUS); + regmap_write(pmu->base, JH71XX_PMU_INT_STATUS, val); + regmap_write(pmu->base, JH71XX_PMU_EVENT_STATUS, val); =20 return IRQ_HANDLED; } @@ -271,7 +274,7 @@ static int jh71xx_pmu_probe(struct platform_device *pde= v) if (!pmu) return -ENOMEM; =20 - pmu->base =3D devm_platform_ioremap_resource(pdev, 0); + pmu->base =3D device_node_to_regmap(np); if (IS_ERR(pmu->base)) return PTR_ERR(pmu->base); =20 --=20 2.25.1 From nobody Wed Dec 17 15:08:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2B90C77B73 for ; Wed, 19 Apr 2023 03:57:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232097AbjDSD5X convert rfc822-to-8bit (ORCPT ); Tue, 18 Apr 2023 23:57:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231963AbjDSD44 (ORCPT ); Tue, 18 Apr 2023 23:56:56 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34D5A5FC4; Tue, 18 Apr 2023 20:56:54 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 014A524E2B4; Wed, 19 Apr 2023 11:56:53 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:52 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:51 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , Hal Feng , , , Subject: [RESEND v2 4/6] soc: starfive: Extract JH7110 pmu private operations Date: Tue, 18 Apr 2023 20:56:44 -0700 Message-ID: <20230419035646.43702-5-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419035646.43702-1-changhuang.liang@starfivetech.com> References: <20230419035646.43702-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move JH7110 private operation into private data of compatible. Convenient to expand different compatible. Signed-off-by: Changhuang Liang --- drivers/soc/starfive/jh71xx_pmu.c | 98 +++++++++++++++++++++---------- 1 file changed, 67 insertions(+), 31 deletions(-) diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71x= x_pmu.c index 306218c83691..bb44cc93e822 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -51,9 +51,17 @@ struct jh71xx_domain_info { u8 bit; }; =20 +struct jh71xx_pmu; +struct jh71xx_pmu_dev; + struct jh71xx_pmu_match_data { const struct jh71xx_domain_info *domain_info; int num_domains; + unsigned int pmu_status; + int (*pmu_parse_dt)(struct platform_device *pdev, + struct jh71xx_pmu *pmu); + int (*pmu_set_state)(struct jh71xx_pmu_dev *pmd, + u32 mask, bool on); }; =20 struct jh71xx_pmu { @@ -80,14 +88,14 @@ static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *= pmd, u32 mask, bool *is_o if (!mask) return -EINVAL; =20 - regmap_read(pmu->base, JH71XX_PMU_CURR_POWER_MODE, &val); + regmap_read(pmu->base, pmu->match_data->pmu_status, &val); =20 *is_on =3D val & mask; =20 return 0; } =20 -static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= on) +static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= on) { struct jh71xx_pmu *pmu =3D pmd->pmu; unsigned long flags; @@ -95,22 +103,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *= pmd, u32 mask, bool on) u32 mode; u32 encourage_lo; u32 encourage_hi; - bool is_on; int ret; =20 - ret =3D jh71xx_pmu_get_state(pmd, mask, &is_on); - if (ret) { - dev_dbg(pmu->dev, "unable to get current state for %s\n", - pmd->genpd.name); - return ret; - } - - if (is_on =3D=3D on) { - dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", - pmd->genpd.name, on ? "en" : "dis"); - return 0; - } - spin_lock_irqsave(&pmu->lock, flags); =20 /* @@ -169,6 +163,29 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev = *pmd, u32 mask, bool on) return 0; } =20 +static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= on) +{ + struct jh71xx_pmu *pmu =3D pmd->pmu; + const struct jh71xx_pmu_match_data *match_data =3D pmu->match_data; + bool is_on; + int ret; + + ret =3D jh71xx_pmu_get_state(pmd, mask, &is_on); + if (ret) { + dev_dbg(pmu->dev, "unable to get current state for %s\n", + pmd->genpd.name); + return ret; + } + + if (is_on =3D=3D on) { + dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", + pmd->genpd.name, on ? "en" : "dis"); + return 0; + } + + return match_data->pmu_set_state(pmd, mask, on); +} + static int jh71xx_pmu_on(struct generic_pm_domain *genpd) { struct jh71xx_pmu_dev *pmd =3D container_of(genpd, @@ -229,6 +246,30 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void = *data) return IRQ_HANDLED; } =20 +static int jh7110_pmu_parse_dt(struct platform_device *pdev, struct jh71xx= _pmu *pmu) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + int ret; + + pmu->base =3D device_node_to_regmap(np); + if (IS_ERR(pmu->base)) + return PTR_ERR(pmu->base); + + pmu->irq =3D platform_get_irq(pdev, 0); + if (pmu->irq < 0) + return pmu->irq; + + ret =3D devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, + 0, pdev->name, pmu); + if (ret) + dev_err(dev, "failed to request irq\n"); + + jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_= FAIL, true); + + return 0; +} + static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index) { struct jh71xx_pmu_dev *pmd; @@ -274,23 +315,18 @@ static int jh71xx_pmu_probe(struct platform_device *p= dev) if (!pmu) return -ENOMEM; =20 - pmu->base =3D device_node_to_regmap(np); - if (IS_ERR(pmu->base)) - return PTR_ERR(pmu->base); - - pmu->irq =3D platform_get_irq(pdev, 0); - if (pmu->irq < 0) - return pmu->irq; - - ret =3D devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, - 0, pdev->name, pmu); - if (ret) - dev_err(dev, "failed to request irq\n"); + spin_lock_init(&pmu->lock); =20 match_data =3D of_device_get_match_data(dev); if (!match_data) return -EINVAL; =20 + ret =3D match_data->pmu_parse_dt(pdev, pmu); + if (ret) { + dev_err(dev, "failed to parse dt\n"); + return ret; + } + pmu->genpd =3D devm_kcalloc(dev, match_data->num_domains, sizeof(struct generic_pm_domain *), GFP_KERNEL); @@ -310,9 +346,6 @@ static int jh71xx_pmu_probe(struct platform_device *pde= v) } } =20 - spin_lock_init(&pmu->lock); - jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_= FAIL, true); - ret =3D of_genpd_add_provider_onecell(np, &pmu->genpd_data); if (ret) { dev_err(dev, "failed to register genpd driver: %d\n", ret); @@ -360,6 +393,9 @@ static const struct jh71xx_domain_info jh7110_power_dom= ains[] =3D { static const struct jh71xx_pmu_match_data jh7110_pmu =3D { .num_domains =3D ARRAY_SIZE(jh7110_power_domains), .domain_info =3D jh7110_power_domains, + .pmu_status =3D JH71XX_PMU_CURR_POWER_MODE, + .pmu_parse_dt =3D jh7110_pmu_parse_dt, + .pmu_set_state =3D jh7110_pmu_set_state, }; =20 static const struct of_device_id jh71xx_pmu_of_match[] =3D { --=20 2.25.1 From nobody Wed Dec 17 15:08:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDE27C77B73 for ; Wed, 19 Apr 2023 03:57:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232220AbjDSD5P convert rfc822-to-8bit (ORCPT ); Tue, 18 Apr 2023 23:57:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231958AbjDSD44 (ORCPT ); Tue, 18 Apr 2023 23:56:56 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6F2961AF; Tue, 18 Apr 2023 20:56:54 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 97E2D24E22D; Wed, 19 Apr 2023 11:56:53 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:53 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:52 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , Hal Feng , , , Subject: [RESEND v2 5/6] soc: starfive: Add JH7110 AON PMU support Date: Tue, 18 Apr 2023 20:56:45 -0700 Message-ID: <20230419035646.43702-6-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419035646.43702-1-changhuang.liang@starfivetech.com> References: <20230419035646.43702-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the dphy rx/tx power switch. Reviewed-by: Walker Chen Signed-off-by: Changhuang Liang --- MAINTAINERS | 1 + drivers/soc/starfive/jh71xx_pmu.c | 63 ++++++++++++++++++++++++++++++- 2 files changed, 63 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 0fafeea8ebdb..8f32d43a9b67 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19950,6 +19950,7 @@ F: include/dt-bindings/reset/starfive?jh71*.h =20 STARFIVE JH71XX PMU CONTROLLER DRIVER M: Walker Chen +M: Changhuang Liang S: Supported F: Documentation/devicetree/bindings/power/starfive* F: drivers/soc/starfive/jh71xx_pmu.c diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71x= x_pmu.c index bb44cc93e822..1303826aa7b5 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -2,7 +2,7 @@ /* * StarFive JH71XX PMU (Power Management Unit) Controller Driver * - * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. */ =20 #include @@ -24,6 +24,9 @@ #define JH71XX_PMU_EVENT_STATUS 0x88 #define JH71XX_PMU_INT_STATUS 0x8C =20 +/* aon pmu register offset */ +#define JH71XX_AON_PMU_SWITCH 0x00 + /* sw encourage cfg */ #define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05 #define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50 @@ -163,6 +166,23 @@ static int jh7110_pmu_set_state(struct jh71xx_pmu_dev = *pmd, u32 mask, bool on) return 0; } =20 +static int jh7110_aon_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, = bool on) +{ + struct jh71xx_pmu *pmu =3D pmd->pmu; + unsigned long flags; + + spin_lock_irqsave(&pmu->lock, flags); + + if (on) + regmap_update_bits(pmu->base, JH71XX_AON_PMU_SWITCH, mask, mask); + else + regmap_update_bits(pmu->base, JH71XX_AON_PMU_SWITCH, mask, 0); + + spin_unlock_irqrestore(&pmu->lock, flags); + + return 0; +} + static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= on) { struct jh71xx_pmu *pmu =3D pmd->pmu; @@ -270,6 +290,24 @@ static int jh7110_pmu_parse_dt(struct platform_device = *pdev, struct jh71xx_pmu * return 0; } =20 +static int jh7110_aon_pmu_parse_dt(struct platform_device *pdev, struct jh= 71xx_pmu *pmu) +{ + struct device *parent; + struct device *dev =3D &pdev->dev; + + parent =3D pdev->dev.parent; + if (!parent) { + dev_err(dev, "No parent for syscon pmu\n"); + return -ENODEV; + } + + pmu->base =3D syscon_node_to_regmap(parent->of_node); + if (IS_ERR(pmu->base)) + return PTR_ERR(pmu->base); + + return 0; +} + static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index) { struct jh71xx_pmu_dev *pmd; @@ -398,10 +436,32 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = =3D { .pmu_set_state =3D jh7110_pmu_set_state, }; =20 +static const struct jh71xx_domain_info jh7110_aon_power_domains[] =3D { + [JH7110_PD_DPHY_TX] =3D { + .name =3D "DPHY-TX", + .bit =3D 30, + }, + [JH7110_PD_DPHY_RX] =3D { + .name =3D "DPHY-RX", + .bit =3D 31, + }, +}; + +static const struct jh71xx_pmu_match_data jh7110_aon_pmu =3D { + .num_domains =3D ARRAY_SIZE(jh7110_aon_power_domains), + .domain_info =3D jh7110_aon_power_domains, + .pmu_status =3D JH71XX_AON_PMU_SWITCH, + .pmu_parse_dt =3D jh7110_aon_pmu_parse_dt, + .pmu_set_state =3D jh7110_aon_pmu_set_state, +}; + static const struct of_device_id jh71xx_pmu_of_match[] =3D { { .compatible =3D "starfive,jh7110-pmu", .data =3D (void *)&jh7110_pmu, + }, { + .compatible =3D "starfive,jh7110-aon-pmu", + .data =3D (void *)&jh7110_aon_pmu, }, { /* sentinel */ } @@ -418,5 +478,6 @@ static struct platform_driver jh71xx_pmu_driver =3D { builtin_platform_driver(jh71xx_pmu_driver); =20 MODULE_AUTHOR("Walker Chen "); +MODULE_AUTHOR("Changhuang Liang "); MODULE_DESCRIPTION("StarFive JH71XX PMU Driver"); MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Wed Dec 17 15:08:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25513C6FD18 for ; Wed, 19 Apr 2023 03:57:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232315AbjDSD5b convert rfc822-to-8bit (ORCPT ); Tue, 18 Apr 2023 23:57:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232000AbjDSD44 (ORCPT ); Tue, 18 Apr 2023 23:56:56 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D18AA6183; Tue, 18 Apr 2023 20:56:55 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 488F124E246; Wed, 19 Apr 2023 11:56:54 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:54 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Apr 2023 11:56:53 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , Hal Feng , , , Subject: [RESEND v2 6/6] riscv: dts: starfive: jh7110: Add AON PMU node Date: Tue, 18 Apr 2023 20:56:46 -0700 Message-ID: <20230419035646.43702-7-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419035646.43702-1-changhuang.liang@starfivetech.com> References: <20230419035646.43702-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add AON PMU node to configure power. It can be used to turn on/off dphy rx/tx power switch. Reviewed-by: Walker Chen Signed-off-by: Changhuang Liang --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 27f8ef37d029..3414edc877d5 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -509,6 +509,11 @@ aoncrg: clock-controller@17000000 { aon_syscon: syscon@17010000 { compatible =3D "starfive,jh7110-aon-syscon", "syscon", "simple-mfd"; reg =3D <0x0 0x17010000 0x0 0x1000>; + + aon_pwrc: power-controller { + compatible =3D "starfive,jh7110-aon-pmu"; + #power-domain-cells =3D <1>; + }; }; =20 aongpio: pinctrl@17020000 { --=20 2.25.1