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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id y1-20020a1c4b01000000b003ef5f77901dsm15481832wma.45.2023.04.18.09.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 09:58:29 -0700 (PDT) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Jonas Bonn , Stefan Kristiansson Subject: [PATCH 1/4] openrisc: Properly store r31 to pt_regs on unhandled exceptions Date: Tue, 18 Apr 2023 17:58:10 +0100 Message-Id: <20230418165813.1900991-2-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230418165813.1900991-1-shorne@gmail.com> References: <20230418165813.1900991-1-shorne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In commit 91993c8c2ed5 ("openrisc: use shadow registers to save regs on exception") the unhandled exception path was changed to do an early store of r30 instead of r31. The entry code was not updated and r31 is not getting stored to pt_regs. This patch updates the entry handler to store r31 instead of r30. We also remove some misleading commented out store r30 and r31 instructrions. I noticed this while working on adding floating point exception handling, This issue probably would never impact anything since we kill the process or Oops right away on unhandled exceptions. Fixes: 91993c8c2ed5 ("openrisc: use shadow registers to save regs on except= ion") Signed-off-by: Stafford Horne --- arch/openrisc/kernel/entry.S | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S index 54a87bba35ca..a130c4dac48d 100644 --- a/arch/openrisc/kernel/entry.S +++ b/arch/openrisc/kernel/entry.S @@ -173,7 +173,6 @@ handler: ;\ l.sw PT_GPR28(r1),r28 ;\ l.sw PT_GPR29(r1),r29 ;\ /* r30 already save */ ;\ -/* l.sw PT_GPR30(r1),r30*/ ;\ l.sw PT_GPR31(r1),r31 ;\ TRACE_IRQS_OFF_ENTRY ;\ /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ @@ -211,9 +210,8 @@ handler: ;\ l.sw PT_GPR27(r1),r27 ;\ l.sw PT_GPR28(r1),r28 ;\ l.sw PT_GPR29(r1),r29 ;\ - /* r31 already saved */ ;\ - l.sw PT_GPR30(r1),r30 ;\ -/* l.sw PT_GPR31(r1),r31 */ ;\ + /* r30 already saved */ ;\ + l.sw PT_GPR31(r1),r31 ;\ /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ l.addi r30,r0,-1 ;\ l.sw PT_ORIG_GPR11(r1),r30 ;\ --=20 2.39.1 From nobody Wed Dec 17 15:33:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DADD4C77B7D for ; Tue, 18 Apr 2023 16:58:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232242AbjDRQ6q (ORCPT ); Tue, 18 Apr 2023 12:58:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232130AbjDRQ6g (ORCPT ); Tue, 18 Apr 2023 12:58:36 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D77530F5; Tue, 18 Apr 2023 09:58:34 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id iw7-20020a05600c54c700b003f16fce55b5so221117wmb.0; Tue, 18 Apr 2023 09:58:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681837112; x=1684429112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n6qUjw+9IN0xT2b+Y+r4noQaKqVwfg3S7vKVKrsqDTY=; b=JZ6KOhP4jYskKGLyfwgC4hVeIgqCrD9EybJ11fHq850UrXZ3ol+f0QLRHCfH3BD6Tx Oru7jlPaT56J/4SsHstMJJkCDJ4DJpshJkD1s53uxNyuls71OD0FSKSZatGnsMx4K7U+ 4z0FQqmpQ4hGZf7rOpTnpfZJZgGkkr7AoDBU+NQtAaLU4VV1eFvdlmmLl0U7qMj5ml/U IlhGNeVIIljlHQu7Pf17qf+zkeSvF/4DubeEGoYmE1y+swMtQblaPSmfHliGY3jaewyY c8kHOZ/JZtpBskrq15sGmp33HVSe6GNbMQgHy2zUgUrp2Ty0JFg8KElY9/vYFALyp3lw rDnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681837112; x=1684429112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n6qUjw+9IN0xT2b+Y+r4noQaKqVwfg3S7vKVKrsqDTY=; b=eG0VjPvQVH2ywpP61ZmBi2fgAPhwyuE08Adl+xUoKRS3fnzMqIJoD3yy5tcTje1vhB D2jPjz2oG1GwagCT83GSDQMTLKfoTsZeFjHctIyJFAK8hsj846mELj4AQCQNaJQsTK+2 4wZ0nDiwb07+DArCvQjwoiAdI8Pb+t5EhF27+JnojZ4DDG0Qzc8I9ZHTNaVBfy1RyB+G 8G4bkRjEaR6sEvHbtPkqy4d51zusS2NReoc9AhK19w4GLuFBxwPNZLa8rFUtP2nQXAe2 O6kkmVH24Ja9HOmyNFiKR+TgSOHb5DVGMrT1ZdPFfMKZD2TU+k8kf8gEZ8M6Czh8mlVN nHQA== X-Gm-Message-State: AAQBX9dI6lRNkRQQu23eBH7OzLVYEzz+6brwPaMSkioJG1gRSgRdrjPh rUs7PI58rspP2/67VOyUIcKRaa67Pgw= X-Google-Smtp-Source: AKy350bBQNddun1q5Lfe+bhdAPTidimlCCNDylrVcmCkAAMBiZruZImp4c5onHLe0GkNa4JPw0AzWQ== X-Received: by 2002:a05:600c:d7:b0:3f1:7287:55ad with SMTP id u23-20020a05600c00d700b003f1728755admr6338104wmm.10.1681837112366; Tue, 18 Apr 2023 09:58:32 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id t16-20020a7bc3d0000000b003f1692ebd0asm10262398wmj.3.2023.04.18.09.58.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 09:58:31 -0700 (PDT) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Oleg Nesterov , Jonas Bonn , Stefan Kristiansson Subject: [PATCH 2/4] openrisc: Support storing and restoring fpu state Date: Tue, 18 Apr 2023 17:58:11 +0100 Message-Id: <20230418165813.1900991-3-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230418165813.1900991-1-shorne@gmail.com> References: <20230418165813.1900991-1-shorne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" OpenRISC floating point state is not so expensive to save as OpenRISC uses general purpose registers for floating point instructions. We need to save only the floating point status and control register, FPCSR. Add support to maintain the FPCSR unconditionally upon exceptions and switches. On machines that do not support FPU this will always just store 0x0 and restore is a no-op. On FPU systems this adds an additional special purpose register read/write and read/write to memory (already cached). Signed-off-by: Stafford Horne --- arch/openrisc/include/asm/ptrace.h | 4 ++-- arch/openrisc/kernel/entry.S | 14 ++++++++++++++ arch/openrisc/kernel/traps.c | 5 +++-- 3 files changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm= /ptrace.h index 01f81d4e97dc..375147ff71fc 100644 --- a/arch/openrisc/include/asm/ptrace.h +++ b/arch/openrisc/include/asm/ptrace.h @@ -59,7 +59,7 @@ struct pt_regs { * -1 for all other exceptions. */ long orig_gpr11; /* For restarting system calls */ - long dummy; /* Cheap alignment fix */ + long fpcsr; /* Floating point control status register. */ long dummy2; /* Cheap alignment fix */ }; =20 @@ -115,6 +115,6 @@ static inline long regs_return_value(struct pt_regs *re= gs) #define PT_GPR31 124 #define PT_PC 128 #define PT_ORIG_GPR11 132 -#define PT_SYSCALLNO 136 +#define PT_FPCSR 136 =20 #endif /* __ASM_OPENRISC_PTRACE_H */ diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S index a130c4dac48d..c7b47e571220 100644 --- a/arch/openrisc/kernel/entry.S +++ b/arch/openrisc/kernel/entry.S @@ -106,6 +106,8 @@ l.mtspr r0,r3,SPR_EPCR_BASE ;\ l.lwz r3,PT_SR(r1) ;\ l.mtspr r0,r3,SPR_ESR_BASE ;\ + l.lwz r3,PT_FPCSR(r1) ;\ + l.mtspr r0,r3,SPR_FPCSR ;\ l.lwz r2,PT_GPR2(r1) ;\ l.lwz r3,PT_GPR3(r1) ;\ l.lwz r4,PT_GPR4(r1) ;\ @@ -175,6 +177,8 @@ handler: ;\ /* r30 already save */ ;\ l.sw PT_GPR31(r1),r31 ;\ TRACE_IRQS_OFF_ENTRY ;\ + l.mfspr r30,r0,SPR_FPCSR ;\ + l.sw PT_FPCSR(r1),r30 ;\ /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ l.addi r30,r0,-1 ;\ l.sw PT_ORIG_GPR11(r1),r30 @@ -215,6 +219,8 @@ handler: ;\ /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ l.addi r30,r0,-1 ;\ l.sw PT_ORIG_GPR11(r1),r30 ;\ + l.mfspr r30,r0,SPR_FPCSR ;\ + l.sw PT_FPCSR(r1),r30 ;\ l.addi r3,r1,0 ;\ /* r4 is exception EA */ ;\ l.addi r5,r0,vector ;\ @@ -1087,6 +1093,10 @@ ENTRY(_switch) l.sw PT_GPR28(r1),r28 l.sw PT_GPR30(r1),r30 =20 + /* Store the old FPU state to new pt_regs */ + l.mfspr r29,r0,SPR_FPCSR + l.sw PT_FPCSR(r1),r29 + l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/ =20 /* We use thread_info->ksp for storing the address of the above @@ -1109,6 +1119,10 @@ ENTRY(_switch) l.lwz r29,PT_SP(r1) l.sw TI_KSP(r10),r29 =20 + /* Restore the old value of FPCSR */ + l.lwz r29,PT_FPCSR(r1) + l.mtspr r0,r29,SPR_FPCSR + /* ...and restore the registers, except r11 because the return value * has already been set above. */ diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c index fd9a0f2b66c4..f5bbe6b55849 100644 --- a/arch/openrisc/kernel/traps.c +++ b/arch/openrisc/kernel/traps.c @@ -75,8 +75,9 @@ void show_registers(struct pt_regs *regs) in_kernel =3D 0; =20 printk("CPU #: %d\n" - " PC: %08lx SR: %08lx SP: %08lx\n", - smp_processor_id(), regs->pc, regs->sr, regs->sp); + " PC: %08lx SR: %08lx SP: %08lx FPCSR: %08lx\n", + smp_processor_id(), regs->pc, regs->sr, regs->sp, + regs->fpcsr); printk("GPR00: %08lx GPR01: %08lx GPR02: %08lx GPR03: %08lx\n", 0L, regs->gpr[1], regs->gpr[2], regs->gpr[3]); printk("GPR04: %08lx GPR05: %08lx GPR06: %08lx GPR07: %08lx\n", --=20 2.39.1 From nobody Wed Dec 17 15:33:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C050DC6FD18 for ; Tue, 18 Apr 2023 16:58:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232519AbjDRQ6w (ORCPT ); Tue, 18 Apr 2023 12:58:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232241AbjDRQ6p (ORCPT ); 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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id q17-20020adfdfd1000000b002e4cd2ec5c7sm13514523wrn.86.2023.04.18.09.58.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 09:58:38 -0700 (PDT) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Jonas Bonn , Stefan Kristiansson , Eric Biederman , Kees Cook , "Jason A. Donenfeld" , Dominik Brodowski , linux-mm@kvack.org Subject: [PATCH 3/4] openrisc: Support floating point user api Date: Tue, 18 Apr 2023 17:58:12 +0100 Message-Id: <20230418165813.1900991-4-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230418165813.1900991-1-shorne@gmail.com> References: <20230418165813.1900991-1-shorne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for handling floating point exceptions and forwarding the SIGFPE signal to processes. Also, add fpu state to sigcontext. Signed-off-by: Stafford Horne --- arch/openrisc/include/uapi/asm/elf.h | 3 +-- arch/openrisc/include/uapi/asm/ptrace.h | 4 ++++ arch/openrisc/include/uapi/asm/sigcontext.h | 1 + arch/openrisc/kernel/entry.S | 11 +++++++++-- arch/openrisc/kernel/head.S | 4 ++-- arch/openrisc/kernel/signal.c | 2 ++ arch/openrisc/kernel/traps.c | 22 +++++++++++++++++++++ 7 files changed, 41 insertions(+), 6 deletions(-) diff --git a/arch/openrisc/include/uapi/asm/elf.h b/arch/openrisc/include/u= api/asm/elf.h index e892d5061685..6868f81c281e 100644 --- a/arch/openrisc/include/uapi/asm/elf.h +++ b/arch/openrisc/include/uapi/asm/elf.h @@ -53,8 +53,7 @@ typedef unsigned long elf_greg_t; #define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) typedef elf_greg_t elf_gregset_t[ELF_NGREG]; =20 -/* A placeholder; OR32 does not have fp support yes, so no fp regs for now= . */ -typedef unsigned long elf_fpregset_t; +typedef struct __or1k_fpu_state elf_fpregset_t; =20 /* EM_OPENRISC is defined in linux/elf-em.h */ #define EM_OR32 0x8472 diff --git a/arch/openrisc/include/uapi/asm/ptrace.h b/arch/openrisc/includ= e/uapi/asm/ptrace.h index d4fab268f6aa..a77cc9915ca8 100644 --- a/arch/openrisc/include/uapi/asm/ptrace.h +++ b/arch/openrisc/include/uapi/asm/ptrace.h @@ -30,6 +30,10 @@ struct user_regs_struct { unsigned long pc; unsigned long sr; }; + +struct __or1k_fpu_state { + unsigned long fpcsr; +}; #endif =20 =20 diff --git a/arch/openrisc/include/uapi/asm/sigcontext.h b/arch/openrisc/in= clude/uapi/asm/sigcontext.h index 8ab775fc3450..ca585e4af6b8 100644 --- a/arch/openrisc/include/uapi/asm/sigcontext.h +++ b/arch/openrisc/include/uapi/asm/sigcontext.h @@ -28,6 +28,7 @@ =20 struct sigcontext { struct user_regs_struct regs; /* needs to be first */ + struct __or1k_fpu_state fpu; unsigned long oldmask; }; =20 diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S index c7b47e571220..c9f48e750b72 100644 --- a/arch/openrisc/kernel/entry.S +++ b/arch/openrisc/kernel/entry.S @@ -848,9 +848,16 @@ _syscall_badsys: =20 /******* END SYSCALL HANDLING *******/ =20 -/* ---[ 0xd00: Trap exception ]------------------------------------------ = */ +/* ---[ 0xd00: Floating Point exception ]-------------------------------- = */ =20 -UNHANDLED_EXCEPTION(_vector_0xd00,0xd00) +EXCEPTION_ENTRY(_fpe_trap_handler) + CLEAR_LWA_FLAG(r3) + /* r4: EA of fault (set by EXCEPTION_HANDLE) */ + l.jal do_fpe_trap + l.addi r3,r1,0 /* pt_regs */ + + l.j _ret_from_exception + l.nop =20 /* ---[ 0xe00: Trap exception ]------------------------------------------ = */ =20 diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S index e11699f3d6bd..439e00f81e5d 100644 --- a/arch/openrisc/kernel/head.S +++ b/arch/openrisc/kernel/head.S @@ -424,9 +424,9 @@ _dispatch_do_ipage_fault: .org 0xc00 EXCEPTION_HANDLE(_sys_call_handler) =20 -/* ---[ 0xd00: Trap exception ]------------------------------------------ = */ +/* ---[ 0xd00: Floating point exception ]---------------------------------= */ .org 0xd00 - UNHANDLED_EXCEPTION(_vector_0xd00) + EXCEPTION_HANDLE(_fpe_trap_handler) =20 /* ---[ 0xe00: Trap exception ]------------------------------------------ = */ .org 0xe00 diff --git a/arch/openrisc/kernel/signal.c b/arch/openrisc/kernel/signal.c index 80f69740c731..4664a18f0787 100644 --- a/arch/openrisc/kernel/signal.c +++ b/arch/openrisc/kernel/signal.c @@ -50,6 +50,7 @@ static int restore_sigcontext(struct pt_regs *regs, err |=3D __copy_from_user(regs, sc->regs.gpr, 32 * sizeof(unsigned long)); err |=3D __copy_from_user(®s->pc, &sc->regs.pc, sizeof(unsigned long)); err |=3D __copy_from_user(®s->sr, &sc->regs.sr, sizeof(unsigned long)); + err |=3D __copy_from_user(®s->fpcsr, &sc->fpu.fpcsr, sizeof(unsigned l= ong)); =20 /* make sure the SM-bit is cleared so user-mode cannot fool us */ regs->sr &=3D ~SPR_SR_SM; @@ -112,6 +113,7 @@ static int setup_sigcontext(struct pt_regs *regs, struc= t sigcontext __user *sc) err |=3D __copy_to_user(sc->regs.gpr, regs, 32 * sizeof(unsigned long)); err |=3D __copy_to_user(&sc->regs.pc, ®s->pc, sizeof(unsigned long)); err |=3D __copy_to_user(&sc->regs.sr, ®s->sr, sizeof(unsigned long)); + err |=3D __copy_to_user(&sc->fpu.fpcsr, ®s->fpcsr, sizeof(unsigned lon= g)); =20 return err; } diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c index f5bbe6b55849..0aa6b07efda1 100644 --- a/arch/openrisc/kernel/traps.c +++ b/arch/openrisc/kernel/traps.c @@ -243,6 +243,28 @@ asmlinkage void unhandled_exception(struct pt_regs *re= gs, int ea, int vector) die("Oops", regs, 9); } =20 +asmlinkage void do_fpe_trap(struct pt_regs *regs, unsigned long address) +{ + int code =3D FPE_FLTUNK; + unsigned long fpcsr =3D regs->fpcsr; + + if (fpcsr & SPR_FPCSR_IVF) + code =3D FPE_FLTINV; + else if (fpcsr & SPR_FPCSR_OVF) + code =3D FPE_FLTOVF; + else if (fpcsr & SPR_FPCSR_UNF) + code =3D FPE_FLTUND; + else if (fpcsr & SPR_FPCSR_DZF) + code =3D FPE_FLTDIV; + else if (fpcsr & SPR_FPCSR_IXF) + code =3D FPE_FLTRES; + + /* Clear all flags */ + regs->fpcsr &=3D ~SPR_FPCSR_ALLF; + + force_sig_fault(SIGFPE, code, (void __user *)regs->pc); +} + asmlinkage void do_trap(struct pt_regs *regs, unsigned long address) { force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->pc); --=20 2.39.1 From nobody Wed Dec 17 15:33:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23981C77B78 for ; Tue, 18 Apr 2023 16:58:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232560AbjDRQ65 (ORCPT ); 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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b003f173a00304sm6468978wmp.17.2023.04.18.09.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 09:58:40 -0700 (PDT) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Oleg Nesterov , Jonas Bonn , Stefan Kristiansson Subject: [PATCH 4/4] openrisc: Add floating point regset Date: Tue, 18 Apr 2023 17:58:13 +0100 Message-Id: <20230418165813.1900991-5-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230418165813.1900991-1-shorne@gmail.com> References: <20230418165813.1900991-1-shorne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Define REGSET_FPU to allow reading and writing the FPCSR fpu state register. This will be used primarily by debuggers like GDB. Signed-off-by: Stafford Horne --- arch/openrisc/kernel/ptrace.c | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/openrisc/kernel/ptrace.c b/arch/openrisc/kernel/ptrace.c index 85ace93fc251..f1fc276d46bb 100644 --- a/arch/openrisc/kernel/ptrace.c +++ b/arch/openrisc/kernel/ptrace.c @@ -84,11 +84,40 @@ static int genregs_set(struct task_struct *target, return ret; } =20 +/* + * As OpenRISC shares GPRs and floating point registers we don't need to e= xport + * the floating point registers again. So here we only export the fpcsr s= pecial + * purpose register. + */ +static int fpregs_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + const struct pt_regs *regs =3D task_pt_regs(target); + + return membuf_store(&to, regs->fpcsr); +} + +static int fpregs_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + struct pt_regs *regs =3D task_pt_regs(target); + int ret; + + /* FPCSR */ + ret =3D user_regset_copyin(&pos, &count, &kbuf, &ubuf, + ®s->fpcsr, 0, 4); + return ret; +} + /* * Define the register sets available on OpenRISC under Linux */ enum or1k_regset { REGSET_GENERAL, + REGSET_FPU, }; =20 static const struct user_regset or1k_regsets[] =3D { @@ -100,6 +129,14 @@ static const struct user_regset or1k_regsets[] =3D { .regset_get =3D genregs_get, .set =3D genregs_set, }, + [REGSET_FPU] =3D { + .core_note_type =3D NT_PRFPREG, + .n =3D sizeof(struct __or1k_fpu_state) / sizeof(long), + .size =3D sizeof(long), + .align =3D sizeof(long), + .regset_get =3D fpregs_get, + .set =3D fpregs_set, + }, }; =20 static const struct user_regset_view user_or1k_native_view =3D { --=20 2.39.1