From nobody Mon Feb 9 16:16:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C12BC77B75 for ; Tue, 18 Apr 2023 07:49:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231419AbjDRHtI (ORCPT ); Tue, 18 Apr 2023 03:49:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231224AbjDRHsW (ORCPT ); Tue, 18 Apr 2023 03:48:22 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 974295FEC; Tue, 18 Apr 2023 00:48:11 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id sz19so13756797ejc.2; Tue, 18 Apr 2023 00:48:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681804090; x=1684396090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l19cpi11+VLyNXUHh2KnWwPalv9JqFIq3IuDMicAupg=; b=pSX84xqzROANM2hGagaRoX4id6ox42yfA50GClMgbs+YZH7nTYGOdUgWghtiKreplP NQv8ZMH3HV9fhzQVoF/zoWyl2qL5mVYr2QUicz0exYzD9qFqbWtbbk+6+KFropKfzUGm Sa5YJab2vdhC5y+gdkjyc0oqAun1dee6tCcVnlPPNgElOe8QMr85r3l6GpH0BV+h68KO gE5MLYyFFbHiHwEXFdyX+HVRJKkpBXOGTPJDxOfP0QQXhdibcX6q9HNL1pcEw1yXI+ZE UvSceRdFCa0cS7VTF0nKywgHarEoqh3WRCsRjA44bFTSh0hI49NZzTvVFETNdrcwp2Ez CPZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681804090; x=1684396090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l19cpi11+VLyNXUHh2KnWwPalv9JqFIq3IuDMicAupg=; b=Y2cBnJYaMvZTyo0ufjx1wM9x34biLvT8ww6oU8h4ZKQQAj9e5VP7DBragAgtzVYyP/ urA47XvCfDzWy9QOj60K6kuJ+vOLWf/429X71s8JMFC6y8YY7Zpd5w1Q1dao8T+J9i15 kCrQVPuo40k5veXHQQBC5/8Byttr3/jp5CsXZFG8rvpQGaxvKXWVe1NOXGxoZP2kc7xA PxdDiKFHzcQG0TYbTcbAEp13q7m3cjmI25TH423G8jR+iFalAVFGv5OUyslJRsCoziar AfNBSrN1I/Zcw4KFVBCjinYN+zaTT33gzeCEoys3OPZiMNv67zxjjij0v4TWiPCs5bYK O81A== X-Gm-Message-State: AAQBX9eGUg3sKdWxknI88vbCQvcnmpP0wdBP0t6aoumcTXNzGW8lAetZ u//3v+FFBUdof5ow/iQPxaU= X-Google-Smtp-Source: AKy350YBgXj2bPbCmHnmYdvZoLazNpv7yPdzMrGyRKc78iy8XexClRw1CNKw6QRlNpVA0xR9I2rrrQ== X-Received: by 2002:a17:907:160b:b0:94f:9cd7:adff with SMTP id hb11-20020a170907160b00b0094f9cd7adffmr4663896ejc.18.1681804089808; Tue, 18 Apr 2023 00:48:09 -0700 (PDT) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id gs8-20020a1709072d0800b0094f694e4ecbsm3048545ejc.146.2023.04.18.00.48.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 00:48:09 -0700 (PDT) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, dlemoal@kernel.org, Rick Wertenbroek , stable@vger.kernel.org, Shawn Lin , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Brian Norris , Caleb Connolly , Corentin Labbe , Johan Jonker , Judy Hsiao , Hugh Cole-Baker , Arnaud Ferraris , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 09/11] PCI: rockchip: Use u32 variable to access 32-bit registers Date: Tue, 18 Apr 2023 09:46:56 +0200 Message-Id: <20230418074700.1083505-10-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230418074700.1083505-1-rick.wertenbroek@gmail.com> References: <20230418074700.1083505-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously u16 variables were used to access 32-bit registers, this resulted in not all of the data being read from the registers. Also the left shift of more than 16-bits would result in moving data out of the variable. Use u32 variables to access 32-bit registers Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe contro= ller") Cc: stable@vger.kernel.org Tested-by: Damien Le Moal Reviewed-by: Damien Le Moal Signed-off-by: Rick Wertenbroek --- drivers/pci/controller/pcie-rockchip-ep.c | 10 +++++----- drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/contro= ller/pcie-rockchip-ep.c index 771f1bb93251..63fbb379638b 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -271,15 +271,15 @@ static int rockchip_pcie_ep_set_msi(struct pci_epc *e= pc, u8 fn, u8 vfn, { struct rockchip_pcie_ep *ep =3D epc_get_drvdata(epc); struct rockchip_pcie *rockchip =3D &ep->rockchip; - u16 flags; + u32 flags; =20 flags =3D rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); flags &=3D ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK; flags |=3D - ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | - PCI_MSI_FLAGS_64BIT; + (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | + (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET); flags &=3D ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP; rockchip_pcie_write(rockchip, flags, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -291,7 +291,7 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc= , u8 fn, u8 vfn) { struct rockchip_pcie_ep *ep =3D epc_get_drvdata(epc); struct rockchip_pcie *rockchip =3D &ep->rockchip; - u16 flags; + u32 flags; =20 flags =3D rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -352,7 +352,7 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchi= p_pcie_ep *ep, u8 fn, u8 interrupt_num) { struct rockchip_pcie *rockchip =3D &ep->rockchip; - u16 flags, mme, data, data_mask; + u32 flags, mme, data, data_mask; u8 msi_count; u64 pci_addr; u32 r; diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controlle= r/pcie-rockchip.h index bef6d7098a2f..501d859420b4 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -227,6 +227,7 @@ #define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4 #define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19) #define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90 +#define ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET 16 #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17 #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17) #define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20 --=20 2.25.1