From nobody Tue Dec 16 11:49:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 950ADC77B7A for ; Mon, 17 Apr 2023 18:04:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231167AbjDQSEM (ORCPT ); Mon, 17 Apr 2023 14:04:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231182AbjDQSEG (ORCPT ); Mon, 17 Apr 2023 14:04:06 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 143065269 for ; Mon, 17 Apr 2023 11:04:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1681754639; x=1713290639; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KoHza1vejrzAkyGsjA2yudMh/oMxUYOS4fEMrrvFgz8=; b=lWnfQRkjgkn/cxKHQStTXy5UiohWfe5I/gzcwWh9eWqiMdw3MsckHVV1 sxXg84y29Ym4be4Zj5DF8neTpGsYsDuzxii6WTjaCN5S6fdvZQXZAV1+o OEju2eLJ7GJU0vrBiflMWfIKkd4OaOCDBee2GInnec4Oq5/cgWXdElZF8 O9FGqiPGAGaS4JVljVwU/dXpm8sEeRR/uJlV1aHBJLJky8qChetJmAg15 tGheW+1KfFuU5WI348wn2B4QOHHc74g69lXVUb9Qg6Su+VbE1Wvb5U6SP C8UVuj/VR0CLXiX78AbCtdReF/L97hIHpjRM6KIrRE0Jw/k/bAVxSKRph A==; X-IronPort-AV: E=Sophos;i="5.99,204,1677567600"; d="scan'208";a="147469774" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Apr 2023 11:03:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 17 Apr 2023 11:03:50 -0700 Received: from DEN-LT-70577.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 17 Apr 2023 11:03:48 -0700 From: Daniel Machon To: CC: , , , , , , , Subject: [PATCH 4/7] phy: sparx5-serdes: power down all CMUs by default Date: Mon, 17 Apr 2023 20:03:32 +0200 Message-ID: <20230417180335.2787494-5-daniel.machon@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417180335.2787494-1-daniel.machon@microchip.com> References: <20230417180335.2787494-1-daniel.machon@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All CMUs are powered up initially. This uses needless power. This patch makes sure all CMUs are powered down by default. This involves configuring a number reference clock and power-down registers of the CMU. Individual CMUs are later powered up, when the serdes lanes are configured. Signed-off-by: Daniel Machon --- drivers/phy/microchip/sparx5_serdes.c | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/phy/microchip/sparx5_serdes.c b/drivers/phy/microchip/= sparx5_serdes.c index d8620e0fae7b..0e9db7b36b60 100644 --- a/drivers/phy/microchip/sparx5_serdes.c +++ b/drivers/phy/microchip/sparx5_serdes.c @@ -1078,6 +1078,54 @@ static int sparx5_serdes_cmu_enable(struct sparx5_se= rdes_private *priv) return err; } =20 +static void sparx5_serdes_cmu_power_off(struct sparx5_serdes_private *priv) +{ + void __iomem *cmu_inst, *cmu_cfg_inst; + int i; + + /* Power down each CMU */ + for (i =3D 0; i < SPX5_CMU_MAX; i++) { + cmu_inst =3D sdx5_inst_get(priv, TARGET_SD_CMU, i); + cmu_cfg_inst =3D sdx5_inst_get(priv, TARGET_SD_CMU_CFG, i); + + sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), + SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, cmu_cfg_inst, + SD_CMU_CFG_SD_CMU_CFG(0)); + + sdx5_inst_rmw(SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(0), + SD_CMU_CMU_05_CFG_REFCK_TERM_EN, cmu_inst, + SD_CMU_CMU_05(0)); + + sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(0), + SD_CMU_CMU_09_CFG_EN_TX_CK_DN, cmu_inst, + SD_CMU_CMU_09(0)); + + sdx5_inst_rmw(SD_CMU_CMU_06_CFG_VCO_PD_SET(1), + SD_CMU_CMU_06_CFG_VCO_PD, cmu_inst, + SD_CMU_CMU_06(0)); + + sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(0), + SD_CMU_CMU_09_CFG_EN_TX_CK_UP, cmu_inst, + SD_CMU_CMU_09(0)); + + sdx5_inst_rmw(SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(1), + SD_CMU_CMU_08_CFG_CK_TREE_PD, cmu_inst, + SD_CMU_CMU_08(0)); + + sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_REFCK_PD_SET(1) | + SD_CMU_CMU_0D_CFG_PD_DIV64_SET(1) | + SD_CMU_CMU_0D_CFG_PD_DIV66_SET(1), + SD_CMU_CMU_0D_CFG_REFCK_PD | + SD_CMU_CMU_0D_CFG_PD_DIV64 | + SD_CMU_CMU_0D_CFG_PD_DIV66, cmu_inst, + SD_CMU_CMU_0D(0)); + + sdx5_inst_rmw(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(1), + SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, cmu_inst, + SD_CMU_CMU_06(0)); + } +} + static void sparx5_sd25g28_reset(void __iomem *regs[], struct sparx5_sd25g28_params *params, u32 sd_index) @@ -2521,6 +2569,9 @@ static int sparx5_serdes_probe(struct platform_device= *pdev) return err; } =20 + /* Power down all CMUs by default */ + sparx5_serdes_cmu_power_off(priv); + provider =3D devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate= ); =20 return PTR_ERR_OR_ZERO(provider); --=20 2.34.1