From nobody Thu Dec 18 07:58:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49B03C77B70 for ; Mon, 17 Apr 2023 09:28:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231168AbjDQJ2M (ORCPT ); Mon, 17 Apr 2023 05:28:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230414AbjDQJ1l (ORCPT ); Mon, 17 Apr 2023 05:27:41 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05AD75257; Mon, 17 Apr 2023 02:27:23 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id q23so52891665ejz.3; Mon, 17 Apr 2023 02:27:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681723641; x=1684315641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/D5e4r9jqiqt8lpQNji9WmConDh7wMZue+/g6ZwTrfA=; b=Gs+RW1XEAfl4scZ7St7I74xz+ViAN6f/8m+7qArUcQmNcftDL5/wKQiUQAfkEhhIc8 pyO2baIpXqYjLB9mO1ZmMzHcBUHA2oShUBeN9Trsn6skWY2KaE7c6OO+YTqtLrxCKEPc pWMhbk3OJdrBZH5UoRQwUuWY48g/Py2qh9Ir13VRqMuyss5kokx+tahicL34qdn8ZZWd REdezPMoDej47W6OCmMihITHlf1kiG/sZGu1ZzZTaO3MDzj4gdd5SJfXTJQa+OFcVF66 6sZMju06Jtskz/kWCxYb6vNDLmZSZFZ0mNyWfE0UrkkP9s0oY2YaCuTLQlF4VKb+ugaV x1YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681723641; x=1684315641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/D5e4r9jqiqt8lpQNji9WmConDh7wMZue+/g6ZwTrfA=; b=aEq1dJMHkQ0KH73mUVa5bcVavCWLxhc0Sbxfva6YSzOab/VZz3Nwk5ZaTdhwWyOYO5 6++PFpNBl0SmdJd4bn62IpUxNFVik4/9VcfS0cPxHU+hcGgjTOZBo20fTvIF60ngWObC J81nQ+8eoKIEHBEa5mGdYJhDCqO3chXkfy8fqP/JWrWAhCTFHfoJx0KXhSJlukht4W8w f5h8DAuLNs0KNxaWWHXh5uM9PMqh8BD7GglVup69jAeej7Bp5HiAuu6YZdx/H0nNgVLE 5Xze94R814c7pBoE+Eb2Rl0ptzdT8Ma+e+0LDkkEZ8/CkkJh+AQRNj7fSpmPV9N071Hs yPTQ== X-Gm-Message-State: AAQBX9e4r2sRWbN6Wdk1AtSpr5V+gIiA16RU6zMd0AggVV4tQhNPswq3 Tpic+GdTIaBJn38EPEcs4RUbavy/r34xyQ== X-Google-Smtp-Source: AKy350YQgprMfiR92H5F8IHg2YqLOpEwEiQLUo+wQDkLdLoLuXj5xFegJHrfsHQKMRUvbDXQqTDr2A== X-Received: by 2002:a17:907:2a8b:b0:94a:5c6d:3207 with SMTP id fl11-20020a1709072a8b00b0094a5c6d3207mr6250677ejc.44.1681723641379; Mon, 17 Apr 2023 02:27:21 -0700 (PDT) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id p20-20020a170906615400b0094aa087578csm6398596ejl.171.2023.04.17.02.27.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 02:27:21 -0700 (PDT) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, Rick Wertenbroek , stable@vger.kernel.org, Damien Le Moal , Shawn Lin , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Heiko Stuebner , Caleb Connolly , Johan Jonker , Brian Norris , Corentin Labbe , Arnaud Ferraris , Sascha Hauer , Judy Hsiao , Hugh Cole-Baker , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/11] PCI: rockchip: Use u32 variable to access 32-bit registers Date: Mon, 17 Apr 2023 11:26:27 +0200 Message-Id: <20230417092631.347976-10-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230417092631.347976-1-rick.wertenbroek@gmail.com> References: <20230417092631.347976-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously u16 variables were used to access 32-bit registers, this resulted in not all of the data being read from the registers. Also the left shift of more than 16-bits would result in moving data out of the variable. Use u32 variables to access 32-bit registers Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe contro= ller") Cc: stable@vger.kernel.org Signed-off-by: Rick Wertenbroek Tested-by: Damien Le Moal Reviewed-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 10 +++++----- drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/contro= ller/pcie-rockchip-ep.c index 771f1bb93251..63fbb379638b 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -271,15 +271,15 @@ static int rockchip_pcie_ep_set_msi(struct pci_epc *e= pc, u8 fn, u8 vfn, { struct rockchip_pcie_ep *ep =3D epc_get_drvdata(epc); struct rockchip_pcie *rockchip =3D &ep->rockchip; - u16 flags; + u32 flags; =20 flags =3D rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); flags &=3D ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK; flags |=3D - ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | - PCI_MSI_FLAGS_64BIT; + (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | + (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET); flags &=3D ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP; rockchip_pcie_write(rockchip, flags, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -291,7 +291,7 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc= , u8 fn, u8 vfn) { struct rockchip_pcie_ep *ep =3D epc_get_drvdata(epc); struct rockchip_pcie *rockchip =3D &ep->rockchip; - u16 flags; + u32 flags; =20 flags =3D rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -352,7 +352,7 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchi= p_pcie_ep *ep, u8 fn, u8 interrupt_num) { struct rockchip_pcie *rockchip =3D &ep->rockchip; - u16 flags, mme, data, data_mask; + u32 flags, mme, data, data_mask; u8 msi_count; u64 pci_addr; u32 r; diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controlle= r/pcie-rockchip.h index bef6d7098a2f..501d859420b4 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -227,6 +227,7 @@ #define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4 #define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19) #define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90 +#define ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET 16 #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17 #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17) #define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20 --=20 2.25.1