From nobody Thu Dec 18 07:52:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D624C77B70 for ; Mon, 17 Apr 2023 07:56:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231154AbjDQH4J (ORCPT ); Mon, 17 Apr 2023 03:56:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230479AbjDQHz6 (ORCPT ); Mon, 17 Apr 2023 03:55:58 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 052FE2D53 for ; Mon, 17 Apr 2023 00:55:56 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4ec816c9b62so1187411e87.2 for ; Mon, 17 Apr 2023 00:55:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681718154; x=1684310154; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=o2kEZXqS3DdorsV7KBvalbCQQT9rGiidMVD8f+P+zW8=; b=cszasHJqTYYYiVgMtunipV+yzyUhFzSLNhUSkwJDjzdL7jFJrC3sW5CWMmi297UZuk icxBUMV5s1ZlZ3lqmVzkwG02nMxJ6IXkEO26lhcMrSMSIQTM71BrUKYMkURHWrY6ZnKI bAVlqFHdMatGCfWMnFwelhVbkjVURlAIXTqiWVJhGu8myBWN+i9tHfHpmFR0NSKQGGud rkycl4wBZ3xdjEtnSM+p7sCoqwxTUDCrsMvfS03lNPgWMM9FCJlAe6K70IrzW+VLH3DA Xj6hQQfit2+FZiMRguB3LIuZ9asqaQCfhECdLQI7rljKFlEP08FJMzEBr2y1RJOH1FNS HyiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681718154; x=1684310154; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o2kEZXqS3DdorsV7KBvalbCQQT9rGiidMVD8f+P+zW8=; b=lqtWnQ/A16JjT3qFBMZYYhHoPeJV9pgSmB1eDdczF1+GGLMnPAV7YP7A9g8wo+nTeJ s3BrnwzQhx0ALaYhp5kQd1ZTt69YNqbmHwspRU1E4rnuy1168+U/hE3VHTvzgLPSXZRe 4Dneg5swpCOqCONvWDpqpoAjn3pTktoWlVy9L5rGeOSMA4ZwnD56nwumT5aO6VaOEWfD RdozQKiJfbPPDtoFTXxwnnV7cFEDB0/7dZgqLPvq0M8mGCUtyDI7MQcfqW9brS4ooFs0 Sf/1SnGZKShLNtlE/0UU+B6d4rnN0mAfqie1Wb5JfAUUzUD7YYeot77O23W9eliiaBXs sRVw== X-Gm-Message-State: AAQBX9drLPa7JUM4tLwydtcIk/kykFDJSc2X6SrgW0MDPoyrqOIyDlCo hOCYVGqlmuJ4uDoupIaEq56qoQ== X-Google-Smtp-Source: AKy350bPHIoevthvL1Vu2On/x5qhfIXMiZgEySgZRAofY0B4hePo2ONJGYQf+Vn7/2yaEFBJjWs1Yw== X-Received: by 2002:a19:c502:0:b0:4ec:8087:88bb with SMTP id w2-20020a19c502000000b004ec808788bbmr1805886lfe.3.1681718154207; Mon, 17 Apr 2023 00:55:54 -0700 (PDT) Received: from [192.168.1.2] (c-05d8225c.014-348-6c756e10.bbcust.telenor.se. [92.34.216.5]) by smtp.gmail.com with ESMTPSA id p2-20020a19f002000000b004eb274b3a43sm1952547lfc.134.2023.04.17.00.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 00:55:53 -0700 (PDT) From: Linus Walleij Date: Mon, 17 Apr 2023 09:55:46 +0200 Subject: [PATCH 1/7] dt-bindings: dma: dma40: Prefer to pass sram through phandle MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230417-ux500-dma40-cleanup-v1-1-b26324956e47@linaro.org> References: <20230417-ux500-dma40-cleanup-v1-0-b26324956e47@linaro.org> In-Reply-To: <20230417-ux500-dma40-cleanup-v1-0-b26324956e47@linaro.org> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Linus Walleij X-Mailer: b4 0.12.2 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Extend the DMA40 bindings so that we can pass two SRAM segments as phandles instead of directly referring to the memory address in the second reg cell. This enables more granular control over the SRAM, and adds the optiona LCLA SRAM segment as well. Deprecate the old way of passing LCPA as a second reg cell, make sram compulsory. Signed-off-by: Linus Walleij --- .../devicetree/bindings/dma/stericsson,dma40.yaml | 35 +++++++++++++++++-= ---- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml b/= Documentation/devicetree/bindings/dma/stericsson,dma40.yaml index 64845347f44d..4fe0df937171 100644 --- a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml +++ b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml @@ -112,14 +112,23 @@ properties: - const: stericsson,dma40 =20 reg: - items: - - description: DMA40 memory base - - description: LCPA memory base + oneOf: + - items: + - description: DMA40 memory base + - items: + - description: DMA40 memory base + - description: LCPA memory base, deprecated, use eSRAM pool inst= ead + deprecated: true + =20 reg-names: - items: - - const: base - - const: lcpa + oneOf: + - items: + - const: base + - items: + - const: base + - const: lcpa + deprecated: true =20 interrupts: maxItems: 1 @@ -127,6 +136,14 @@ properties: clocks: maxItems: 1 =20 + sram: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + items: + maxItems: 2 + description: + List of phandles for the SRAM used by the DMA40 block, the first + phandle is the LCPA memory, the second is the LCLA memory. + memcpy-channels: $ref: /schemas/types.yaml#/definitions/uint32-array description: Array of u32 elements indicating which channels on the DMA @@ -138,6 +155,7 @@ required: - reg - interrupts - clocks + - sram - memcpy-channels =20 additionalProperties: false @@ -149,8 +167,9 @@ examples: #include dma-controller@801c0000 { compatible =3D "stericsson,db8500-dma40", "stericsson,dma40"; - reg =3D <0x801c0000 0x1000>, <0x40010000 0x800>; - reg-names =3D "base", "lcpa"; + reg =3D <0x801c0000 0x1000>; + reg-names =3D "base"; + sram =3D <&lcpa>, <&lcla>; interrupts =3D ; #dma-cells =3D <3>; memcpy-channels =3D <56 57 58 59 60>; --=20 2.39.2