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[83.9.30.99]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b004ec8a3d4200sm2053439lfq.293.2023.04.17.08.30.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 08:30:24 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Apr 2023 17:30:15 +0200 Subject: [PATCH 1/5] dt-bindings: display/msm: Add reg bus interconnect MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230417-topic-dpu_regbus-v1-1-06fbdc1643c0@linaro.org> References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681745422; l=1021; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=DgEhAwck/2UMFZpU98hoIh71vdQR9UmmeTw0XAyM3ys=; b=ciJNKHjiF7ITdMqgyQfJ5T8aGhSzJ7QpX1an0grzifZiCGiobk7sJ7VxHrZq7Ks1lDIevGYZ2Ppn gZhM6RO4AVtKPj9aTKdLen85YbNGGGyEr8b2giju+qcxUh69exFG X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. Describe it in bindings to allow for use in device trees. Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/mdss-common.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml= b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index ccd7d6417523..9eb5b6d3e0b9 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -72,6 +72,7 @@ properties: items: - const: mdp0-mem - const: mdp1-mem + - const: cpu-cfg =20 resets: items: --=20 2.40.0 From nobody Wed Dec 17 21:11:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 746F2C77B70 for ; Mon, 17 Apr 2023 15:31:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230254AbjDQPbe (ORCPT ); Mon, 17 Apr 2023 11:31:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230244AbjDQPbU (ORCPT ); Mon, 17 Apr 2023 11:31:20 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C95EEC177 for ; Mon, 17 Apr 2023 08:30:42 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-4ec816d64afso7066300e87.1 for ; Mon, 17 Apr 2023 08:30:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681745426; x=1684337426; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TusSYFhXpBTw3hD+Ig+2V6T5nJHWfXxfYQbiZRqJGNM=; b=dHm8aCvlXVcrP0iqD99p7M4Y/pOudpG+4rlOXksjIISbeEgITHmNiCyOWnztmGmBbL 9U0qtBuRVP3WmgtaCfn6QzqRQ2MAoY7iMOL4fpLO2d3o//gorp4SvmTxRqmX5b7yrdAK BEqM0uLWK6AAeOimsL1ObgL9hGdSsl8wCnD9kQ3snz9L2g1mlvFSgccT2OaGZIdHjfph 1XGDcfvkeJesdJxiCEtsImj8xNS4qsEI/vHoZmD0F9NJyNYkD/ixp4QTXUg7YA/naxBk qSH/Xiyk7kCiTWqgdbFXO9IXfn6pP8jkKCllavZHIvd0XvVZUDUG8sGyxMAYp2XdkilT 9tMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681745426; x=1684337426; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TusSYFhXpBTw3hD+Ig+2V6T5nJHWfXxfYQbiZRqJGNM=; b=aOQGpim44/ac06CZa/iwH2S2uNzW3GQ8MSzwLOtqduGFz0D9PtuEnuu0khi5aiqw+Z oEgeLew+yVUd1pa8XVn10B41J+mGmZ5FGozC5zsO7KF1+KSmCtCZzTZTmGOe0cURmbWL kIMio3TfoqjXd7s0fNCLfo6eaTruTOSFnrLAcQx0FxGkHfuXhK49gd6nUHXS38wYrDhT /Vzw1Hy0BZF8SLkzJs+iV3I3rJQ0YokUOtKWfctgd/pq7xQPAEgvBwN3D/TBoc5G6ACP 224u42WXj9pq35mCuGcbIY2dVYUeopVls237qCJ7EFAoNLXBqh9e7yIC/vygP6/yQ+yx fhFA== X-Gm-Message-State: AAQBX9ez1cC+c1TBzVWHaCxs9Ai4i7g1u0e7M6iG7a3msd4+qsEyVMCw Bo8FMRu0L+dJgW1Mhh6+dQet5RriLkm49jFcrho= X-Google-Smtp-Source: AKy350agehUton9XiPOAB4GqX1C2HbJ/wGsW22oIBdTT8/x4OXa6voDLfKXDnQ2Uv7CF+tDhvqbCzg== X-Received: by 2002:ac2:532c:0:b0:4eb:e8e:4139 with SMTP id f12-20020ac2532c000000b004eb0e8e4139mr2462637lfh.2.1681745426517; Mon, 17 Apr 2023 08:30:26 -0700 (PDT) Received: from [192.168.1.101] (abyk99.neoplus.adsl.tpnet.pl. [83.9.30.99]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b004ec8a3d4200sm2053439lfq.293.2023.04.17.08.30.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 08:30:26 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Apr 2023 17:30:16 +0200 Subject: [PATCH 2/5] drm/msm/dpu1: Rename path references to mdp_path MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230417-topic-dpu_regbus-v1-2-06fbdc1643c0@linaro.org> References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681745422; l=3187; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=RHVX4b0dy7ygKXk/64XZDOzn26jUEVt2/m6N5KVO6Vs=; b=qhl8VwYNu7H7amoau38AAJki+EoSvXRe0p3hYZz1l9uP0M+SPAdPsESbHnLiWGF1IWWRLpLbCih8 jUqjgwyVDIwSPBiS81m0CFn3q3LaeRVXuNnjeTnu1QNfB77xNcJ5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The DPU1 driver needs to handle all MDPn<->DDR paths, as well as CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are calculated, but the latter one has static predefines spanning all SoCs. In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename the path-related struct members to include "mdp_". Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++-- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/dr= m/msm/disp/dpu1/dpu_core_perf.c index 1d9d83d7b99e..349c6cb3301d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -230,18 +230,18 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_= kms *kms, =20 DRM_DEBUG_ATOMIC("crtc=3D%d bw=3D%llu paths:%d\n", tmp_crtc->base.id, - dpu_cstate->new_perf.bw_ctl, kms->num_paths); + dpu_cstate->new_perf.bw_ctl, kms->num_mdp_paths); } } =20 - if (!kms->num_paths) + if (!kms->num_mdp_paths) return 0; =20 avg_bw =3D perf.bw_ctl; - do_div(avg_bw, (kms->num_paths * 1000)); /*Bps_to_icc*/ + do_div(avg_bw, (kms->num_mdp_paths * 1000)); /*Bps_to_icc*/ =20 - for (i =3D 0; i < kms->num_paths; i++) - icc_set_bw(kms->path[i], avg_bw, perf.max_per_pipe_ib); + for (i =3D 0; i < kms->num_mdp_paths; i++) + icc_set_bw(kms->mdp_path[i], avg_bw, perf.max_per_pipe_ib); =20 return ret; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 0e7a68714e9e..dd6c1c40ab9e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -397,12 +397,12 @@ static int dpu_kms_parse_data_bus_icc_path(struct dpu= _kms *dpu_kms) if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); =20 - dpu_kms->path[0] =3D path0; - dpu_kms->num_paths =3D 1; + dpu_kms->mdp_path[0] =3D path0; + dpu_kms->num_mdp_paths =3D 1; =20 if (!IS_ERR_OR_NULL(path1)) { - dpu_kms->path[1] =3D path1; - dpu_kms->num_paths++; + dpu_kms->mdp_path[1] =3D path1; + dpu_kms->num_mdp_paths++; } return 0; } @@ -1238,8 +1238,8 @@ static int __maybe_unused dpu_runtime_suspend(struct = device *dev) dev_pm_opp_set_rate(dev, 0); clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); =20 - for (i =3D 0; i < dpu_kms->num_paths; i++) - icc_set_bw(dpu_kms->path[i], 0, 0); + for (i =3D 0; i < dpu_kms->num_mdp_paths; i++) + icc_set_bw(dpu_kms->mdp_path[i], 0, 0); =20 return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.h index aca39a4689f4..d5d9bec90705 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -109,8 +109,8 @@ struct dpu_kms { * when disabled. */ atomic_t bandwidth_ref; - struct icc_path *path[2]; - u32 num_paths; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; }; =20 struct vsync_info { --=20 2.40.0 From nobody Wed Dec 17 21:11:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0181C77B76 for ; Mon, 17 Apr 2023 15:31:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229956AbjDQPbq (ORCPT ); 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[83.9.30.99]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b004ec8a3d4200sm2053439lfq.293.2023.04.17.08.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 08:30:27 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Apr 2023 17:30:17 +0200 Subject: [PATCH 3/5] drm/msm/mdss: Rename path references to mdp_path MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230417-topic-dpu_regbus-v1-3-06fbdc1643c0@linaro.org> References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681745422; l=2175; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=mFT0UyX9LhxCNCpprLZW/XLO+LLNqKMZSGZE8MZeFUU=; b=BXHtHcUcP4g/hixvZ0bGJVRvqCP7askf6+3q9wseZvQ/7VfvWeLIM9JhT3BU/O5D9uFsmsKTreg+ diV6OtW0D5MqNkqhqHE4VLhrMAs+6iejgdtaEbsRGpVZvrINpjs1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The DPU1 driver needs to handle all MDPn<->DDR paths, as well as CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are calculated, but the latter one has static predefines spanning all SoCs. In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename the path-related struct members to include "mdp_". Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e8c93731aaa1..9e2ce7f22677 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -48,8 +48,8 @@ struct msm_mdss { struct irq_domain *domain; } irq_controller; const struct msm_mdss_data *mdss_data; - struct icc_path *path[2]; - u32 num_paths; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; }; =20 static int msm_mdss_parse_data_bus_icc_path(struct device *dev, @@ -62,13 +62,13 @@ static int msm_mdss_parse_data_bus_icc_path(struct devi= ce *dev, if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); =20 - msm_mdss->path[0] =3D path0; - msm_mdss->num_paths =3D 1; + msm_mdss->mdp_path[0] =3D path0; + msm_mdss->num_mdp_paths =3D 1; =20 path1 =3D of_icc_get(dev, "mdp1-mem"); if (!IS_ERR_OR_NULL(path1)) { - msm_mdss->path[1] =3D path1; - msm_mdss->num_paths++; + msm_mdss->mdp_path[1] =3D path1; + msm_mdss->num_mdp_paths++; } =20 return 0; @@ -79,16 +79,16 @@ static void msm_mdss_put_icc_path(void *data) struct msm_mdss *msm_mdss =3D data; int i; =20 - for (i =3D 0; i < msm_mdss->num_paths; i++) - icc_put(msm_mdss->path[i]); + for (i =3D 0; i < msm_mdss->num_mdp_paths; i++) + icc_put(msm_mdss->mdp_path[i]); } =20 static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned lo= ng bw) { int i; =20 - for (i =3D 0; i < msm_mdss->num_paths; i++) - icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); + for (i =3D 0; i < msm_mdss->num_mdp_paths; i++) + icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); } =20 static void msm_mdss_irq(struct irq_desc *desc) --=20 2.40.0 From nobody Wed Dec 17 21:11:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CA6FC77B70 for ; Mon, 17 Apr 2023 15:31:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231387AbjDQPbu (ORCPT ); Mon, 17 Apr 2023 11:31:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231209AbjDQPbl (ORCPT ); Mon, 17 Apr 2023 11:31:41 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 243DFBBA3 for ; Mon, 17 Apr 2023 08:31:06 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2a8bb726210so11951561fa.1 for ; Mon, 17 Apr 2023 08:31:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681745429; x=1684337429; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PbVhusCEghNKEPZ8TLDEdqw82MnqWQVPyy1y462DY9k=; b=vG/uhlDHyTadETatt819cKu9odf4EjYBgf4EYXzYjIlvJmYFp7NLxrg5Pd9yQ4par0 tbYp28bwgmFxSETBGY+Rrp6eA819DR7FLdIRZ1nSLwmq+P6m3crSEetKqQxqsniWVowW 9zQ4EcoUSdtTYX9UgIl/9Cy8s2z/N4BocL5dP3R1rFtXNEkf9Xg6h8B72azDvJakrG+H sAzoupFMyUEdgG+P1l0Qypd35ABtdb9LG5rIRO4bY60GBF8LrP7axjSH2jV5YUPsVd3W IR8mc87yxRPLqGUEXs/r9RTa9Ycp43SKK0YAvqj599/dUo3qnXfxbEuDkPFlHGgHInFu nuag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681745429; x=1684337429; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PbVhusCEghNKEPZ8TLDEdqw82MnqWQVPyy1y462DY9k=; b=CWyaGk6rpqo1Qqa4fJdu1CKHLIFrAAVMqQ3vrDHoCwc+euLw9//1MeyMlTHYMJNjHV H4xZWhD0Woxkog2U/l/M82NubT3QP+dhiUVd5fK/Pfgcx7RJWqz1uCT8VRObjS3M1XfA MSkZu2JCJC2/YPmi7iOsM/bOkM6m0hpx7Sl1gBl0WdzgKXfcdUTfI92yuTYBQnxr6vu0 BrPrpnx20ltV67+kBY7bCWbO+pzpenb8X0p52UxHUyKw667QIBMQYmGwszXJyq5ZCiUp 6iFnGd3ilp4lJjuhMbEw4uMQh1iTpbvgkf7C9MLw93zEvjq8CX6PVYGc3u00Y1V/tvpQ DIow== X-Gm-Message-State: AAQBX9eHwSTNzBBZFgNcJDIzVXLCHLbHCu5ZZYt7uMLxXCoJL5kTV0d3 GzfQwBedbkCbElIn8BGzmtxZ437fIN7wKP7FAG8= X-Google-Smtp-Source: AKy350ZFca4MHSPEHzAuUtnlhK8+04AZOucpZ19yBZbQQlFSTFKEdxqPL/D9EBLV4ijZa2GEREui9g== X-Received: by 2002:ac2:47e1:0:b0:4e9:ce2c:26b0 with SMTP id b1-20020ac247e1000000b004e9ce2c26b0mr2186862lfp.14.1681745429463; Mon, 17 Apr 2023 08:30:29 -0700 (PDT) Received: from [192.168.1.101] (abyk99.neoplus.adsl.tpnet.pl. [83.9.30.99]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b004ec8a3d4200sm2053439lfq.293.2023.04.17.08.30.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 08:30:29 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Apr 2023 17:30:18 +0200 Subject: [PATCH 4/5] drm/msm/mdss: Handle the reg bus ICC path MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230417-topic-dpu_regbus-v1-4-06fbdc1643c0@linaro.org> References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681745422; l=3137; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wX+gJPCe8UmLoFyI2GJLXSE1t0Mv12xmqDSsK2E8jZI=; b=5xiKkr66PFQP6ZSqLKRRPFd+S077x81GWeppbqJQlTkHd+GVqAn2hoMw2omK55rgB2aCud7qPoYm 7jn8UljSDUu65rLWRgQrdQbpTqj1ZycewVweNG7g9gkRH7l6DiQU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. On the MDSS side, we only have to ensure that it's on at what Qualcomm downstream calls "77 MHz", a.k.a 76.8 Mbps and turn it off at suspend. To achieve that, make msm_mdss_icc_request_bw() accept a boolean to indicate whether we want the busses to be on or off, as this function's only use is to vote for minimum or no bandwidth at all. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 9e2ce7f22677..4d126d20d661 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -50,6 +50,7 @@ struct msm_mdss { const struct msm_mdss_data *mdss_data; struct icc_path *mdp_path[2]; u32 num_mdp_paths; + struct icc_path *reg_bus_path; }; =20 static int msm_mdss_parse_data_bus_icc_path(struct device *dev, @@ -57,6 +58,7 @@ static int msm_mdss_parse_data_bus_icc_path(struct device= *dev, { struct icc_path *path0; struct icc_path *path1; + struct icc_path *reg_bus_path; =20 path0 =3D of_icc_get(dev, "mdp0-mem"); if (IS_ERR_OR_NULL(path0)) @@ -71,6 +73,10 @@ static int msm_mdss_parse_data_bus_icc_path(struct devic= e *dev, msm_mdss->num_mdp_paths++; } =20 + reg_bus_path =3D of_icc_get(dev, "cpu-cfg"); + if (!IS_ERR_OR_NULL(reg_bus_path)) + msm_mdss->reg_bus_path =3D reg_bus_path; + return 0; } =20 @@ -83,12 +89,15 @@ static void msm_mdss_put_icc_path(void *data) icc_put(msm_mdss->mdp_path[i]); } =20 -static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned lo= ng bw) +static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, bool enable) { int i; =20 for (i =3D 0; i < msm_mdss->num_mdp_paths; i++) - icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); + icc_set_bw(msm_mdss->mdp_path[i], 0, enable ? Bps_to_icc(MIN_IB_BW) : 0); + + if (msm_mdss->reg_bus_path) + icc_set_bw(msm_mdss->reg_bus_path, 0, enable ? 76800 : 0); } =20 static void msm_mdss_irq(struct irq_desc *desc) @@ -241,7 +250,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) * the interconnect is enabled (non-zero bandwidth). Let's make sure * that the interconnects are at least at a minimum amount. */ - msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); + msm_mdss_icc_request_bw(msm_mdss, true); =20 ret =3D clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { @@ -289,7 +298,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) static int msm_mdss_disable(struct msm_mdss *msm_mdss) { clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); - msm_mdss_icc_request_bw(msm_mdss, 0); + msm_mdss_icc_request_bw(msm_mdss, false); =20 return 0; } --=20 2.40.0 From nobody Wed Dec 17 21:11:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6563FC77B76 for ; Mon, 17 Apr 2023 15:31:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231273AbjDQPbx (ORCPT ); Mon, 17 Apr 2023 11:31:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231217AbjDQPbl (ORCPT ); Mon, 17 Apr 2023 11:31:41 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9268BBB3 for ; Mon, 17 Apr 2023 08:31:07 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2a8b3ecf59fso14036561fa.0 for ; Mon, 17 Apr 2023 08:31:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681745431; x=1684337431; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lcxH0mNsQVfDuHuH7DyMK38UqQVq7f3xMxzQMn5dBWA=; b=gnQ5ymplkK5b7sYMnqpxw4yJ9NphJIng4sG9Cn67lskFdtnpqzs70ltj+eEg+tkttO Sq/k3dDx/KHaH3Uz2+J/sthqAkS3CxzKqcj+t2dXHMlHP6pR5rCR7gxLoZMTKQcwXOAw mL/RZ5L7XRCO4GyUsypitOsPT0UYzjrR0Z9IPqteiW5+hUNC3Hx8Vr5vXdMYeWmkfVzX pHUYcGKlnYITZayEa4ro9WzgobH2AHarbLJdVx8/Qiqu7m8Y5NeykBIgJqmSZQ3W+gM5 bj6YrNrWyIoPZtrykHBbRDTWAGFe7VedGNbSjV83OlV+XRq9VIQdG+Ojk+xdOyn9XgXG gQwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681745431; x=1684337431; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lcxH0mNsQVfDuHuH7DyMK38UqQVq7f3xMxzQMn5dBWA=; b=bY55zFdgUIye7CxViFFoDEfDqAi9Y4Ipdt8iKynhjH+nZlt0i8f1Ts0wk6cbDeqeZi 38cmeMZTHwF2GfXCciIcWyNXocXD0VWqi4SyjcFsH4sCy+5AGO6Am+tqYTSyVszatybG d/Tk1NPMPdt4qPOFL2tkKdIxhoUn0DEbZDKK0xBeneYx+vU1V4+bapyXhlvT9wEXYLwQ V5pKNyoy5NrC3ycHqXgpJhVLAJz9Gi6ch10q6BqcMsvLGadNQnLmHwNjnTSFQm5qMdXE YbuVmf9Y2iTNv2UlYsMRUfvexrOBTu6iqGIqKg8a/6DzoSBqUuHsKatu+zsZcnf9GcBK wJQQ== X-Gm-Message-State: AAQBX9f1mkHDX64EVROP1NSuD10F+UHPwhxcDfkl3TeY3x7vzVFQP3m4 pzGSFsFFlIxWmPzuS8ie8S13s9OxoKL+g02zf90= X-Google-Smtp-Source: AKy350YAQdB34K4Wt5YmouiLx0ktgowQsOMlPWso9pM6x6NdIXxq7ADxK2Zm3lKzIlmKf7RxMs66wA== X-Received: by 2002:a19:f806:0:b0:4e9:c627:195d with SMTP id a6-20020a19f806000000b004e9c627195dmr1879931lff.57.1681745430903; Mon, 17 Apr 2023 08:30:30 -0700 (PDT) Received: from [192.168.1.101] (abyk99.neoplus.adsl.tpnet.pl. [83.9.30.99]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b004ec8a3d4200sm2053439lfq.293.2023.04.17.08.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 08:30:30 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Apr 2023 17:30:19 +0200 Subject: [PATCH 5/5] drm/msm/dpu1: Handle the reg bus ICC path MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230417-topic-dpu_regbus-v1-5-06fbdc1643c0@linaro.org> References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> In-Reply-To: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681745422; l=3473; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=yaaDRHHygxKzQdks1Y/6TtLq+nFnkHcN9/nfzu3GSEU=; b=VTNZxxN5Kh+K53Ykp22wmxgC0rpDu78abg1GvWpdZHX0debI+H9cd8gXbR/JRvN94fKwoWyLNipa 5fEg7jJlAWe/w//ky+w/HA/5ewSdnYYRe+EWAGN92gxgmZdBrX72 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. On the DPU side, we need to keep the bus alive. The vendor driver kickstarts it to max (300Mbps) throughput on first commit, but in exchange for some battery life in rare DPU-enabled-panel-disabled usecases, we can request it at DPU init and gate it at suspend. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 22 ++++++++++++++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index dd6c1c40ab9e..d1f77faebbc0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -384,15 +384,17 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dp= u_kms) return 0; } =20 -static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) +static int dpu_kms_parse_icc_paths(struct dpu_kms *dpu_kms) { struct icc_path *path0; struct icc_path *path1; + struct icc_path *reg_bus_path; struct drm_device *dev =3D dpu_kms->dev; struct device *dpu_dev =3D dev->dev; =20 path0 =3D msm_icc_get(dpu_dev, "mdp0-mem"); path1 =3D msm_icc_get(dpu_dev, "mdp1-mem"); + reg_bus_path =3D msm_icc_get(dpu_dev, "cpu-cfg"); =20 if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); @@ -404,6 +406,10 @@ static int dpu_kms_parse_data_bus_icc_path(struct dpu_= kms *dpu_kms) dpu_kms->mdp_path[1] =3D path1; dpu_kms->num_mdp_paths++; } + + if (!IS_ERR_OR_NULL(reg_bus_path)) + dpu_kms->reg_bus_path =3D reg_bus_path; + return 0; } =20 @@ -1039,7 +1045,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) DPU_DEBUG("REG_DMA is not defined"); } =20 - dpu_kms_parse_data_bus_icc_path(dpu_kms); + dpu_kms_parse_icc_paths(dpu_kms); =20 rc =3D pm_runtime_resume_and_get(&dpu_kms->pdev->dev); if (rc < 0) @@ -1241,6 +1247,9 @@ static int __maybe_unused dpu_runtime_suspend(struct = device *dev) for (i =3D 0; i < dpu_kms->num_mdp_paths; i++) icc_set_bw(dpu_kms->mdp_path[i], 0, 0); =20 + if (dpu_kms->reg_bus_path) + icc_set_bw(dpu_kms->reg_bus_path, 0, 0); + return 0; } =20 @@ -1261,6 +1270,15 @@ static int __maybe_unused dpu_runtime_resume(struct = device *dev) return rc; } =20 + /* + * The vendor driver supports setting 76.8 / 150 / 300 Mbps on this + * path, but it seems to go for the highest level when display output + * is enabled and zero otherwise. For simplicity, we can assume that + * DPU being enabled and running implies that. + */ + if (dpu_kms->reg_bus_path) + icc_set_bw(dpu_kms->reg_bus_path, 0, MBps_to_icc(300)); + dpu_vbif_init_memtypes(dpu_kms); =20 drm_for_each_encoder(encoder, ddev) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.h index d5d9bec90705..c332381d58c4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -111,6 +111,7 @@ struct dpu_kms { atomic_t bandwidth_ref; struct icc_path *mdp_path[2]; u32 num_mdp_paths; + struct icc_path *reg_bus_path; }; =20 struct vsync_info { --=20 2.40.0