From nobody Thu Dec 18 18:57:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1A5BC77B70 for ; Fri, 14 Apr 2023 08:15:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230133AbjDNIPs (ORCPT ); Fri, 14 Apr 2023 04:15:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229999AbjDNIPb (ORCPT ); Fri, 14 Apr 2023 04:15:31 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 322C2768D for ; Fri, 14 Apr 2023 01:15:27 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6ED894B3; Fri, 14 Apr 2023 01:16:11 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.19.162]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D02663F6C4; Fri, 14 Apr 2023 01:15:23 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: Radu Rendec , Alexandre Ghiti , Conor Dooley , Will Deacon , Florian Fainelli , Pierre Gondois , Sudeep Holla , Greg Kroah-Hartman , "Rafael J. Wysocki" , Palmer Dabbelt , Gavin Shan , Jeremy Linton Subject: [PATCH v4 1/4] cacheinfo: Check sib_leaf in cache_leaves_are_shared() Date: Fri, 14 Apr 2023 10:14:49 +0200 Message-Id: <20230414081453.244787-2-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414081453.244787-1-pierre.gondois@arm.com> References: <20230414081453.244787-1-pierre.gondois@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If there is no ACPI/DT information, it is assumed that L1 caches are private and L2 (and higher) caches are shared. A cache is 'shared' between two CPUs if it is accessible from these two CPUs. Each CPU owns a representation (i.e. has a dedicated cacheinfo struct) of the caches it has access to. cache_leaves_are_shared() tries to identify whether two representations are designating the same actual cache. In cache_leaves_are_shared(), if 'this_leaf' is a L2 cache (or higher) and 'sib_leaf' is a L1 cache, the caches are detected as shared as only this_leaf's cache level is checked. This is leads to setting sib_leaf as being shared with another CPU, which is incorrect as this is a L1 cache. Check 'sib_leaf->level'. Also update the comment as the function is called when populating 'shared_cpu_map'. Fixes: f16d1becf96f ("cacheinfo: Use cache identifiers to check if the cach= es are shared if available") Signed-off-by: Pierre Gondois Reviewed-by: Conor Dooley Tested-by: Florian Fainelli --- drivers/base/cacheinfo.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index f3903d002819..c5d2293ac2a6 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -38,11 +38,10 @@ static inline bool cache_leaves_are_shared(struct cache= info *this_leaf, { /* * For non DT/ACPI systems, assume unique level 1 caches, - * system-wide shared caches for all other levels. This will be used - * only if arch specific code has not populated shared_cpu_map + * system-wide shared caches for all other levels. */ if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI))) - return !(this_leaf->level =3D=3D 1); + return (this_leaf->level !=3D 1) && (sib_leaf->level !=3D 1); =20 if ((sib_leaf->attributes & CACHE_ID) && (this_leaf->attributes & CACHE_ID)) --=20 2.25.1 From nobody Thu Dec 18 18:57:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3FF8C77B70 for ; Fri, 14 Apr 2023 08:15:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230081AbjDNIPy (ORCPT ); Fri, 14 Apr 2023 04:15:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230084AbjDNIPm (ORCPT ); Fri, 14 Apr 2023 04:15:42 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 630B97D8A for ; Fri, 14 Apr 2023 01:15:31 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A745A2F4; Fri, 14 Apr 2023 01:16:15 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.19.162]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AFD8B3F6C4; Fri, 14 Apr 2023 01:15:28 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: Radu Rendec , Alexandre Ghiti , Conor Dooley , Will Deacon , Florian Fainelli , Pierre Gondois , Sudeep Holla , Greg Kroah-Hartman , "Rafael J. Wysocki" , Palmer Dabbelt , Gavin Shan Subject: [PATCH v4 2/4] cacheinfo: Check cache properties are present in DT Date: Fri, 14 Apr 2023 10:14:50 +0200 Message-Id: <20230414081453.244787-3-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414081453.244787-1-pierre.gondois@arm.com> References: <20230414081453.244787-1-pierre.gondois@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If a Device Tree (DT) is used, the presence of cache properties is assumed. Not finding any is not considered. For arm64 platforms, cache information can be fetched from the clidr_el1 register. Checking whether cache information is available in the DT allows to switch to using clidr_el1. init_of_cache_level() \-of_count_cache_leaves() will assume there a 2 cache leaves (L1 data/instruction caches), which can be different from clidr_el1 information. cache_setup_of_node() tries to read cache properties in the DT. If there are none, this is considered a success. Knowing no information was available would allow to switch to using clidr_el1. Fixes: de0df442ee49 ("cacheinfo: Check 'cache-unified' property to count ca= che leaves") Reported-by: Alexandre Ghiti Link: https://lore.kernel.org/all/20230404-hatred-swimmer-6fecdf33b57a@spud/ Signed-off-by: Pierre Gondois Reviewed-by: Conor Dooley Tested-by: Florian Fainelli --- drivers/base/cacheinfo.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index c5d2293ac2a6..ea8f416852bd 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -78,6 +78,9 @@ bool last_level_cache_is_shared(unsigned int cpu_x, unsig= ned int cpu_y) } =20 #ifdef CONFIG_OF + +static bool of_check_cache_nodes(struct device_node *np); + /* OF properties to query for a given cache type */ struct cache_type_info { const char *size_prop; @@ -205,6 +208,11 @@ static int cache_setup_of_node(unsigned int cpu) return -ENOENT; } =20 + if (!of_check_cache_nodes(np)) { + of_node_put(np); + return -ENOENT; + } + prev =3D np; =20 while (index < cache_leaves(cpu)) { @@ -229,6 +237,25 @@ static int cache_setup_of_node(unsigned int cpu) return 0; } =20 +static bool of_check_cache_nodes(struct device_node *np) +{ + struct device_node *next; + + if (of_property_present(np, "cache-size") || + of_property_present(np, "i-cache-size") || + of_property_present(np, "d-cache-size") || + of_property_present(np, "cache-unified")) + return true; + + next =3D of_find_next_cache_node(np); + if (next) { + of_node_put(next); + return true; + } + + return false; +} + static int of_count_cache_leaves(struct device_node *np) { unsigned int leaves =3D 0; @@ -260,6 +287,11 @@ int init_of_cache_level(unsigned int cpu) struct device_node *prev =3D NULL; unsigned int levels =3D 0, leaves, level; =20 + if (!of_check_cache_nodes(np)) { + of_node_put(np); + return -ENOENT; + } + leaves =3D of_count_cache_leaves(np); if (leaves > 0) levels =3D 1; --=20 2.25.1 From nobody Thu Dec 18 18:57:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89BE1C77B70 for ; Fri, 14 Apr 2023 08:15:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230149AbjDNIP5 (ORCPT ); Fri, 14 Apr 2023 04:15:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229866AbjDNIPm (ORCPT ); Fri, 14 Apr 2023 04:15:42 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0301B7EF3 for ; Fri, 14 Apr 2023 01:15:36 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 29C8B2F4; Fri, 14 Apr 2023 01:16:20 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.19.162]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 04FBF3F6C4; Fri, 14 Apr 2023 01:15:32 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: Radu Rendec , Alexandre Ghiti , Conor Dooley , Will Deacon , Florian Fainelli , Pierre Gondois , Sudeep Holla , Greg Kroah-Hartman , "Rafael J. Wysocki" , Palmer Dabbelt , Gavin Shan Subject: [PATCH v4 3/4] arch_topology: Remove early cacheinfo error message if -ENOENT Date: Fri, 14 Apr 2023 10:14:51 +0200 Message-Id: <20230414081453.244787-4-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414081453.244787-1-pierre.gondois@arm.com> References: <20230414081453.244787-1-pierre.gondois@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" fetch_cache_info() tries to get the number of cache leaves/levels for each CPU in order to pre-allocate memory for cacheinfo struct. Allocating this memory later triggers a: 'BUG: sleeping function called from invalid context' in PREEMPT_RT kernels. If there is no cache related information available in DT or ACPI, fetch_cache_info() fails and an error message is printed: 'Early cacheinfo failed, ret =3D ...' Not having cache information should be a valid configuration. Remove the error message if fetch_cache_info() fails with -ENOENT. Suggested-by: Conor Dooley Link: https://lore.kernel.org/all/20230404-hatred-swimmer-6fecdf33b57a@spud/ Signed-off-by: Pierre Gondois Reviewed-by: Conor Dooley Tested-by: Florian Fainelli --- drivers/base/arch_topology.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index b1c1dd38ab01..c4b6198d7461 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -843,10 +843,11 @@ void __init init_cpu_topology(void) =20 for_each_possible_cpu(cpu) { ret =3D fetch_cache_info(cpu); - if (ret) { + if (!ret) + continue; + else if (ret !=3D -ENOENT) pr_err("Early cacheinfo failed, ret =3D %d\n", ret); - break; - } + return; } } =20 --=20 2.25.1 From nobody Thu Dec 18 18:57:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 042BBC77B6E for ; Fri, 14 Apr 2023 08:16:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230058AbjDNIQB (ORCPT ); Fri, 14 Apr 2023 04:16:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230110AbjDNIPp (ORCPT ); Fri, 14 Apr 2023 04:15:45 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 39C0083F6 for ; Fri, 14 Apr 2023 01:15:40 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5F9B94B3; Fri, 14 Apr 2023 01:16:24 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.19.162]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 684ED3F6C4; Fri, 14 Apr 2023 01:15:37 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: Radu Rendec , Alexandre Ghiti , Conor Dooley , Will Deacon , Florian Fainelli , Pierre Gondois , Sudeep Holla , Greg Kroah-Hartman , "Rafael J. Wysocki" , Palmer Dabbelt , Gavin Shan Subject: [PATCH v4 4/4] cacheinfo: Add use_arch[|_cache]_info field/function Date: Fri, 14 Apr 2023 10:14:52 +0200 Message-Id: <20230414081453.244787-5-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414081453.244787-1-pierre.gondois@arm.com> References: <20230414081453.244787-1-pierre.gondois@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The cache information can be extracted from either a Device Tree (DT), the PPTT ACPI table, or arch registers (clidr_el1 for arm64). The clidr_el1 register is used only if DT/ACPI information is not available. It does not states how caches are shared among CPUs. Add a use_arch_cache_info field/function to identify when the DT/ACPI doesn't provide cache information. Use this information to assume L1 caches are privates and L2 and higher are shared among all CPUs. Signed-off-by: Pierre Gondois Tested-by: Florian Fainelli --- drivers/base/cacheinfo.c | 12 ++++++++++-- include/linux/cacheinfo.h | 6 ++++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index ea8f416852bd..8120ac1ddbe4 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -28,6 +28,9 @@ static DEFINE_PER_CPU(struct cpu_cacheinfo, ci_cpu_cachei= nfo); #define per_cpu_cacheinfo_idx(cpu, idx) \ (per_cpu_cacheinfo(cpu) + (idx)) =20 +/* Set if no cache information is found in DT/ACPI. */ +static bool use_arch_info; + struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu) { return ci_cacheinfo(cpu); @@ -40,7 +43,8 @@ static inline bool cache_leaves_are_shared(struct cachein= fo *this_leaf, * For non DT/ACPI systems, assume unique level 1 caches, * system-wide shared caches for all other levels. */ - if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI))) + if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI)) || + use_arch_info) return (this_leaf->level !=3D 1) && (sib_leaf->level !=3D 1); =20 if ((sib_leaf->attributes & CACHE_ID) && @@ -343,6 +347,10 @@ static int cache_setup_properties(unsigned int cpu) else if (!acpi_disabled) ret =3D cache_setup_acpi(cpu); =20 + // Assume there is no cache information available in DT/ACPI from now. + if (ret && use_arch_cache_info()) + use_arch_info =3D true; + return ret; } =20 @@ -361,7 +369,7 @@ static int cache_shared_cpu_map_setup(unsigned int cpu) * to update the shared cpu_map if the cache attributes were * populated early before all the cpus are brought online */ - if (!last_level_cache_is_valid(cpu)) { + if (!last_level_cache_is_valid(cpu) && !use_arch_info) { ret =3D cache_setup_properties(cpu); if (ret) return ret; diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 908e19d17f49..b91cc9991c7c 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -129,4 +129,10 @@ static inline int get_cpu_cacheinfo_id(int cpu, int le= vel) return -1; } =20 +#ifdef CONFIG_ARM64 +#define use_arch_cache_info() (true) +#else +#define use_arch_cache_info() (false) +#endif + #endif /* _LINUX_CACHEINFO_H */ --=20 2.25.1