From nobody Thu Dec 18 18:47:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFB53C77B79 for ; Fri, 14 Apr 2023 14:07:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230372AbjDNOHQ (ORCPT ); Fri, 14 Apr 2023 10:07:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230265AbjDNOHJ (ORCPT ); Fri, 14 Apr 2023 10:07:09 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 686A3A5C1 for ; Fri, 14 Apr 2023 07:06:42 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id i26so23879416lfc.6 for ; Fri, 14 Apr 2023 07:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681481184; x=1684073184; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=HANrBatD66XHrbynSUb+/d3zU2tkPBuvtN1APBMREqs=; b=vmS8y1HoE3osnmSlFtEzioX6TV5Um9jP0ExIdP3zFRLiSZW6+sRf5ERlXDRKWWEBx/ fTivZmIt9xt9gE01HBFaWbuMcAq158o4uWc4udD6AFn5gRS4dwlCQhKN4o4kISiFQGXL LqCuczJt6lpfI1bWxF/ub8BSg+qk8PI4FoJ2z+475a+y2LiBYM9ncWzV1juQmh44WhpO CJQvVbz6ZORpvmZhPvl88e2t6M3tSRGKeCdbRNKvuE8n2QK32R57LvkIJxrjqGCQSAbL BH590BAv8/RfVSA5wo595UDxqGt/cdrTFVNmwNCR0aqfmyXl3cTpOHGluf/rR9y8pDbh I+oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681481184; x=1684073184; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HANrBatD66XHrbynSUb+/d3zU2tkPBuvtN1APBMREqs=; b=A09IEu4EdUtaSoi2ZmP4v4yuZ4pYxKp/8oNpPhis7D3BJd7I+09k7myzhN26KV9Ju0 +MCrnFfJGJ51XYIttqHYHDmGx6izB8KxS0ILrtH1bbmILqOxvfeqllVfBd496ZyX/Zvy ZLAuwBf8vSDt3AwB7oBOp7XblO4zTjqPt1d3Ra4WH4hpfbgwaansTH4UwOMM4ISd90B8 Fmsq6ZZb49Qx74bx3zkG9a/qUXLYbY68upL7NAWIo7sk5koxrNUWL3jRQA/YpygkqQtc yPH9Yo6m8RX+2gvx2tgArgzTXLknEG/auXDMgVSbrhWAShPPsjyMhD0Em6AW5npnl+C2 /7Kw== X-Gm-Message-State: AAQBX9eN1haV30WQPX3WtHWhK/LKFMCGZ4rSJdk6TME/1iO89wF/zf+5 MAcES8XOXfk/SKzQBkoUu8aL7A== X-Google-Smtp-Source: AKy350ZXNx9gUpKotPMlL4TZIccFfIfntAQ6+DMyC3z1S7xiZNKxTlSI+yACE1Foc5Bc8CHs7KMgZg== X-Received: by 2002:a19:5208:0:b0:4e8:16e8:88b with SMTP id m8-20020a195208000000b004e816e8088bmr1761984lfb.29.1681481184186; Fri, 14 Apr 2023 07:06:24 -0700 (PDT) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id b10-20020ac25e8a000000b004d856fe5121sm808794lfq.194.2023.04.14.07.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 07:06:23 -0700 (PDT) From: Linus Walleij Date: Fri, 14 Apr 2023 16:06:18 +0200 Subject: [PATCH 2/6] pinctrl: pistachio: Convert to immutable irq_chip MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230414-immutable-irqchips-2-v1-2-6b59a5186b00@linaro.org> References: <20230414-immutable-irqchips-2-v1-0-6b59a5186b00@linaro.org> In-Reply-To: <20230414-immutable-irqchips-2-v1-0-6b59a5186b00@linaro.org> To: Marc Zyngier , Viresh Kumar , Shiraz Hashim , soc@kernel.org, Bjorn Andersson , Andy Gross , Konrad Dybcio Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Linus Walleij X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-pistachio.c | 35 +++++++++++++++++++++++++--------= -- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-= pistachio.c index 7ca4ecb6eb8d..53408344927a 100644 --- a/drivers/pinctrl/pinctrl-pistachio.c +++ b/drivers/pinctrl/pinctrl-pistachio.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include =20 @@ -93,10 +94,10 @@ struct pistachio_pin_group { struct pistachio_gpio_bank { struct pistachio_pinctrl *pctl; void __iomem *base; + int instance; unsigned int pin_base; unsigned int npins; struct gpio_chip gpio_chip; - struct irq_chip irq_chip; }; =20 struct pistachio_pinctrl { @@ -1228,12 +1229,14 @@ static void pistachio_gpio_irq_mask(struct irq_data= *data) struct pistachio_gpio_bank *bank =3D irqd_to_bank(data); =20 gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0); + gpiochip_disable_irq(&bank->gpio_chip, irqd_to_hwirq(data)); } =20 static void pistachio_gpio_irq_unmask(struct irq_data *data) { struct pistachio_gpio_bank *bank =3D irqd_to_bank(data); =20 + gpiochip_enable_irq(&bank->gpio_chip, irqd_to_hwirq(data)); gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1); } =20 @@ -1312,6 +1315,7 @@ static void pistachio_gpio_irq_handler(struct irq_des= c *desc) =20 #define GPIO_BANK(_bank, _pin_base, _npins) \ { \ + .instance =3D (_bank), \ .pin_base =3D _pin_base, \ .npins =3D _npins, \ .gpio_chip =3D { \ @@ -1326,14 +1330,6 @@ static void pistachio_gpio_irq_handler(struct irq_de= sc *desc) .base =3D _pin_base, \ .ngpio =3D _npins, \ }, \ - .irq_chip =3D { \ - .name =3D "GPIO" #_bank, \ - .irq_startup =3D pistachio_gpio_irq_startup, \ - .irq_ack =3D pistachio_gpio_irq_ack, \ - .irq_mask =3D pistachio_gpio_irq_mask, \ - .irq_unmask =3D pistachio_gpio_irq_unmask, \ - .irq_set_type =3D pistachio_gpio_irq_set_type, \ - }, \ } =20 static struct pistachio_gpio_bank pistachio_gpio_banks[] =3D { @@ -1345,6 +1341,25 @@ static struct pistachio_gpio_bank pistachio_gpio_ban= ks[] =3D { GPIO_BANK(5, PISTACHIO_PIN_MFIO(80), 10), }; =20 +static void pistachio_gpio_irq_print_chip(struct irq_data *data, + struct seq_file *p) +{ + struct pistachio_gpio_bank *bank =3D irqd_to_bank(data); + + seq_printf(p, "GPIO%d", bank->instance); +} + +static const struct irq_chip pistachio_gpio_irq_chip =3D { + .irq_startup =3D pistachio_gpio_irq_startup, + .irq_ack =3D pistachio_gpio_irq_ack, + .irq_mask =3D pistachio_gpio_irq_mask, + .irq_unmask =3D pistachio_gpio_irq_unmask, + .irq_set_type =3D pistachio_gpio_irq_set_type, + .irq_print_chip =3D pistachio_gpio_irq_print_chip, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) { struct pistachio_gpio_bank *bank; @@ -1394,7 +1409,7 @@ static int pistachio_gpio_register(struct pistachio_p= inctrl *pctl) bank->gpio_chip.fwnode =3D child; =20 girq =3D &bank->gpio_chip.irq; - girq->chip =3D &bank->irq_chip; + gpio_irq_chip_set_chip(girq, &pistachio_gpio_irq_chip); girq->parent_handler =3D pistachio_gpio_irq_handler; girq->num_parents =3D 1; girq->parents =3D devm_kcalloc(pctl->dev, 1, --=20 2.34.1