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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:30:00.9740 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2d414a9-8927-412a-2735-08db3c44b5ea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E63A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4156 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On AMD and Hygon processors supporting X86_FEATURE_TOPOEXT set the l2c_id using the Extended APIC ID and the Cache Properties CPUID. Tested-by: Oleksandr Natalenko Signed-off-by: K Prateek Nayak --- o v1->v2 - No functional changes since v1 for AMD processors. - Renamed cacheinfo_amd_init_l2c_id() to cacheinfo_topoext_init_l2c_id() and added the call to same in Hygon's topology init path. - Collected tags from v1. --- arch/x86/include/asm/cacheinfo.h | 1 + arch/x86/kernel/cpu/amd.c | 1 + arch/x86/kernel/cpu/cacheinfo.c | 36 ++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/hygon.c | 1 + 4 files changed, 39 insertions(+) diff --git a/arch/x86/include/asm/cacheinfo.h b/arch/x86/include/asm/cachei= nfo.h index ce9685fc78d8..2034cd556c07 100644 --- a/arch/x86/include/asm/cacheinfo.h +++ b/arch/x86/include/asm/cacheinfo.h @@ -7,6 +7,7 @@ extern unsigned int memory_caching_control; #define CACHE_MTRR 0x01 #define CACHE_PAT 0x02 =20 +void cacheinfo_topoext_init_l2c_id(struct cpuinfo_x86 *c, int cpu); void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu); void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu); =20 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index f769d6d08b43..500401b9e645 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -358,6 +358,7 @@ static void amd_get_topology(struct cpuinfo_x86 *c) if (!err) c->x86_coreid_bits =3D get_count_order(c->x86_max_cores); =20 + cacheinfo_topoext_init_l2c_id(c, cpu); cacheinfo_amd_init_llc_id(c, cpu); =20 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index f4e5aa27eec6..bed7b9633451 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -659,6 +659,42 @@ static int find_num_cache_leaves(struct cpuinfo_x86 *c) return i; } =20 +void cacheinfo_topoext_init_l2c_id(struct cpuinfo_x86 *c, int cpu) +{ + u32 eax, ebx, ecx, edx, num_sharing_cache; + int i =3D 0, bits; + + /* Check if L2 cache identifiers exists. */ + if (!cpuid_ecx(0x80000006)) + return; + + while (true) { + u32 level; + + cpuid_count(0x8000001d, i, &eax, &ebx, &ecx, &edx); + if (!eax) + return; + + /* + * Check if the current leaf is for L2 cache using + * eax[7:5] used to describe the cache level. + */ + level =3D (eax >> 5) & 0x7; + if (level =3D=3D 2) + break; + + ++i; + } + + /* + * L2 ID is calculated from the number of threads + * sharing the L2 cache. + */ + num_sharing_cache =3D ((eax >> 14) & 0xfff) + 1; + bits =3D get_count_order(num_sharing_cache); + per_cpu(cpu_l2c_id, cpu) =3D c->apicid >> bits; +} + void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu) { /* diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index 5a2962c492d3..cb0025b4a2fd 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -89,6 +89,7 @@ static void hygon_get_topology(struct cpuinfo_x86 *c) /* Socket ID is ApicId[6] for these processors. */ c->phys_proc_id =3D c->apicid >> APICID_SOCKET_ID_BIT; =20 + cacheinfo_topoext_init_l2c_id(c, cpu); cacheinfo_hygon_init_llc_id(c, cpu); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:30:25.8335 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d665472e-6b3b-468e-69a0-08db3c44c4bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E637.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6405 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" x86 processors map cluster to the L2 cache. Add documentation stating the same, and provide more information on the values and API related to CPU clusters exposed by the kernel. Signed-off-by: K Prateek Nayak --- o v1->v2 - Reworded the definition of cluster on x86 based on Peter's suggestion. - Fixed double spacing before and after the cluster section. --- Documentation/x86/topology.rst | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/x86/topology.rst b/Documentation/x86/topology.rst index 7f58010ea86a..5dae8a0327d1 100644 --- a/Documentation/x86/topology.rst +++ b/Documentation/x86/topology.rst @@ -33,6 +33,7 @@ historical nature and should be cleaned up. The topology of a system is described in the units of: =20 - packages + - cluster - cores - threads =20 @@ -90,6 +91,23 @@ Package-related topology information in the kernel: Cache. In general, it is a number identifying an LLC uniquely on t= he system. =20 +Clusters +=3D=3D=3D=3D=3D=3D=3D=3D +A cluster consists of threads of one or more cores sharing the same L2 cac= he. + +Cluster-related topology information in the kernel: + + - cluster_id: + + A per-CPU variable containing: + + - On Intel, the common upper bits of APIC ID of the list of CPUs sha= ring + the L2 Cache with lower bits set to 0. + + - On AMD and Hygon, with Topology Extension, the common upper bits o= f the + Extended APIC ID of the list of CPUs sharing the L2 Cache, left sh= ifted + to remove trailing 0s. + Cores =3D=3D=3D=3D=3D A core consists of 1 or more threads. It does not matter whether the threa= ds @@ -125,6 +143,11 @@ Thread-related topology information in the kernel: =20 The number of online threads is also printed in /proc/cpuinfo "sibling= s." =20 + - topology_cluster_cpumask(): + + The cpumask contains all online threads in the cluster to which a thre= ad + belongs. + - topology_sibling_cpumask(): =20 The cpumask contains all online threads in the core to which a thread @@ -138,6 +161,10 @@ Thread-related topology information in the kernel: =20 The physical package ID to which a thread belongs. =20 + - topology_cluster_id(); + + The ID of the cluster to which a thread belongs. + - topology_core_id(); =20 The ID of the core to which a thread belongs. It is also printed in /p= roc/cpuinfo --=20 2.34.1