From nobody Wed Dec 17 10:03:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79FF9C77B72 for ; Thu, 20 Apr 2023 17:33:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231636AbjDTRdE (ORCPT ); Thu, 20 Apr 2023 13:33:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231586AbjDTRc7 (ORCPT ); Thu, 20 Apr 2023 13:32:59 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3948D49E6 for ; Thu, 20 Apr 2023 10:32:56 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id y24so3667413ljm.6 for ; Thu, 20 Apr 2023 10:32:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682011974; x=1684603974; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=P1QUEi4KCioig+7MEuspZ8Q1/71UjWTN1Jyb1cQYkHw=; b=O85RtNVrl9M4nCdFA4BXrn/HEFzclT+XKWDgbs4vtvP8aycnyWRl1hJ5gbDoJD7cyE f6EA2f5v6PQzF/Ql/WX5hHwxXzTxTEkDCIU/uQGm1/cxi38OWuavmNTB0aAI14+V3H4r Q1YT2+n4G+cFGo+JM49sE4c3oJC9ahqhw9BzxBfQVxzRxMPq7Y0PSIGGVCC4xxOJJl3E /p12xY8OcpHFzQTSppI94is8Mpgy3aSczya9cvqFSdwp+Ep0nHshU3UoCIRr/lsWTecL 2mEBgev6Gl2J0u6AervWlVSB+ZiYFd5uyt9bhq2+mJMrFosUmsKJkbCfy3Seu+yrKGQS hpUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682011974; x=1684603974; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P1QUEi4KCioig+7MEuspZ8Q1/71UjWTN1Jyb1cQYkHw=; b=kQ7fDQlg8aP76S3UoALHP/LIRYIfXUSXB2cGlIg0VrRnWhw/qhY13r+LDJMDhLcE9B D4ALMPsJr27epwW6gFzK2JIPGiasxv97PZzUNv15IyqbGm4lcHIAAeuqXwYCUdbqabmI SNxBpryhpBOXbqZSBodRXPjQ/8ctj0RVgdJIwJ+nc4pIpvZzpHd/RO/UBE+IIU7cNruJ GCX4esxZo2qixOiISEs+R1FblKVWWWE/k3w+SikLdBlvQ4e0xQDiIP7EXgpa2tM+BKL0 DJJR6nRsItmVC7nxUAFhi5jFVudIi2LNxlzIYPDWWtBRjpHdrBmCNzNHX1JPq3J6riwP 4jTQ== X-Gm-Message-State: AAQBX9fxlTof51pvUm9JyFizma6PfY732RBMBPHy7NfVr5gm/UbMIkGG ZJD7v550jzT/SeagJDWH38qDaQ== X-Google-Smtp-Source: AKy350aJnCxM8HWEyF1YEXqdKt+VkAX0vQneduQniFOJMHsQfjTNv5V3v2u9E3gjgvgr90AJYJQo+Q== X-Received: by 2002:a2e:8012:0:b0:2a8:dcb0:6c8e with SMTP id j18-20020a2e8012000000b002a8dcb06c8emr652376ljg.33.1682011974585; Thu, 20 Apr 2023 10:32:54 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id e22-20020a2e8ed6000000b002a8c1462ecbsm309597ljl.137.2023.04.20.10.32.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 10:32:54 -0700 (PDT) From: Konrad Dybcio Date: Thu, 20 Apr 2023 19:32:50 +0200 Subject: [PATCH v4 1/2] dt-bindings: clock: Add SM8350 VIDEOCC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org> References: <20230413-topic-lahaina_vidcc-v4-0-86c714a66a81@linaro.org> In-Reply-To: <20230413-topic-lahaina_vidcc-v4-0-86c714a66a81@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , Taniya Das Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682011971; l=4835; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9Ky1ETSdCXuI6Z+f0jtlluA/Pju2puOcRtbU8+oK15g=; b=Xe/RzGuRAEWqTfw1c0NmBK1z59sxOZ+KoyGkQ3PKlk8dIlAoOkyiKLcuPHSGDWM50fPOD5yHKNuL ypHkG8j7DF3nJSgT2gOZowhUF4OcznDQ4moEC9lDc3x8FfKOC+Ia X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SM8350, like most recent higher-end chips has a separate clock controller block just for the Venus IP. Document it. The binding was separated as the driver, unlike the earlier ones, doesn't expect clock-names to keep it easier to maintain. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8350-videocc.yaml | 68 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,sm8350-videocc.h | 35 +++++++++++ include/dt-bindings/reset/qcom,sm8350-videocc.h | 18 ++++++ 3 files changed, 121 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml new file mode 100644 index 000000000000..23505c8c3dbd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Video Clock & Reset Controller + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,videocc-sm8350.h + include/dt-bindings/reset/qcom,videocc-sm8350.h + +properties: + compatible: + const: qcom,sm8350-videocc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Board sleep clock + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + - required-opps + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + clock-controller@abf0000 { + compatible =3D "qcom,sm8350-videocc"; + reg =3D <0x0abf0000 0x10000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm8350-videocc.h b/include/dt-b= indings/clock/qcom,sm8350-videocc.h new file mode 100644 index 000000000000..b6945a448676 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8350-videocc.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H + +/* Clocks */ +#define VIDEO_CC_AHB_CLK_SRC 0 +#define VIDEO_CC_MVS0_CLK 1 +#define VIDEO_CC_MVS0_CLK_SRC 2 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 3 +#define VIDEO_CC_MVS0C_CLK 4 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 5 +#define VIDEO_CC_MVS1_CLK 6 +#define VIDEO_CC_MVS1_CLK_SRC 7 +#define VIDEO_CC_MVS1_DIV2_CLK 8 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 9 +#define VIDEO_CC_MVS1C_CLK 10 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11 +#define VIDEO_CC_SLEEP_CLK 12 +#define VIDEO_CC_SLEEP_CLK_SRC 13 +#define VIDEO_CC_XO_CLK_SRC 14 +#define VIDEO_PLL0 15 +#define VIDEO_PLL1 16 + +/* GDSCs */ +#define MVS0C_GDSC 0 +#define MVS1C_GDSC 1 +#define MVS0_GDSC 2 +#define MVS1_GDSC 3 + +#endif diff --git a/include/dt-bindings/reset/qcom,sm8350-videocc.h b/include/dt-b= indings/reset/qcom,sm8350-videocc.h new file mode 100644 index 000000000000..cd356b207a4a --- /dev/null +++ b/include/dt-bindings/reset/qcom,sm8350-videocc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H +#define _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H + +#define VIDEO_CC_CVP_INTERFACE_BCR 0 +#define VIDEO_CC_CVP_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_CVP_MVS0C_BCR 3 +#define VIDEO_CC_CVP_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define VIDEO_CC_CVP_MVS1C_BCR 6 + +#endif --=20 2.40.0 From nobody Wed Dec 17 10:03:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A9F8C77B7A for ; Thu, 20 Apr 2023 17:33:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231676AbjDTRdO (ORCPT ); Thu, 20 Apr 2023 13:33:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231615AbjDTRdD (ORCPT ); Thu, 20 Apr 2023 13:33:03 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F057E449A for ; Thu, 20 Apr 2023 10:32:57 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2a8baeac4d1so6336241fa.1 for ; Thu, 20 Apr 2023 10:32:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682011976; x=1684603976; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dhccM9/eMTOd/LuYcHsCJo0EEgm5osKm7YU+7iXvH8o=; b=LjXe9Id10+eSrdtCq3SecLxfUa7aeRz+ZfHSzKoAy/YGZf2GUnCQJzbVAqIuklFTnd 0Q2P2/iwoyXJlYrI04KPWeKKuT3NOjq1+XOsNl9PY3NoDoQ97is71RtVhO5D6s7ki0v+ s+go7D/+LsHOY8Fzk7yTqkCeTpIQaRQS41MiIr9Y4p/vSZrucgGvH/NIYYYUZ4wKrQ/1 ZdqlnyNqqIlwgkgpUsH7mxCR9c3SAWjbRL10qRF8iyia9ImVAkRIY0hS6Ig6PS7MYSKL UWWNbOVEOgLKfRlp20OwQhPdS0MPTjAghgf44zBf1lzBk4Du5+nG0vyko+udjdAo7N7q j1GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682011976; x=1684603976; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dhccM9/eMTOd/LuYcHsCJo0EEgm5osKm7YU+7iXvH8o=; b=QNiZfsJ0f91V6LrSQGTcW6Gfu6MCsKdpJJAroVVCp+4Sus8yfNPwB4b6AyKsYwWJwE 2IdHUKFvhx8k41E1RoHElXwCeMArsq95A8IUXGa9jcJsjnNHR3hYRollYUGDQwX4OCzR a/QgBJ3uAkZKbCQx8XjGMLlGGux9mlURIfB309wwZ6nS4Hy+3qDVWkXibfywmZ0tr1SG zee1odfbqvSo8Gf9IVHqOyNUNqsPCzBfjfun45z0lIULd/xXmmzNxrHFSCdQIu/1E7h4 +fg+QNtVWSfAsHrS7+C6qXJqgMfnIv8hPsSDJHj04ZzYeqbSPBU7nUbakiSbqtgeRuen TInQ== X-Gm-Message-State: AAQBX9dlJNBYicWmKdYAHVZFEoKQSZkHULq1BUfr4oo9zS+UTTA+4ldN BNpUzJchX92v66bqjWR+j7I4/g== X-Google-Smtp-Source: AKy350b3N1cNQEdAXdC0dShEDnCVnhn31pwRekrkT+QqMQVImOihM5IUBvclgESp5KIvUvcIQJrZww== X-Received: by 2002:ac2:51a3:0:b0:4ee:d63b:c08d with SMTP id f3-20020ac251a3000000b004eed63bc08dmr653368lfk.48.1682011976078; Thu, 20 Apr 2023 10:32:56 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id e22-20020a2e8ed6000000b002a8c1462ecbsm309597ljl.137.2023.04.20.10.32.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 10:32:55 -0700 (PDT) From: Konrad Dybcio Date: Thu, 20 Apr 2023 19:32:51 +0200 Subject: [PATCH v4 2/2] clk: qcom: Introduce SM8350 VIDEOCC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230413-topic-lahaina_vidcc-v4-2-86c714a66a81@linaro.org> References: <20230413-topic-lahaina_vidcc-v4-0-86c714a66a81@linaro.org> In-Reply-To: <20230413-topic-lahaina_vidcc-v4-0-86c714a66a81@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , Taniya Das Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682011971; l=16996; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=XcN5KCQUkpBqtjOGBAy1iX5s0WOK2lh/KKmarfTvjAs=; b=HjOnfSHs7UrL1HPxZt8TlbJ8wDKdQyzMoYqrvUeA1AdvVrvGkc/f1ThOJTvmcSkUyqXHdQ3dIRig 8S8JSlUeDqvNQv2LPtqk3sIPtd1vgndjgLjx1kDIl773O/3xGv74 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the Video Clock Controller found on the SM8350 SoC. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-sm8350.c | 552 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 562 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 12be3e2371b3..32e1302d86ab 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -925,6 +925,15 @@ config SM_VIDEOCC_8250 Say Y if you want to support video devices and functionality such as video encode and decode. =20 +config SM_VIDEOCC_8350 + tristate "SM8350 Video Clock Controller" + select SM_GCC_8350 + select QCOM_GDSC + help + Support for the video clock controller on SM8350 devices. + Say Y if you want to support video devices and functionality such as + video encode and decode. + config SPMI_PMIC_CLKDIV tristate "SPMI PMIC clkdiv Support" depends on SPMI || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 9ff4c373ad95..79405b19b85d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -127,6 +127,7 @@ obj-$(CONFIG_SM_GPUCC_8350) +=3D gpucc-sm8350.o obj-$(CONFIG_SM_TCSRCC_8550) +=3D tcsrcc-sm8550.o obj-$(CONFIG_SM_VIDEOCC_8150) +=3D videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) +=3D videocc-sm8250.o +obj-$(CONFIG_SM_VIDEOCC_8350) +=3D videocc-sm8350.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) +=3D clk-spmi-pmic-div.o obj-$(CONFIG_KPSS_XCC) +=3D kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) +=3D hfpll.o diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-s= m8350.c new file mode 100644 index 000000000000..b148877fc73d --- /dev/null +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" +#include "gdsc.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_AO, + P_SLEEP_CLK, + P_VIDEO_PLL0_OUT_MAIN, + P_VIDEO_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_5lpe_vco[] =3D { + { 249600000, 1750000000, 0 }, +}; + +static const struct alpha_pll_config video_pll0_config =3D { + .l =3D 0x25, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00002261, + .config_ctl_hi1_val =3D 0x2a9a699c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000000, + .test_ctl_hi1_val =3D 0x01800000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000805, + .user_ctl_hi1_val =3D 0x00000000, +}; + +static struct clk_alpha_pll video_pll0 =3D { + .offset =3D 0x42c, + .vco_table =3D lucid_5lpe_vco, + .num_vco =3D ARRAY_SIZE(lucid_5lpe_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_pll0", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct alpha_pll_config video_pll1_config =3D { + .l =3D 0x2b, + .alpha =3D 0xc000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00002261, + .config_ctl_hi1_val =3D 0x2a9a699c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000000, + .test_ctl_hi1_val =3D 0x01800000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000805, + .user_ctl_hi1_val =3D 0x00000000, +}; + +static struct clk_alpha_pll video_pll1 =3D { + .offset =3D 0x7d0, + .vco_table =3D lucid_5lpe_vco, + .num_vco =3D ARRAY_SIZE(lucid_5lpe_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_pll1", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_BI_TCXO_AO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO_AO }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL1_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_pll1.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src =3D { + .cmd_rcgr =3D 0xbd4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_ahb_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] =3D { + F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0xb94, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] =3D { + F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs1_clk_src =3D { + .cmd_rcgr =3D 0xbb4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_2, + .freq_tbl =3D ftbl_video_cc_mvs1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_clk_src", + .parent_data =3D video_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0xef0, + .mnd_width =3D 0, + .hid_width =3D 5, + .freq_tbl =3D ftbl_video_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sleep_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_SLEEP_CLK, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0xecc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_xo_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_div_clk_src =3D { + .reg =3D 0xd54, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src =3D { + .reg =3D 0xc54, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1_div_clk_src =3D { + .reg =3D 0xdd4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src =3D { + .reg =3D 0xcf4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk =3D { + .halt_reg =3D 0xd34, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xd34, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xd34, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk =3D { + .halt_reg =3D 0xc34, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xc34, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_clk =3D { + .halt_reg =3D 0xdb4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xdb4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xdb4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_div2_clk =3D { + .halt_reg =3D 0xdf4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xdf4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xdf4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_div2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1c_clk =3D { + .halt_reg =3D 0xcd4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xcd4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1c_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_sleep_clk =3D { + .halt_reg =3D 0xf10, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf10, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_sleep_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mvs0c_gdsc =3D { + .gdscr =3D 0xbf8, + .pd =3D { + .name =3D "mvs0c_gdsc", + }, + .flags =3D RETAIN_FF_ENABLE, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc mvs1c_gdsc =3D { + .gdscr =3D 0xc98, + .pd =3D { + .name =3D "mvs1c_gdsc", + }, + .flags =3D RETAIN_FF_ENABLE, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc mvs0_gdsc =3D { + .gdscr =3D 0xd18, + .pd =3D { + .name =3D "mvs0_gdsc", + }, + .flags =3D HW_CTRL | RETAIN_FF_ENABLE, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc mvs1_gdsc =3D { + .gdscr =3D 0xd98, + .pd =3D { + .name =3D "mvs1_gdsc", + }, + .flags =3D HW_CTRL | RETAIN_FF_ENABLE, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct clk_regmap *video_cc_sm8350_clocks[] =3D { + [VIDEO_CC_AHB_CLK_SRC] =3D &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] =3D &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] =3D &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] =3D &video_cc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0C_CLK] =3D &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] =3D &video_cc_mvs0c_div2_div_clk_src.cl= kr, + [VIDEO_CC_MVS1_CLK] =3D &video_cc_mvs1_clk.clkr, + [VIDEO_CC_MVS1_CLK_SRC] =3D &video_cc_mvs1_clk_src.clkr, + [VIDEO_CC_MVS1_DIV2_CLK] =3D &video_cc_mvs1_div2_clk.clkr, + [VIDEO_CC_MVS1_DIV_CLK_SRC] =3D &video_cc_mvs1_div_clk_src.clkr, + [VIDEO_CC_MVS1C_CLK] =3D &video_cc_mvs1c_clk.clkr, + [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] =3D &video_cc_mvs1c_div2_div_clk_src.cl= kr, + [VIDEO_CC_SLEEP_CLK] =3D &video_cc_sleep_clk.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] =3D &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_XO_CLK_SRC] =3D &video_cc_xo_clk_src.clkr, + [VIDEO_PLL0] =3D &video_pll0.clkr, + [VIDEO_PLL1] =3D &video_pll1.clkr, +}; + +static const struct qcom_reset_map video_cc_sm8350_resets[] =3D { + [VIDEO_CC_CVP_INTERFACE_BCR] =3D { 0xe54 }, + [VIDEO_CC_CVP_MVS0_BCR] =3D { 0xd14 }, + [VIDEO_CC_MVS0C_CLK_ARES] =3D { 0xc34, 2 }, + [VIDEO_CC_CVP_MVS0C_BCR] =3D { 0xbf4 }, + [VIDEO_CC_CVP_MVS1_BCR] =3D { 0xd94 }, + [VIDEO_CC_MVS1C_CLK_ARES] =3D { 0xcd4, 2 }, + [VIDEO_CC_CVP_MVS1C_BCR] =3D { 0xc94 }, +}; + +static struct gdsc *video_cc_sm8350_gdscs[] =3D { + [MVS0C_GDSC] =3D &mvs0c_gdsc, + [MVS1C_GDSC] =3D &mvs1c_gdsc, + [MVS0_GDSC] =3D &mvs0_gdsc, + [MVS1_GDSC] =3D &mvs1_gdsc, +}; + +static const struct regmap_config video_cc_sm8350_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x10000, + .fast_io =3D true, +}; + +static struct qcom_cc_desc video_cc_sm8350_desc =3D { + .config =3D &video_cc_sm8350_regmap_config, + .clks =3D video_cc_sm8350_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_sm8350_clocks), + .resets =3D video_cc_sm8350_resets, + .num_resets =3D ARRAY_SIZE(video_cc_sm8350_resets), + .gdscs =3D video_cc_sm8350_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_sm8350_gdscs), +}; + +static int video_cc_sm8350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + ret =3D devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap =3D qcom_cc_map(pdev, &video_cc_sm8350_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); + clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); + + /* + * Keep clocks always enabled: + * video_cc_ahb_clk + * video_cc_xo_clk + */ + regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); + + ret =3D qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; +} + +static const struct of_device_id video_cc_sm8350_match_table[] =3D { + { .compatible =3D "qcom,sm8350-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_sm8350_match_table); + +static struct platform_driver video_cc_sm8350_driver =3D { + .probe =3D video_cc_sm8350_probe, + .driver =3D { + .name =3D "sm8350-videocc", + .of_match_table =3D video_cc_sm8350_match_table, + }, +}; +module_platform_driver(video_cc_sm8350_driver); + +MODULE_DESCRIPTION("QTI SM8350 VIDEOCC Driver"); +MODULE_LICENSE("GPL"); --=20 2.40.0