From nobody Fri Dec 19 03:44:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89605C77B71 for ; Thu, 13 Apr 2023 18:45:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230241AbjDMSpm (ORCPT ); Thu, 13 Apr 2023 14:45:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230117AbjDMSph (ORCPT ); Thu, 13 Apr 2023 14:45:37 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 648C683ED for ; Thu, 13 Apr 2023 11:45:10 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id u12so2695292lfu.5 for ; Thu, 13 Apr 2023 11:45:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681411504; x=1684003504; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hZACr2qT1r+Pq/JG1rFFm+OjlMblwToTQZN+UEc9YSE=; b=ipoZ09DD8FOfkQzZoNddbAAVIjuTGgv3X8jItYX/VKEDi4DKFx0hMeQw1RilOubilj uU0B5n6+CXaU1AtxicTzo8me/QtmJQ6sF0FxduKsAyflcBaOtzRvMFS7r7Yksq2zlMq6 t4TldUJ9XhZiveAq+OpW6NoNJ3AwMfiLZjNBKcC83zGD4ltSCtvyuiolOSg8VPOamC+8 /cZDBOPoLJog3Fuof+RaSkX1iWtDMF+rK4HGSwCEXevazjoLpXWlmAuaQxDDWWHP3n23 LEgmt28rS+LsA0Jd2vePORdbaVvhv+mruCFrw2oaCtl16Uvfrw/Ck/5QRMPPWOLyCrvx vBiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681411504; x=1684003504; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hZACr2qT1r+Pq/JG1rFFm+OjlMblwToTQZN+UEc9YSE=; b=jECEtE97WflSIk0Yo23VOayBdKxyVKBkgd5CTKlM3xRtJ7way5FTspgwA6+VojhMzp puHLNDbzGW3Z0K6lLUso460R4d5YoaD+KO4k+kgn4jUOXMGaTCvzKk0z67Mnrwk2iBDp ftZxzfNdoRLf/0N3eXSbz4zW5IAoWQZ7xCxflT0JDjNE5m18Oi3WxeDgayofrHlv6e9r oAXeB3M7Df5f+DbLeI0zAZ/Yry2src0IEtdym0kPoIXy/Han40mfgVPCHQvrXApweG2V SP7p4E5un1lvOk14RG1IwMXPv+j7igxJmgUgtD0vJap1jjME//t91mKpHvx0NaStCu14 0zhQ== X-Gm-Message-State: AAQBX9evBtzP8McXpHPFzflxlXJijtDqd+v8NJXeZ/sPmouIXP7bI81G z2zIunYHkND+NAKys4PcKa+fvQ== X-Google-Smtp-Source: AKy350a/4OMy48fn79E4+jYeY45rNsKnNmTWLoYvl4/gP65R2uYAcZ7FhKBxQs5Wbr9xlEo8cpnJbw== X-Received: by 2002:ac2:4895:0:b0:4d5:a689:7580 with SMTP id x21-20020ac24895000000b004d5a6897580mr1315941lfc.47.1681411503841; Thu, 13 Apr 2023 11:45:03 -0700 (PDT) Received: from [192.168.1.101] (abyl123.neoplus.adsl.tpnet.pl. [83.9.31.123]) by smtp.gmail.com with ESMTPSA id r12-20020ac24d0c000000b004e95f53adc7sm419621lfi.27.2023.04.13.11.45.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Apr 2023 11:45:03 -0700 (PDT) From: Konrad Dybcio Date: Thu, 13 Apr 2023 20:44:58 +0200 Subject: [PATCH 1/2] dt-bindings: clock: qcom,videocc: Add SM8350 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230413-topic-lahaina_vidcc-v1-1-134f9b22a5b3@linaro.org> References: <20230413-topic-lahaina_vidcc-v1-0-134f9b22a5b3@linaro.org> In-Reply-To: <20230413-topic-lahaina_vidcc-v1-0-134f9b22a5b3@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , Taniya Das Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681411500; l=4559; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=yDNgI5vaFDUinUfBBr+IuGY3i/nybTj/plx2VvRXMcU=; b=kCI9+Y3Yau+8W4V5pT49oVmrNAQ+AMsy1qHMQJv0ZoeP7gblBQqWZjfEc7J9boIRTdoKnPYxre40 2HjDfGoiAa1QF3RcaEv7cyXAgZSkuUfMbWN74nOdyzhuMLI+bQl0 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SM8350, like most recent higher-end chips has a separate clock controller block just for the Venus IP. Document it. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/clock/qcom,videocc.yaml | 29 +++++++++++++++++- include/dt-bindings/clock/qcom,sm8350-videocc.h | 35 ++++++++++++++++++= ++++ include/dt-bindings/reset/qcom,sm8350-videocc.h | 18 +++++++++++ 3 files changed, 81 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Do= cumentation/devicetree/bindings/clock/qcom,videocc.yaml index 2b07146161b4..6d892b0f2306 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -19,6 +19,8 @@ description: | include/dt-bindings/clock/qcom,videocc-sdm845.h include/dt-bindings/clock/qcom,videocc-sm8150.h include/dt-bindings/clock/qcom,videocc-sm8250.h + include/dt-bindings/clock/qcom,videocc-sm8350.h + include/dt-bindings/reset/qcom,videocc-sm8350.h =20 properties: compatible: @@ -28,6 +30,7 @@ properties: - qcom,sdm845-videocc - qcom,sm8150-videocc - qcom,sm8250-videocc + - qcom,sm8350-videocc =20 clocks: minItems: 1 @@ -63,7 +66,6 @@ required: - compatible - reg - clocks - - clock-names - '#clock-cells' - '#reset-cells' - '#power-domain-cells' @@ -85,6 +87,9 @@ allOf: items: - const: bi_tcxo =20 + required: + - clock-names + - if: properties: compatible: @@ -101,6 +106,9 @@ allOf: - const: bi_tcxo - const: bi_tcxo_ao =20 + required: + - clock-names + - if: properties: compatible: @@ -119,6 +127,25 @@ allOf: - const: bi_tcxo - const: bi_tcxo_ao =20 + required: + - clock-names + + - if: + properties: + compatible: + enum: + - qcom,sm8350-videocc + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Board sleep clock + + required: + - power-domains + additionalProperties: false =20 examples: diff --git a/include/dt-bindings/clock/qcom,sm8350-videocc.h b/include/dt-b= indings/clock/qcom,sm8350-videocc.h new file mode 100644 index 000000000000..b6945a448676 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8350-videocc.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H + +/* Clocks */ +#define VIDEO_CC_AHB_CLK_SRC 0 +#define VIDEO_CC_MVS0_CLK 1 +#define VIDEO_CC_MVS0_CLK_SRC 2 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 3 +#define VIDEO_CC_MVS0C_CLK 4 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 5 +#define VIDEO_CC_MVS1_CLK 6 +#define VIDEO_CC_MVS1_CLK_SRC 7 +#define VIDEO_CC_MVS1_DIV2_CLK 8 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 9 +#define VIDEO_CC_MVS1C_CLK 10 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11 +#define VIDEO_CC_SLEEP_CLK 12 +#define VIDEO_CC_SLEEP_CLK_SRC 13 +#define VIDEO_CC_XO_CLK_SRC 14 +#define VIDEO_PLL0 15 +#define VIDEO_PLL1 16 + +/* GDSCs */ +#define MVS0C_GDSC 0 +#define MVS1C_GDSC 1 +#define MVS0_GDSC 2 +#define MVS1_GDSC 3 + +#endif diff --git a/include/dt-bindings/reset/qcom,sm8350-videocc.h b/include/dt-b= indings/reset/qcom,sm8350-videocc.h new file mode 100644 index 000000000000..df7a808720ee --- /dev/null +++ b/include/dt-bindings/reset/qcom,sm8350-videocc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H +#define _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H + +#define CVP_VIDEO_CC_INTERFACE_BCR 0 +#define CVP_VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define CVP_VIDEO_CC_MVS0C_BCR 3 +#define CVP_VIDEO_CC_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define CVP_VIDEO_CC_MVS1C_BCR 6 + +#endif --=20 2.40.0 From nobody Fri Dec 19 03:44:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6763FC77B6E for ; Thu, 13 Apr 2023 18:45:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230270AbjDMSpq (ORCPT ); Thu, 13 Apr 2023 14:45:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230250AbjDMSpl (ORCPT ); Thu, 13 Apr 2023 14:45:41 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C41876AA for ; Thu, 13 Apr 2023 11:45:12 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id x4so501294lfr.8 for ; Thu, 13 Apr 2023 11:45:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681411505; x=1684003505; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+R8RC3kGQqgnaooJNYVw/1Mh9uv8861rn5bH89aAReM=; b=QoXXtSPYps2JS9upZSF+fHpJWOjrm0z/CIB0ffxv5OJrGK7x9PzKGnLGEXPQ+LUhJd ttBeB8KUXjIFQjgsRLff1KU53U7GCfFXanGcRedv9PNydTA1MoReH5iNTE4ctyNpIkqI R+3ABjMtzl7FOPAq4qGBNrumtRIVMPpL7k/RyBc8Mih5dq8Olel08/idQN2ZmCuttgB2 UEFtIp4RVnk5vlkRDe+CmT4zhJvknEYAwP1Fk8aX/mLqwMIrjRrW8p1iJUI/BEYRloIW 5tFrfxqfJ17ywPdhXxfzWZhYh7tfsOJApf8xkzzJVpFFlKCsz9eVq/7FrFhjbhq5U0IE wlzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681411505; x=1684003505; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+R8RC3kGQqgnaooJNYVw/1Mh9uv8861rn5bH89aAReM=; b=Zm38WsifR+FOBU9gIupM/hE2BlhcCDdToqpIjpDpmFzqURHpZ2d/FhEwXjpnaaUORJ iEeUGBs6zpHd62m/YxjoyBmwcyNQBuUwORsg/IDB78r8ElLPLY0Cm5jV7w4xxWnvVRF2 sn4GxQ7OCvOTOfzwTjfa8XAvoJuFM9d9mtsG8czolzrcfGjjQduDw7Muwesg+jzquLEY bFC/TTs4CevaSeVPIu8Gj528XjKqYqrEwDzeJhUWG52ybVNonXCKXmyo/McBNz+MK/rL NwAWWRJqkioWSqNgnUXz5ve2GOg+LHV5YWGR9OYGEUmJ6kj80S7xN3IUUuatX1BypJbe kX2g== X-Gm-Message-State: AAQBX9doLOy7o324s4mAKtOQFc8usomphAI2j9KtQ/80xIdCz5IKdC97 fp1YYdvJTZIIHYMZps8tiMvDag== X-Google-Smtp-Source: AKy350Y1L0LqrMBPCsEt/RGUKui8p+uvQFJI0ACPjAA4VMWfpD9Xej6+UepT3K/mTvfpwE3Ilp4KKw== X-Received: by 2002:ac2:4e63:0:b0:4ed:b09a:6447 with SMTP id y3-20020ac24e63000000b004edb09a6447mr293467lfs.60.1681411505264; Thu, 13 Apr 2023 11:45:05 -0700 (PDT) Received: from [192.168.1.101] (abyl123.neoplus.adsl.tpnet.pl. [83.9.31.123]) by smtp.gmail.com with ESMTPSA id r12-20020ac24d0c000000b004e95f53adc7sm419621lfi.27.2023.04.13.11.45.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Apr 2023 11:45:04 -0700 (PDT) From: Konrad Dybcio Date: Thu, 13 Apr 2023 20:44:59 +0200 Subject: [PATCH 2/2] clk: qcom: Introduce SM8350 VIDEOCC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230413-topic-lahaina_vidcc-v1-2-134f9b22a5b3@linaro.org> References: <20230413-topic-lahaina_vidcc-v1-0-134f9b22a5b3@linaro.org> In-Reply-To: <20230413-topic-lahaina_vidcc-v1-0-134f9b22a5b3@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , Taniya Das Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681411500; l=17427; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=t2SuIf03zE+g67EYbEKVVwvVi13Twg5rvb4tqvAK/Ls=; b=5G7GHnxKmMs1UbEsnjOcjkLdiIBFtVxeUol5m07NyHWPQw0pnvy5SWxIeXU+LdqmhVveaeJH9kyM kUK6vIQ8CVDLRHdeawTxH+DxbcMxIEf1OzAHrpPXoReKFcqbpChA X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the Video Clock Controller found on the SM8350 SoC. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-sm8350.c | 575 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 585 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d71c9d6036bb..dbb1dfcddb31 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -916,6 +916,15 @@ config SM_VIDEOCC_8250 Say Y if you want to support video devices and functionality such as video encode and decode. =20 +config SM_VIDEOCC_8350 + tristate "SM8350 Video Clock Controller" + select SM_GCC_8350 + select QCOM_GDSC + help + Support for the video clock controller on SM8350 devices. + Say Y if you want to support video devices and functionality such as + video encode and decode. + config SPMI_PMIC_CLKDIV tristate "SPMI PMIC clkdiv Support" depends on SPMI || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b54085e579a0..53290040523b 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -126,6 +126,7 @@ obj-$(CONFIG_SM_GPUCC_8350) +=3D gpucc-sm8350.o obj-$(CONFIG_SM_TCSRCC_8550) +=3D tcsrcc-sm8550.o obj-$(CONFIG_SM_VIDEOCC_8150) +=3D videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) +=3D videocc-sm8250.o +obj-$(CONFIG_SM_VIDEOCC_8350) +=3D videocc-sm8350.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) +=3D clk-spmi-pmic-div.o obj-$(CONFIG_KPSS_XCC) +=3D kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) +=3D hfpll.o diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-s= m8350.c new file mode 100644 index 000000000000..186a5bd9e184 --- /dev/null +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" +#include "gdsc.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_AO, + P_SLEEP_CLK, + P_VIDEO_PLL0_OUT_MAIN, + P_VIDEO_PLL1_OUT_MAIN, +}; + +static struct pll_vco lucid_5lpe_vco[] =3D { + { 249600000, 1750000000, 0 }, +}; + +static const struct alpha_pll_config video_pll0_config =3D { + .l =3D 0x25, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00002261, + .config_ctl_hi1_val =3D 0x2a9a699c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000000, + .test_ctl_hi1_val =3D 0x01800000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000805, + .user_ctl_hi1_val =3D 0x00000000, +}; + +static struct clk_alpha_pll video_pll0 =3D { + .offset =3D 0x42c, + .vco_table =3D lucid_5lpe_vco, + .num_vco =3D ARRAY_SIZE(lucid_5lpe_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "video_pll0", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct alpha_pll_config video_pll1_config =3D { + .l =3D 0x2b, + .alpha =3D 0xc000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00002261, + .config_ctl_hi1_val =3D 0x2a9a699c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000000, + .test_ctl_hi1_val =3D 0x01800000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000805, + .user_ctl_hi1_val =3D 0x00000000, +}; + +static struct clk_alpha_pll video_pll1 =3D { + .offset =3D 0x7d0, + .vco_table =3D lucid_5lpe_vco, + .num_vco =3D ARRAY_SIZE(lucid_5lpe_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "video_pll1", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_BI_TCXO_AO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO_AO }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL1_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_pll1.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src =3D { + .cmd_rcgr =3D 0xbd4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_ahb_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] =3D { + F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0xb94, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_mvs0_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] =3D { + F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs1_clk_src =3D { + .cmd_rcgr =3D 0xbb4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_2, + .freq_tbl =3D ftbl_video_cc_mvs1_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_mvs1_clk_src", + .parent_data =3D video_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0xef0, + .mnd_width =3D 0, + .hid_width =3D 5, + .freq_tbl =3D ftbl_video_cc_sleep_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_sleep_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_SLEEP_CLK, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0xecc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_xo_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_div_clk_src =3D { + .reg =3D 0xd54, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "video_cc_mvs0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src =3D { + .reg =3D 0xc54, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "video_cc_mvs0c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1_div_clk_src =3D { + .reg =3D 0xdd4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "video_cc_mvs1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src =3D { + .reg =3D 0xcf4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "video_cc_mvs1c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk =3D { + .halt_reg =3D 0xd34, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xd34, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xd34, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk =3D { + .halt_reg =3D 0xc34, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xc34, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_clk =3D { + .halt_reg =3D 0xdb4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xdb4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xdb4, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_mvs1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_div2_clk =3D { + .halt_reg =3D 0xdf4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xdf4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xdf4, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_mvs1_div2_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1c_clk =3D { + .halt_reg =3D 0xcd4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xcd4, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_mvs1c_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_sleep_clk =3D { + .halt_reg =3D 0xf10, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xf10, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &video_cc_sleep_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mvs0c_gdsc =3D { + .gdscr =3D 0xbf8, + .pd =3D { + .name =3D "mvs0c_gdsc", + }, + .flags =3D RETAIN_FF_ENABLE, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc mvs1c_gdsc =3D { + .gdscr =3D 0xc98, + .pd =3D { + .name =3D "mvs1c_gdsc", + }, + .flags =3D RETAIN_FF_ENABLE, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc mvs0_gdsc =3D { + .gdscr =3D 0xd18, + .pd =3D { + .name =3D "mvs0_gdsc", + }, + .flags =3D HW_CTRL | RETAIN_FF_ENABLE, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc mvs1_gdsc =3D { + .gdscr =3D 0xd98, + .pd =3D { + .name =3D "mvs1_gdsc", + }, + .flags =3D HW_CTRL | RETAIN_FF_ENABLE, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct clk_regmap *video_cc_sm8350_clocks[] =3D { + [VIDEO_CC_AHB_CLK_SRC] =3D &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] =3D &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] =3D &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] =3D &video_cc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0C_CLK] =3D &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] =3D &video_cc_mvs0c_div2_div_clk_src.cl= kr, + [VIDEO_CC_MVS1_CLK] =3D &video_cc_mvs1_clk.clkr, + [VIDEO_CC_MVS1_CLK_SRC] =3D &video_cc_mvs1_clk_src.clkr, + [VIDEO_CC_MVS1_DIV2_CLK] =3D &video_cc_mvs1_div2_clk.clkr, + [VIDEO_CC_MVS1_DIV_CLK_SRC] =3D &video_cc_mvs1_div_clk_src.clkr, + [VIDEO_CC_MVS1C_CLK] =3D &video_cc_mvs1c_clk.clkr, + [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] =3D &video_cc_mvs1c_div2_div_clk_src.cl= kr, + [VIDEO_CC_SLEEP_CLK] =3D &video_cc_sleep_clk.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] =3D &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_XO_CLK_SRC] =3D &video_cc_xo_clk_src.clkr, + [VIDEO_PLL0] =3D &video_pll0.clkr, + [VIDEO_PLL1] =3D &video_pll1.clkr, +}; + +static const struct qcom_reset_map video_cc_sm8350_resets[] =3D { + [CVP_VIDEO_CC_INTERFACE_BCR] =3D { 0xe54 }, + [CVP_VIDEO_CC_MVS0_BCR] =3D { 0xd14 }, + [VIDEO_CC_MVS0C_CLK_ARES] =3D { 0xc34, 2 }, + [CVP_VIDEO_CC_MVS0C_BCR] =3D { 0xbf4 }, + [CVP_VIDEO_CC_MVS1_BCR] =3D { 0xd94 }, + [VIDEO_CC_MVS1C_CLK_ARES] =3D { 0xcd4, 2 }, + [CVP_VIDEO_CC_MVS1C_BCR] =3D { 0xc94 }, +}; + +static struct gdsc *video_cc_sm8350_gdscs[] =3D { + [MVS0C_GDSC] =3D &mvs0c_gdsc, + [MVS1C_GDSC] =3D &mvs1c_gdsc, + [MVS0_GDSC] =3D &mvs0_gdsc, + [MVS1_GDSC] =3D &mvs1_gdsc, +}; + +static const struct regmap_config video_cc_sm8350_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x10000, + .fast_io =3D true, +}; + +static struct qcom_cc_desc video_cc_sm8350_desc =3D { + .config =3D &video_cc_sm8350_regmap_config, + .clks =3D video_cc_sm8350_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_sm8350_clocks), + .resets =3D video_cc_sm8350_resets, + .num_resets =3D ARRAY_SIZE(video_cc_sm8350_resets), + .gdscs =3D video_cc_sm8350_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_sm8350_gdscs), +}; + +static void video_cc_sm8350_pm_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + +static int video_cc_sm8350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + pm_runtime_enable(&pdev->dev); + + ret =3D devm_add_action_or_reset(&pdev->dev, video_cc_sm8350_pm_runtime_d= isable, &pdev->dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap =3D qcom_cc_map(pdev, &video_cc_sm8350_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + }; + + clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); + clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); + + /* + * Keep clocks always enabled: + * video_cc_ahb_clk + * video_cc_xo_clk + */ + regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); + + ret =3D qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; +} + +static const struct dev_pm_ops video_cc_sm8350_pm_ops =3D { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static const struct of_device_id video_cc_sm8350_match_table[] =3D { + { .compatible =3D "qcom,sm8350-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_sm8350_match_table); + +static struct platform_driver video_cc_sm8350_driver =3D { + .probe =3D video_cc_sm8350_probe, + .driver =3D { + .name =3D "sm8350-videocc", + .of_match_table =3D video_cc_sm8350_match_table, + .pm =3D &video_cc_sm8350_pm_ops, + }, +}; + +static int __init video_cc_sm8350_init(void) +{ + return platform_driver_register(&video_cc_sm8350_driver); +} +subsys_initcall(video_cc_sm8350_init); + +static void __exit video_cc_sm8350_exit(void) +{ + platform_driver_unregister(&video_cc_sm8350_driver); +} +module_exit(video_cc_sm8350_exit); + +MODULE_DESCRIPTION("QTI SM8350 VIDEOCC Driver"); +MODULE_LICENSE("GPL"); --=20 2.40.0