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[2a02:8440:d20f:2c76:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id h23-20020aa7c957000000b005066ca60b2csm2242687edt.63.2023.04.14.09.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:13:01 -0700 (PDT) From: Guillaume Ranquet Date: Fri, 14 Apr 2023 18:07:46 +0200 Subject: [PATCH v2 1/2] phy: mediatek: hdmi: mt8195: fix uninitialized variable usage in pll_calc MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230413-fixes-for-mt8195-hdmi-phy-v2-1-bbad62e64321@baylibre.com> References: <20230413-fixes-for-mt8195-hdmi-phy-v2-0-bbad62e64321@baylibre.com> In-Reply-To: <20230413-fixes-for-mt8195-hdmi-phy-v2-0-bbad62e64321@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume Ranquet , kernel test robot X-Mailer: b4 0.13-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ret variable in mtk_hdmi_pll_calc() was used unitialized as reported by the kernel test robot. Fix the issue by removing the variable altogether and testing out the return value of mtk_hdmi_pll_set_hw() Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Reported-by: kernel test robot Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nathan Chancellor --- drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/media= tek/phy-mtk-hdmi-mt8195.c index abfc077fb0a8..054b73cb31ee 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -213,7 +213,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_= phy, struct clk_hw *hw, u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; u8 txpredivs[4] =3D { 2, 4, 6, 12 }; u32 fbkdiv_low; - int i, ret; + int i; =20 pixel_clk =3D rate; tmds_clk =3D pixel_clk; @@ -292,13 +292,9 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi= _phy, struct clk_hw *hw, if (!(digital_div <=3D 32 && digital_div >=3D 1)) return -EINVAL; =20 - mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low, + return mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low, PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv, txposdiv, digital_div); - if (ret) - return -EINVAL; - - return 0; } =20 static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw) --=20 2.40.0 From nobody Fri Sep 20 20:33:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5DE7C77B6E for ; Fri, 14 Apr 2023 16:13:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230099AbjDNQNL (ORCPT ); Fri, 14 Apr 2023 12:13:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229528AbjDNQNF (ORCPT ); Fri, 14 Apr 2023 12:13:05 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8182136 for ; Fri, 14 Apr 2023 09:13:04 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-504eac2f0b2so2896101a12.3 for ; Fri, 14 Apr 2023 09:13:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1681488783; x=1684080783; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=flkZrEmQ4lhBir76YpEsiit3KQbCll7hap6g9ky4XjY=; b=zaTmkBAJWvJky4Aq1jB49C5WY+IgRDVMOCslR69Vl6Fgr4/MRocM/kLTVgfUS8Vc9t Q5XzQKszCuzICokhmRt1Go9VJJvcH1uT6f+5rfYnMRm/VGeYBqxiP4x2NmQ1MevYDkjN Lxk0CUgrBgJbq5FMC8z4GlSzvTMMDwmIo9sndS4eHwEvB5es271P2gctIkx59RCxGrjD qQOHmZ/zRLOW555qQAT+JAPtnfGECgKfLCX77sAM0b2vkpi1jeX85CPnkPEabfcUueWU o/6fqwlu5lZhedeQOhwirSYVKUm8EFzTq31Ybde4rBY1SDN7cNyHo866FrH2kGX024ZB 3Y+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681488783; x=1684080783; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=flkZrEmQ4lhBir76YpEsiit3KQbCll7hap6g9ky4XjY=; b=kzlcmRuwnqnhE1lwSZQO1xSEVNN9IqzMNaFyv6hbNSHoZwRAilW8bU3sHkzAipaC6W D5isZInhSxUosSvsHRh6VMnH0vDCsDyVXYHSYOGIw9pZbtoNOpvet5WRAL2Z4aIF76bz rP8SO0WYrOufku6b3GQ0EicoXsY5cjpJIH9KMXSYYoLEyHTXNeuQdVN+N/aI0/F8ijq4 aclcXLBX6tIGN4a+ODmFo0ERJszlZxcJKzaZFv6FEatoMhqhrj9DGvMcOEheAxUt8gIB GyWkG1UEkUvrhea2ebIILeElYmBjFuDl0S22JSeDOK152Lh2wqqWkQm/1eFYFTJSHHi8 bwOw== X-Gm-Message-State: AAQBX9c67bx0Gl6ZkyjhNh3F2zxk0SM/OjgHWrK8ymk/dpUR1ClO+PGl 2oQpeZCPM9nV6cDaHIiZabjRig== X-Google-Smtp-Source: AKy350b2JE8Qx2Y+iWCoW/RhZBJ5V4rhMWPwFiGL7k5VHEtk/DsRY4ZLJHBMfiz8yCcBW8ZuvdtkfQ== X-Received: by 2002:aa7:d85a:0:b0:506:8e06:8b4b with SMTP id f26-20020aa7d85a000000b005068e068b4bmr290176eds.8.1681488783366; Fri, 14 Apr 2023 09:13:03 -0700 (PDT) Received: from [127.0.0.1] (2a02-8440-d20f-2c76-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:d20f:2c76:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id h23-20020aa7c957000000b005066ca60b2csm2242687edt.63.2023.04.14.09.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:13:03 -0700 (PDT) From: Guillaume Ranquet Date: Fri, 14 Apr 2023 18:07:47 +0200 Subject: [PATCH v2 2/2] phy: mediatek: hdmi: mt8195: fix wrong pll calculus MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230413-fixes-for-mt8195-hdmi-phy-v2-2-bbad62e64321@baylibre.com> References: <20230413-fixes-for-mt8195-hdmi-phy-v2-0-bbad62e64321@baylibre.com> In-Reply-To: <20230413-fixes-for-mt8195-hdmi-phy-v2-0-bbad62e64321@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume Ranquet X-Mailer: b4 0.13-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has been replaced by 'div_u64'. Fix the issue by multiplying the values in the denominator instead of dividing them. Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Guillaume Ranquet --- drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/media= tek/phy-mtk-hdmi-mt8195.c index 054b73cb31ee..caa953780bee 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -271,7 +271,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_= phy, struct clk_hw *hw, * [32,24] 9bit integer, [23,0]:24bit fraction */ pcw =3D div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, - da_hdmitx21_ref_ck / PLL_FBKDIV_HS3); + da_hdmitx21_ref_ck * PLL_FBKDIV_HS3); =20 if (pcw > GENMASK_ULL(32, 0)) return -EINVAL; @@ -288,7 +288,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_= phy, struct clk_hw *hw, posdiv2 =3D 1; =20 /* Digital clk divider, max /32 */ - digital_div =3D div_u64((u64)ns_hdmipll_ck, posdiv1 / posdiv2 / pixel_clk= ); + digital_div =3D div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); if (!(digital_div <=3D 32 && digital_div >=3D 1)) return -EINVAL; =20 --=20 2.40.0