From nobody Fri Sep 20 20:37:03 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 170B9C77B78 for ; Thu, 13 Apr 2023 12:51:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230084AbjDMMvt (ORCPT ); Thu, 13 Apr 2023 08:51:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230057AbjDMMvn (ORCPT ); Thu, 13 Apr 2023 08:51:43 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8B6CA266 for ; Thu, 13 Apr 2023 05:51:41 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id k36-20020a05600c1ca400b003f0a7c483feso1021862wms.4 for ; Thu, 13 Apr 2023 05:51:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1681390300; x=1683982300; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pfiB0dyNF5IN+dDnQ49hhgOP3vgf9O+J5xAGBbme+xg=; b=jt9lPv4lNrVGnYs0/3pm0ZbWLL22vClDmV9Mi1AjKNPGPhp2Z1qGKvnTZxfZ2IH6Va kdWB9Vni+Q2YbR5aVEZCe1q10+kzpEoLsR96keXGahTbBCxs1Gw4Rf4FvtwtSZ7HVKN3 C81hq4PEchuYqdXF9E0329vVtPniqlkTwnJJ+uxVfTuZcKBHUJIiO6LOLKb21khCxIfq KaSXyJEqR4mqIBxAuPCklrrhmsA+bnWVtMAjwFperuNLjMPZ2+tDlEdIBc5Io+l0ofVe E9obFN/51kCQ1pDsVpsDL0sTjweGDhw6VzcDBOGCHtbPxDwugox0FApsENkM9nt4vwjQ tf2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681390300; x=1683982300; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pfiB0dyNF5IN+dDnQ49hhgOP3vgf9O+J5xAGBbme+xg=; b=L9U8JWvTjfuS6DUoHaf/8Tk/mo99hSlwClu1FYICF9qVIlLAAzlRWfatm5MztFwY55 kv57CFTJobm5nwxpElAzBx7QErnQ2yZly0AcD+eGXdz+uk7aJQehrdPUUa0qSWo0LP/H UlDdcNAe//xKZYxW2I5FFrTRk2Zl8MAC3hH8c1zLRcOLy7VZEQ8+IqdKI340vgHONAXI 0lbAbySpH3u5FvXbc4NimcHOCA9l5BVSNtQVKFNO+jyQAOBO3BHKcVD8pyv+RhYZbd4i UgS7J4BMqBm3kgPQu0x1gYFMj7bbaVwXX/ptSVZs513cI1rCSODnrUbZ/BQQkCSBulIT 65wA== X-Gm-Message-State: AAQBX9d2P1UQovyMxQ7hmTbpuSU0J0xy01NAQPGMXtk2h6juoNjzeLgr eRgcVY5CbsY8pGreUn2mlxFRMg== X-Google-Smtp-Source: AKy350ZhM3KTvTuJ+Clczlm2zRYmzA4Al3yjFIK+ApB//dgCEkIZNS4r1rOYNFbWtYCj5wo3UmI1kQ== X-Received: by 2002:a7b:ca57:0:b0:3ed:4685:4618 with SMTP id m23-20020a7bca57000000b003ed46854618mr1728570wml.34.1681390300370; Thu, 13 Apr 2023 05:51:40 -0700 (PDT) Received: from [127.0.0.1] ([82.66.159.240]) by smtp.gmail.com with ESMTPSA id k17-20020a5d66d1000000b002f67e4d1c63sm156356wrw.12.2023.04.13.05.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Apr 2023 05:51:40 -0700 (PDT) From: Guillaume Ranquet Date: Thu, 13 Apr 2023 14:46:25 +0200 Subject: [PATCH 1/2] phy: mediatek: hdmi: mt8195: fix uninitialized variable usage in pll_calc MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230413-fixes-for-mt8195-hdmi-phy-v1-1-b8482458df0d@baylibre.com> References: <20230413-fixes-for-mt8195-hdmi-phy-v1-0-b8482458df0d@baylibre.com> In-Reply-To: <20230413-fixes-for-mt8195-hdmi-phy-v1-0-b8482458df0d@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume Ranquet , kernel test robot X-Mailer: b4 0.13-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ret variable in mtk_hdmi_pll_calc() was used unitialized as reported by the kernel test robot. Fix the issue by removing the variable altogether and testing out the return value of mtk_hdmi_pll_set_hw() Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Reported-by: kernel test robot Signed-off-by: Guillaume Ranquet --- drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/media= tek/phy-mtk-hdmi-mt8195.c index abfc077fb0a8..e10da6c4147e 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -213,7 +213,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_= phy, struct clk_hw *hw, u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; u8 txpredivs[4] =3D { 2, 4, 6, 12 }; u32 fbkdiv_low; - int i, ret; + int i; =20 pixel_clk =3D rate; tmds_clk =3D pixel_clk; @@ -292,10 +292,9 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi= _phy, struct clk_hw *hw, if (!(digital_div <=3D 32 && digital_div >=3D 1)) return -EINVAL; =20 - mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low, + if (mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low, PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv, - txposdiv, digital_div); - if (ret) + txposdiv, digital_div)) return -EINVAL; =20 return 0; --=20 2.39.2 From nobody Fri Sep 20 20:37:03 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CC73C77B61 for ; Thu, 13 Apr 2023 12:51:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230130AbjDMMvv (ORCPT ); Thu, 13 Apr 2023 08:51:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230063AbjDMMvp (ORCPT ); Thu, 13 Apr 2023 08:51:45 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C31ADA5E6 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230413-fixes-for-mt8195-hdmi-phy-v1-2-b8482458df0d@baylibre.com> References: <20230413-fixes-for-mt8195-hdmi-phy-v1-0-b8482458df0d@baylibre.com> In-Reply-To: <20230413-fixes-for-mt8195-hdmi-phy-v1-0-b8482458df0d@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume Ranquet X-Mailer: b4 0.13-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has been replaced by 'div_u64'. Fix the issue by multiplying the values in the denominator instead of dividing them. Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/media= tek/phy-mtk-hdmi-mt8195.c index e10da6c4147e..5e84b294a43e 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -271,7 +271,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_= phy, struct clk_hw *hw, * [32,24] 9bit integer, [23,0]:24bit fraction */ pcw =3D div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, - da_hdmitx21_ref_ck / PLL_FBKDIV_HS3); + da_hdmitx21_ref_ck * PLL_FBKDIV_HS3); =20 if (pcw > GENMASK_ULL(32, 0)) return -EINVAL; @@ -288,7 +288,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_= phy, struct clk_hw *hw, posdiv2 =3D 1; =20 /* Digital clk divider, max /32 */ - digital_div =3D div_u64((u64)ns_hdmipll_ck, posdiv1 / posdiv2 / pixel_clk= ); + digital_div =3D div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); if (!(digital_div <=3D 32 && digital_div >=3D 1)) return -EINVAL; =20 --=20 2.39.2