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(075-129-116-198.res.spectrum.com. [75.129.116.198]) by smtp.gmail.com with ESMTPSA id w24-20020a9d77d8000000b00690e990e61asm6706020otl.14.2023.04.12.11.45.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 11:45:14 -0700 (PDT) From: Brian Gerst To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , Peter Zijlstra , Ingo Molnar , Brian Gerst Subject: [PATCH v2 6/6] x86/boot: Use copied boot data in sme_enable() Date: Wed, 12 Apr 2023 14:45:02 -0400 Message-Id: <20230412184502.145289-7-brgerst@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230412184502.145289-1-brgerst@gmail.com> References: <20230412184502.145289-1-brgerst@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use the copied version instead of the original real mode data. Signed-off-by: Brian Gerst --- arch/x86/include/asm/mem_encrypt.h | 4 +-- arch/x86/kernel/head_64.S | 8 +----- arch/x86/mm/mem_encrypt_identity.c | 42 ++++++++++++++++-------------- 3 files changed, 26 insertions(+), 28 deletions(-) diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_= encrypt.h index b7126701574c..74f094eb88a6 100644 --- a/arch/x86/include/asm/mem_encrypt.h +++ b/arch/x86/include/asm/mem_encrypt.h @@ -40,7 +40,7 @@ void __init sme_early_init(void); void __init sev_setup_arch(void); =20 void __init sme_encrypt_kernel(struct boot_params *bp); -void __init sme_enable(struct boot_params *bp); +void __init sme_enable(void); =20 int __init early_set_memory_decrypted(unsigned long vaddr, unsigned long s= ize); int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long s= ize); @@ -70,7 +70,7 @@ static inline void __init sme_early_init(void) { } static inline void __init sev_setup_arch(void) { } =20 static inline void __init sme_encrypt_kernel(struct boot_params *bp) { } -static inline void __init sme_enable(struct boot_params *bp) { } +static inline void __init sme_enable(void) { } =20 static inline void sev_es_init_vc_handling(void) { } =20 diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index c7b2ef379f42..c6ea37712921 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -72,14 +72,11 @@ SYM_CODE_START_NOALIGN(startup_64) wrmsr =20 leaq _text(%rip), %rdi - pushq %rsi + /* RSI contains address of real_mode_data */ call copy_bootdata - popq %rsi =20 leaq _text(%rip), %rdi - pushq %rsi call startup_64_setup_env - popq %rsi =20 #ifdef CONFIG_AMD_MEM_ENCRYPT /* @@ -88,10 +85,7 @@ SYM_CODE_START_NOALIGN(startup_64) * which needs to be done before any CPUID instructions are executed in * subsequent code. */ - movq %rsi, %rdi - pushq %rsi call sme_enable - popq %rsi #endif =20 /* Now switch to __KERNEL_CS so IRET works reliably */ diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_i= dentity.c index c6efcf559d88..e75e4f5a8a71 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -502,8 +502,9 @@ void __init sme_encrypt_kernel(struct boot_params *bp) native_write_cr3(__native_read_cr3()); } =20 -void __init sme_enable(struct boot_params *bp) +void __init sme_enable(void) { + struct boot_params *bp; const char *cmdline_ptr, *cmdline_arg, *cmdline_on, *cmdline_off; unsigned int eax, ebx, ecx, edx; unsigned long feature_mask; @@ -513,6 +514,27 @@ void __init sme_enable(struct boot_params *bp) bool snp; u64 msr; =20 + /* + * Fixups have not been applied to phys_base yet and we're running + * identity mapped, so we must obtain the address to global data + * using rip-relative addressing. + */ + asm("lea sme_cmdline_arg(%%rip), %0" + : "=3Dr" (cmdline_arg) + : "p" (sme_cmdline_arg)); + asm("lea sme_cmdline_on(%%rip), %0" + : "=3Dr" (cmdline_on) + : "p" (sme_cmdline_on)); + asm("lea sme_cmdline_off(%%rip), %0" + : "=3Dr" (cmdline_off) + : "p" (sme_cmdline_off)); + asm("lea boot_params(%%rip), %0" + : "=3Dr" (bp) + : "m" (boot_params)); + asm("lea boot_command_line(%%rip), %0" + : "=3Dr" (cmdline_ptr) + : "p" (boot_command_line)); + snp =3D snp_init(bp); =20 /* Check for the SME/SEV support leaf */ @@ -577,29 +599,11 @@ void __init sme_enable(struct boot_params *bp) goto out; } =20 - /* - * Fixups have not been applied to phys_base yet and we're running - * identity mapped, so we must obtain the address to the SME command - * line argument data using rip-relative addressing. - */ - asm ("lea sme_cmdline_arg(%%rip), %0" - : "=3Dr" (cmdline_arg) - : "p" (sme_cmdline_arg)); - asm ("lea sme_cmdline_on(%%rip), %0" - : "=3Dr" (cmdline_on) - : "p" (sme_cmdline_on)); - asm ("lea sme_cmdline_off(%%rip), %0" - : "=3Dr" (cmdline_off) - : "p" (sme_cmdline_off)); - if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT)) active_by_default =3D true; else active_by_default =3D false; =20 - cmdline_ptr =3D (const char *)((u64)bp->hdr.cmd_line_ptr | - ((u64)bp->ext_cmd_line_ptr << 32)); - if (cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer))= < 0) return; =20 --=20 2.39.2