From nobody Sat Sep 21 00:13:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE21DC7619A for ; Wed, 12 Apr 2023 13:13:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230046AbjDLNN2 (ORCPT ); Wed, 12 Apr 2023 09:13:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230272AbjDLNNK (ORCPT ); Wed, 12 Apr 2023 09:13:10 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D19D076B8; Wed, 12 Apr 2023 06:12:42 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4B83D660326E; Wed, 12 Apr 2023 14:12:25 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1681305146; bh=nJdVU7VlnC0bQc4i84vLOllab4PclCES7DJKViJt7vE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XnzTv6u0bpKYXhvdAO5TSi0QbpIKV66dtN0ZVEIK+7pHbzA14NTV8lpAIsQnKxg+D idU2mxsP+ZLATp7v2RYBRuDQZcNTKMg6RIt3SMQ58txjvS6jznKO0YzgBGjuAtCqHy sSBzjNlq89W5Si07Bz3GsYo4aXXxzl8DDs2wbKN5aIloNwBJHMbUxxX33rZ2Vi9Ron 1YwUALMH9AUmeKoedys+2yS2f60mPF/oTRwx/nwxaXTDBIj/kVGcL7kaeHxGbDOd84 tYl1ZyGUPHhXkEFfV40VQMH1DodYMfvV2AmxcriVg6eSDDmY3j78p3RXSEykDDAZ9A yIG0VHz/KeIiA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, amergnat@baylibre.com, flora.fu@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno Subject: [PATCH v3 5/6] soc: mediatek: mtk-pmic-wrap: Add support for MT6331 w/ MT6332 companion Date: Wed, 12 Apr 2023 15:12:15 +0200 Message-Id: <20230412131216.198313-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230412131216.198313-1-angelogioacchino.delregno@collabora.com> References: <20230412131216.198313-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the MT6331 PMIC and for its companion MT6332 PMIC. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/soc/mediatek/mtk-pmic-wrap.c | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index 366e40b802e4..ceeac43f7bd1 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -170,6 +170,40 @@ static const u32 mt6323_regs[] =3D { [PWRAP_DEW_RDDMY_NO] =3D 0x01a4, }; =20 +static const u32 mt6331_regs[] =3D { + [PWRAP_DEW_DIO_EN] =3D 0x018c, + [PWRAP_DEW_READ_TEST] =3D 0x018e, + [PWRAP_DEW_WRITE_TEST] =3D 0x0190, + [PWRAP_DEW_CRC_SWRST] =3D 0x0192, + [PWRAP_DEW_CRC_EN] =3D 0x0194, + [PWRAP_DEW_CRC_VAL] =3D 0x0196, + [PWRAP_DEW_MON_GRP_SEL] =3D 0x0198, + [PWRAP_DEW_CIPHER_KEY_SEL] =3D 0x019a, + [PWRAP_DEW_CIPHER_IV_SEL] =3D 0x019c, + [PWRAP_DEW_CIPHER_EN] =3D 0x019e, + [PWRAP_DEW_CIPHER_RDY] =3D 0x01a0, + [PWRAP_DEW_CIPHER_MODE] =3D 0x01a2, + [PWRAP_DEW_CIPHER_SWRST] =3D 0x01a4, + [PWRAP_DEW_RDDMY_NO] =3D 0x01a6, +}; + +static const u32 mt6332_regs[] =3D { + [PWRAP_DEW_DIO_EN] =3D 0x80f6, + [PWRAP_DEW_READ_TEST] =3D 0x80f8, + [PWRAP_DEW_WRITE_TEST] =3D 0x80fa, + [PWRAP_DEW_CRC_SWRST] =3D 0x80fc, + [PWRAP_DEW_CRC_EN] =3D 0x80fe, + [PWRAP_DEW_CRC_VAL] =3D 0x8100, + [PWRAP_DEW_MON_GRP_SEL] =3D 0x8102, + [PWRAP_DEW_CIPHER_KEY_SEL] =3D 0x8104, + [PWRAP_DEW_CIPHER_IV_SEL] =3D 0x8106, + [PWRAP_DEW_CIPHER_EN] =3D 0x8108, + [PWRAP_DEW_CIPHER_RDY] =3D 0x810a, + [PWRAP_DEW_CIPHER_MODE] =3D 0x810c, + [PWRAP_DEW_CIPHER_SWRST] =3D 0x810e, + [PWRAP_DEW_RDDMY_NO] =3D 0x8110, +}; + static const u32 mt6351_regs[] =3D { [PWRAP_DEW_DIO_EN] =3D 0x02F2, [PWRAP_DEW_READ_TEST] =3D 0x02F4, @@ -1182,6 +1216,8 @@ static int mt8186_regs[] =3D { =20 enum pmic_type { PMIC_MT6323, + PMIC_MT6331, + PMIC_MT6332, PMIC_MT6351, PMIC_MT6357, PMIC_MT6358, @@ -2041,6 +2077,16 @@ static const struct pwrap_slv_type pmic_mt6323 =3D { PWRAP_SLV_CAP_SECURITY, }; =20 +static const struct pwrap_slv_type pmic_mt6331 =3D { + .dew_regs =3D mt6331_regs, + .type =3D PMIC_MT6331, + .comp_dew_regs =3D mt6332_regs, + .comp_type =3D PMIC_MT6332, + .regops =3D &pwrap_regops16, + .caps =3D PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | + PWRAP_SLV_CAP_SECURITY, +}; + static const struct pwrap_slv_type pmic_mt6351 =3D { .dew_regs =3D mt6351_regs, .type =3D PMIC_MT6351, @@ -2086,6 +2132,7 @@ static const struct pwrap_slv_type pmic_mt6397 =3D { =20 static const struct of_device_id of_slave_match_tbl[] =3D { { .compatible =3D "mediatek,mt6323", .data =3D &pmic_mt6323 }, + { .compatible =3D "mediatek,mt6331", .data =3D &pmic_mt6331 }, { .compatible =3D "mediatek,mt6351", .data =3D &pmic_mt6351 }, { .compatible =3D "mediatek,mt6357", .data =3D &pmic_mt6357 }, { .compatible =3D "mediatek,mt6358", .data =3D &pmic_mt6358 }, --=20 2.40.0