From nobody Fri Dec 19 20:54:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34099C77B6E for ; Wed, 12 Apr 2023 11:09:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229969AbjDLLJl (ORCPT ); Wed, 12 Apr 2023 07:09:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229917AbjDLLJb (ORCPT ); Wed, 12 Apr 2023 07:09:31 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05B8759F3; Wed, 12 Apr 2023 04:09:29 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id e22so10391649wra.6; Wed, 12 Apr 2023 04:09:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681297767; x=1683889767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v7nHC1ZoyGnBMkj9VoSQB3G3dDc74yMKyzp+x8lL8uQ=; b=YbqshfwsKjNyErx/MS3m0/eEGOfQUxhVFBfHqvf2NAUHqxyH9lx0G6hYDJaO2jmzWn +ha9/F71KHtdK1e23eCBBYfJp54/9DD9MLEpCsxedkqOADDFp/Z8rKyiAH/hj49CAB1G r/qFsgiM0hR1mdUharwka2IImp54uPgni9YmC767fwk6SSvxzYmuNBKN36ZX/zey+UhK GXxeYS8sUt1B42trqIjDatzDxbmqOfMCk8Mv2hXTaKoDfb/zA2PvMZjF2qSjUZcMcQhL w5bbR3kgb18fgvHmnfsZDNS7yVipf+IVD/WtyYP2wblUvWLzIODcube+JOOHwAITiJ/x ecvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681297767; x=1683889767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v7nHC1ZoyGnBMkj9VoSQB3G3dDc74yMKyzp+x8lL8uQ=; b=zaMzr2khwTwWUKoUr155oYqgQHkJWj3WwlL8g49pqsqvQUYLZKEvfUZDOviRUCaGHY RfoZQwSE56T3sa/coz14LHN27swK8CDQPcQNkvd4ZIAOVae2pDrizWOvGKWPH7GtMys8 e/yLXmNLk76ou+97I8bgmXZ6DNJ4cpQ7dnL4s4t79r49BUZ1QfjDHWwK2t10Ab8CewH2 xVUNbuJiYYM4TcRbxoCEu3KzMJLd6NslZ7AiutM7iz8my7/RaaGruYxPqoqH5hT0UO5t ghmkXU/MncLxDai2Wjo6ihTL2vAwtqIfBBSmfIMkJmjUNkPTQnXM50hlUFh1AHyGytPo hCOw== X-Gm-Message-State: AAQBX9cMboUpS4Ae/nFQUMjMLiEVKcu6ZDEczY+ZDOYEOZoMVlukw3T0 VC3tzVtljbhhCX59LBAiNBA= X-Google-Smtp-Source: AKy350aoGXknWeyuPSXbyZQdthar+ZVQIT0TUZxcsTGaG9Btecmwvc5yAyNXr6WU5czPvUKoGQ4Zzw== X-Received: by 2002:adf:de05:0:b0:2f0:595:679b with SMTP id b5-20020adfde05000000b002f00595679bmr1798349wrm.66.1681297767343; Wed, 12 Apr 2023 04:09:27 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:783d:9280:20c4:db22]) by smtp.gmail.com with ESMTPSA id l13-20020a5d668d000000b002e61e002943sm16863582wru.116.2023.04.12.04.09.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:09:26 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Arnd Bergmann , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-riscv@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v8 3/7] riscv: errata: Add Andes alternative ports Date: Wed, 12 Apr 2023 12:08:56 +0100 Message-Id: <20230412110900.69738-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add required ports of the Alternative scheme for Andes CPU cores. I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason cache management needs a software workaround. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley --- v7 -> v8 * Now patching the code using patch_text_nosync() and riscv_alternative_fix= _offsets() v6 -> v7 * Renamed RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND -> ANDES_SBI_EXT_IOCP_SW_WORKAR= OUND * Dropped "depends on !XIP_KERNEL" for ERRATA_ANDES config v5 -> v6 * Dropped patching alternative and now just probing IOCP v4 -> v5 * Sorted the Kconfig/Makefile/Switch based on Core name * Added a comments * Introduced RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT ID to check if CMO needs to be applied. Is there a way we can access the DTB while patch= ing as we can drop this SBI EXT ID and add a DT property instead for cmo? RFC v3 -> v4 * New patch --- arch/riscv/Kconfig.errata | 21 ++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/andes/Makefile | 1 + arch/riscv/errata/andes/errata.c | 104 +++++++++++++++++++++++++++ arch/riscv/include/asm/alternative.h | 3 + arch/riscv/include/asm/errata_list.h | 5 ++ arch/riscv/kernel/alternative.c | 5 ++ 7 files changed, 140 insertions(+) create mode 100644 arch/riscv/errata/andes/Makefile create mode 100644 arch/riscv/errata/andes/errata.c diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 0c8f4652cd82..92c779764b27 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -1,5 +1,26 @@ menu "CPU errata selection" =20 +config ERRATA_ANDES + bool "Andes AX45MP errata" + depends on RISCV_ALTERNATIVE + help + All Andes errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all Andes errata. Please say "Y" + here if your platform uses Andes CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + +config ERRATA_ANDES_CMO + bool "Apply Andes cache management errata" + depends on ERRATA_ANDES && MMU && ARCH_R9A07G043 + select RISCV_DMA_NONCOHERENT + default y + help + This will apply the cache management errata to handle the + non-standard handling on non-coherent operations on Andes cores. + + If you don't know what to do here, say "Y". + config ERRATA_SIFIVE bool "SiFive errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index a1055965fbee..6f1c693af92d 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -1,2 +1,3 @@ +obj-$(CONFIG_ERRATA_ANDES) +=3D andes/ obj-$(CONFIG_ERRATA_SIFIVE) +=3D sifive/ obj-$(CONFIG_ERRATA_THEAD) +=3D thead/ diff --git a/arch/riscv/errata/andes/Makefile b/arch/riscv/errata/andes/Mak= efile new file mode 100644 index 000000000000..2d644e19caef --- /dev/null +++ b/arch/riscv/errata/andes/Makefile @@ -0,0 +1 @@ +obj-y +=3D errata.o diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/err= ata.c new file mode 100644 index 000000000000..49315f36022e --- /dev/null +++ b/arch/riscv/errata/andes/errata.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Erratas to be applied for Andes CPU cores + * + * Copyright (C) 2023 Renesas Electronics Corporation. + * + * Author: Lad Prabhakar + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL +#define ANDESTECH_AX45MP_MIMPID 0x500UL +#define ANDESTECH_SBI_EXT_ANDES 0x0900031E + +#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1 + +static long ax45mp_iocp_sw_workaround(void) +{ + struct sbiret ret; + + /* + * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing= and + * cache is controllable only then CMO will be applied to the platform. + */ + ret =3D sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROU= ND, + 0, 0, 0, 0, 0, 0); + + return ret.error ? 0 : ret.value; +} + +static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, u= nsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO)) + return false; + + if (arch_id !=3D ANDESTECH_AX45MP_MARCHID || impid !=3D ANDESTECH_AX45MP_= MIMPID) + return false; + + if (!ax45mp_iocp_sw_workaround()) + return false; + + /* Set this just to make core cbo code happy */ + riscv_cbom_block_size =3D 1; + riscv_noncoherent_supported(); + + return true; +} + +static u32 andes_errata_probe(unsigned int stage, unsigned long archid, un= signed long impid) +{ + u32 cpu_req_errata =3D 0; + + /* + * In the absence of the I/O Coherency Port, access to certain peripherals + * requires vendor specific DMA handling. + */ + if (errata_probe_iocp(stage, archid, impid)) + cpu_req_errata |=3D BIT(ERRATA_ANDESTECH_NO_IOCP); + + return cpu_req_errata; +} + +void __init_or_module andes_errata_patch_func(struct alt_entry *begin, str= uct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage) +{ + u32 cpu_req_errata =3D andes_errata_probe(stage, archid, impid); + void *oldptr, *altptr; + struct alt_entry *alt; + u32 tmp; + + if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) + return; + + for (alt =3D begin; alt < end; alt++) { + if (alt->vendor_id !=3D ANDESTECH_VENDOR_ID) + continue; + if (alt->patch_id >=3D ERRATA_ANDESTECH_NUMBER) + continue; + + tmp =3D BIT(alt->patch_id); + if (cpu_req_errata & tmp) { + oldptr =3D ALT_OLD_PTR(alt); + altptr =3D ALT_ALT_PTR(alt); + + mutex_lock(&text_mutex); + patch_text_nosync(oldptr, altptr, alt->alt_len); + + riscv_alternative_fix_offsets(oldptr, alt->alt_len, + oldptr - altptr); + mutex_unlock(&text_mutex); + } + } +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/= alternative.h index 58ccd2f8cab7..3c2b59b25017 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -45,6 +45,9 @@ struct alt_entry { u32 patch_id; /* The patch ID (erratum ID or cpufeature ID) */ }; =20 +void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *en= d, + unsigned long archid, unsigned long impid, + unsigned int stage); void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *e= nd, unsigned long archid, unsigned long impid, unsigned int stage); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index fb1a810f3d8c..e2ecd01bfac7 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -11,6 +11,11 @@ #include #include =20 +#ifdef CONFIG_ERRATA_ANDES +#define ERRATA_ANDESTECH_NO_IOCP 0 +#define ERRATA_ANDESTECH_NUMBER 1 +#endif + #ifdef CONFIG_ERRATA_SIFIVE #define ERRATA_SIFIVE_CIP_453 0 #define ERRATA_SIFIVE_CIP_1200 1 diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternativ= e.c index 2354c69dc7d1..8a34e72c2b5e 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -42,6 +42,11 @@ static void __init_or_module riscv_fill_cpu_mfr_info(str= uct cpu_manufacturer_inf #endif =20 switch (cpu_mfr_info->vendor_id) { +#ifdef CONFIG_ERRATA_ANDES + case ANDESTECH_VENDOR_ID: + cpu_mfr_info->patch_func =3D andes_errata_patch_func; + break; +#endif #ifdef CONFIG_ERRATA_SIFIVE case SIFIVE_VENDOR_ID: cpu_mfr_info->patch_func =3D sifive_errata_patch_func; --=20 2.25.1