From nobody Mon Feb 9 16:57:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62422C77B77 for ; Wed, 12 Apr 2023 11:09:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229927AbjDLLJb (ORCPT ); Wed, 12 Apr 2023 07:09:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229765AbjDLLJ2 (ORCPT ); Wed, 12 Apr 2023 07:09:28 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83DC71BD; Wed, 12 Apr 2023 04:09:26 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id s2so7214124wra.7; Wed, 12 Apr 2023 04:09:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681297765; x=1683889765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dGO+LaGVOk29cf36FklMYJChk9NGcDDsM7QD9QuVRBA=; b=MeP2q3zHTymS32ugCSJabv9lQy4/FYzsnn7cm2pA1JzNgNltj1ed3r0YHawXaMZDT1 Orgij9HV213j7YDORZ9TfG65iZK7PyLpVFO5W3YbtyEGDaLbzyzprSrTMGS6Ns4TV0l9 t0Lcf9fOhKoOOLKlW+YNtDxCVfa1n3HYAXyuaFqzC8mdaKVlf7ajnSM+sPw34RGGTAU0 uCJ8ZXkcXKpKxIf3IQQGpu9yDpXxMzeDrx77XeXn3H0rUJPs/VXcegQhuV9vHbwVz0Bl cjvnBZCEqxSiaGNWXjW6z4alV4ec7eZTTp+9XLlxbAclyO9GS89KNilAzTG5UdFbaB49 yqSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681297765; x=1683889765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dGO+LaGVOk29cf36FklMYJChk9NGcDDsM7QD9QuVRBA=; b=yW1fE3BStBNoj+SjhgJg8X9EUptD+Cko8N/OsjuHHIisdq9lHMZaGLJ0TBoLdSNoBk rcHzw1xMh0b0Q2h9OtcyPxY3uVL460LBy7w+nbXL6J2fDBxnWhhWoDoTrm6RBMfp34P3 8dwx15ehAnu6QHQZ1UH9ZqUTNOK/VBJzW5NtJe0Fy3FbkZdm23fc0x/9w6V6ewP/QsZX ogaaVwQineZZejGhDn3cq9uGaYgFcUbpokBvAd0z5Hn0OIqZF0Tf6Oewfohp4m7vNbNV 2wktqXpfoa3D0Tg43EoWOvemuTbeeyijRDeUGTk7kANIqwAAlCjF7XqofLkf+Gwc4aog DE1g== X-Gm-Message-State: AAQBX9d4hBgQXIUzh5HBeAr4ef55XKtF9prVPLrw1jjdZpjEz3LPj/Oa w1WCT+8v3r71Tb+ZnqiZmhU= X-Google-Smtp-Source: AKy350YBc0s02ZGC8rTSixIk/cyfKzaWZdfTr03S7OWoBzyHDkdxxMY6jqIT3ULF3eRXDFBdmjSjkA== X-Received: by 2002:a5d:65cd:0:b0:2f0:2cf9:fed0 with SMTP id e13-20020a5d65cd000000b002f02cf9fed0mr6792924wrw.49.1681297764779; Wed, 12 Apr 2023 04:09:24 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:783d:9280:20c4:db22]) by smtp.gmail.com with ESMTPSA id l13-20020a5d668d000000b002e61e002943sm16863582wru.116.2023.04.12.04.09.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:09:23 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Arnd Bergmann , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-riscv@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar , Heiko Stuebner Subject: [PATCH v8 1/7] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Date: Wed, 12 Apr 2023 12:08:54 +0100 Message-Id: <20230412110900.69738-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Introduce ALTERNATIVE_3() macro. A vendor wants to replace an old_content, but another vendor has used ALTERNATIVE_2() to patch its customized content at the same location. In this case, this vendor can use macro ALTERNATIVE_3() and then replace ALTERNATIVE_2() with ALTERNATIVE_3() to append its customized content. While at it update comment above ALTERNATIVE_2() macro and make it generic so that the comment holds good for any new addition of ALTERNATIVE_X() macros. Signed-off-by: Lad Prabhakar Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley --- v5->v8 * Added RB tags from Conor and Heiko * Fixed review comments pointed by Geert and Conor v4->v5 * Rebased the patch on top of Andrew's series (now in Palmers for next-bran= ch) * Updated comment for ALTERNATIVE_x() as suggested by Heiko RFC v3 -> v4 * New patch --- arch/riscv/include/asm/alternative-macros.h | 51 +++++++++++++++++++-- 1 file changed, 46 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/inclu= de/asm/alternative-macros.h index b8c55fb3ab2c..fd5f99714f29 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -50,8 +50,17 @@ ALT_NEW_CONTENT \vendor_id_2, \patch_id_2, \enable_2, "\new_c_2" .endm =20 +.macro ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, errata_id_1, enable_= 1, \ + new_c_2, vendor_id_2, errata_id_2, enable_2, \ + new_c_3, vendor_id_3, errata_id_3, enable_3 + ALTERNATIVE_CFG_2 "\old_c", "\new_c_1", \vendor_id_1, \errata_id_1, \enab= le_1, \ + "\new_c_2", \vendor_id_2, \errata_id_2, \enable_2 + ALT_NEW_CONTENT \vendor_id_3, \errata_id_3, \enable_3, "\new_c_3" +.endm + #define __ALTERNATIVE_CFG(...) ALTERNATIVE_CFG __VA_ARGS__ #define __ALTERNATIVE_CFG_2(...) ALTERNATIVE_CFG_2 __VA_ARGS__ +#define __ALTERNATIVE_CFG_3(...) ALTERNATIVE_CFG_3 __VA_ARGS__ =20 #else /* !__ASSEMBLY__ */ =20 @@ -98,6 +107,13 @@ __ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, patch_id_1, enable_1) \ ALT_NEW_CONTENT(vendor_id_2, patch_id_2, enable_2, new_c_2) =20 +#define __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, enab= le_1, \ + new_c_2, vendor_id_2, errata_id_2, enable_2, \ + new_c_3, vendor_id_3, errata_id_3, enable_3) \ + __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \ + new_c_2, vendor_id_2, errata_id_2, enable_2) \ + ALT_NEW_CONTENT(vendor_id_3, errata_id_3, enable_3, new_c_3) + #endif /* __ASSEMBLY__ */ =20 #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, patch_id, CONFIG_k) \ @@ -108,6 +124,13 @@ __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, patch_id_1, IS_ENABLED(C= ONFIG_k_1), \ new_c_2, vendor_id_2, patch_id_2, IS_ENABLED(CONFIG_k_2)) =20 +#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, CONFI= G_k_1, \ + new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2, \ + new_c_3, vendor_id_3, errata_id_3, CONFIG_k_3) \ + __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(= CONFIG_k_1), \ + new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2), \ + new_c_3, vendor_id_3, errata_id_3, IS_ENABLED(CONFIG_k_3)) + #else /* CONFIG_RISCV_ALTERNATIVE */ #ifdef __ASSEMBLY__ =20 @@ -121,6 +144,9 @@ #define _ALTERNATIVE_CFG_2(old_c, ...) \ ALTERNATIVE_CFG old_c =20 +#define _ALTERNATIVE_CFG_3(old_c, ...) \ + ALTERNATIVE_CFG old_c + #else /* !__ASSEMBLY__ */ =20 #define __ALTERNATIVE_CFG(old_c) \ @@ -132,6 +158,9 @@ #define _ALTERNATIVE_CFG_2(old_c, ...) \ __ALTERNATIVE_CFG(old_c) =20 +#define _ALTERNATIVE_CFG_3(old_c, ...) \ + __ALTERNATIVE_CFG(old_c) + #endif /* __ASSEMBLY__ */ #endif /* CONFIG_RISCV_ALTERNATIVE */ =20 @@ -152,15 +181,27 @@ _ALTERNATIVE_CFG(old_content, new_content, vendor_id, patch_id, CONFIG_k) =20 /* - * A vendor wants to replace an old_content, but another vendor has used - * ALTERNATIVE() to patch its customized content at the same location. In - * this case, this vendor can create a new macro ALTERNATIVE_2() based - * on the following sample code and then replace ALTERNATIVE() with - * ALTERNATIVE_2() to append its customized content. + * ALTERNATIVE_x macros allow providing multiple replacement options + * for an ALTERNATIVE code section. This is helpful if multiple + * implementation variants for the same functionality. + * + * Usage: + * ALTERNATIVE_x(old_content, + * new_content1, vendor_id1, errata_id1, CONFIG_k1, + * new_content2, vendor_id2, errata_id2, CONFIG_k2, + * ... + * new_contentx, vendor_idx, errata_idx, CONFIG_kx) */ #define ALTERNATIVE_2(old_content, new_content_1, vendor_id_1, patch_id_1,= CONFIG_k_1, \ new_content_2, vendor_id_2, patch_id_2, CONFIG_k_2) \ _ALTERNATIVE_CFG_2(old_content, new_content_1, vendor_id_1, patch_id_1, C= ONFIG_k_1, \ new_content_2, vendor_id_2, patch_id_2, CONFIG_k_2) =20 +#define ALTERNATIVE_3(old_content, new_content_1, vendor_id_1, errata_id_1= , CONFIG_k_1, \ + new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2, \ + new_content_3, vendor_id_3, errata_id_3, CONFIG_k_3) \ + _ALTERNATIVE_CFG_3(old_content, new_content_1, vendor_id_1, errata_id_1, = CONFIG_k_1, \ + new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2, \ + new_content_3, vendor_id_3, errata_id_3, CONFIG_k_3) + #endif --=20 2.25.1 From nobody Mon Feb 9 16:57:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04103C77B6E for ; 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Wed, 12 Apr 2023 04:09:25 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Arnd Bergmann , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-riscv@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v8 2/7] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Date: Wed, 12 Apr 2023 12:08:55 +0100 Message-Id: <20230412110900.69738-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add Andes Technology to the vendors list. Signed-off-by: Lad Prabhakar Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- v7 -> v8 * No change v6 -> v7 * No change v5 -> v6 * No change v4 -> v5 * Included RB tags RFC v3 -> v4 * New patch --- arch/riscv/include/asm/vendorid_list.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/as= m/vendorid_list.h index cb89af3f0704..e55407ace0c3 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -5,6 +5,7 @@ #ifndef ASM_VENDOR_LIST_H #define ASM_VENDOR_LIST_H =20 +#define ANDESTECH_VENDOR_ID 0x31e #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 =20 --=20 2.25.1 From nobody Mon Feb 9 16:57:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34099C77B6E for ; Wed, 12 Apr 2023 11:09:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229969AbjDLLJl (ORCPT ); Wed, 12 Apr 2023 07:09:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229917AbjDLLJb (ORCPT ); Wed, 12 Apr 2023 07:09:31 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05B8759F3; Wed, 12 Apr 2023 04:09:29 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id e22so10391649wra.6; Wed, 12 Apr 2023 04:09:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681297767; x=1683889767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v7nHC1ZoyGnBMkj9VoSQB3G3dDc74yMKyzp+x8lL8uQ=; b=YbqshfwsKjNyErx/MS3m0/eEGOfQUxhVFBfHqvf2NAUHqxyH9lx0G6hYDJaO2jmzWn +ha9/F71KHtdK1e23eCBBYfJp54/9DD9MLEpCsxedkqOADDFp/Z8rKyiAH/hj49CAB1G r/qFsgiM0hR1mdUharwka2IImp54uPgni9YmC767fwk6SSvxzYmuNBKN36ZX/zey+UhK GXxeYS8sUt1B42trqIjDatzDxbmqOfMCk8Mv2hXTaKoDfb/zA2PvMZjF2qSjUZcMcQhL w5bbR3kgb18fgvHmnfsZDNS7yVipf+IVD/WtyYP2wblUvWLzIODcube+JOOHwAITiJ/x ecvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681297767; x=1683889767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v7nHC1ZoyGnBMkj9VoSQB3G3dDc74yMKyzp+x8lL8uQ=; b=zaMzr2khwTwWUKoUr155oYqgQHkJWj3WwlL8g49pqsqvQUYLZKEvfUZDOviRUCaGHY RfoZQwSE56T3sa/coz14LHN27swK8CDQPcQNkvd4ZIAOVae2pDrizWOvGKWPH7GtMys8 e/yLXmNLk76ou+97I8bgmXZ6DNJ4cpQ7dnL4s4t79r49BUZ1QfjDHWwK2t10Ab8CewH2 xVUNbuJiYYM4TcRbxoCEu3KzMJLd6NslZ7AiutM7iz8my7/RaaGruYxPqoqH5hT0UO5t ghmkXU/MncLxDai2Wjo6ihTL2vAwtqIfBBSmfIMkJmjUNkPTQnXM50hlUFh1AHyGytPo hCOw== X-Gm-Message-State: AAQBX9cMboUpS4Ae/nFQUMjMLiEVKcu6ZDEczY+ZDOYEOZoMVlukw3T0 VC3tzVtljbhhCX59LBAiNBA= X-Google-Smtp-Source: AKy350aoGXknWeyuPSXbyZQdthar+ZVQIT0TUZxcsTGaG9Btecmwvc5yAyNXr6WU5czPvUKoGQ4Zzw== X-Received: by 2002:adf:de05:0:b0:2f0:595:679b with SMTP id b5-20020adfde05000000b002f00595679bmr1798349wrm.66.1681297767343; Wed, 12 Apr 2023 04:09:27 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:783d:9280:20c4:db22]) by smtp.gmail.com with ESMTPSA id l13-20020a5d668d000000b002e61e002943sm16863582wru.116.2023.04.12.04.09.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:09:26 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Arnd Bergmann , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-riscv@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v8 3/7] riscv: errata: Add Andes alternative ports Date: Wed, 12 Apr 2023 12:08:56 +0100 Message-Id: <20230412110900.69738-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add required ports of the Alternative scheme for Andes CPU cores. I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason cache management needs a software workaround. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley --- v7 -> v8 * Now patching the code using patch_text_nosync() and riscv_alternative_fix= _offsets() v6 -> v7 * Renamed RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND -> ANDES_SBI_EXT_IOCP_SW_WORKAR= OUND * Dropped "depends on !XIP_KERNEL" for ERRATA_ANDES config v5 -> v6 * Dropped patching alternative and now just probing IOCP v4 -> v5 * Sorted the Kconfig/Makefile/Switch based on Core name * Added a comments * Introduced RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT ID to check if CMO needs to be applied. Is there a way we can access the DTB while patch= ing as we can drop this SBI EXT ID and add a DT property instead for cmo? RFC v3 -> v4 * New patch --- arch/riscv/Kconfig.errata | 21 ++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/andes/Makefile | 1 + arch/riscv/errata/andes/errata.c | 104 +++++++++++++++++++++++++++ arch/riscv/include/asm/alternative.h | 3 + arch/riscv/include/asm/errata_list.h | 5 ++ arch/riscv/kernel/alternative.c | 5 ++ 7 files changed, 140 insertions(+) create mode 100644 arch/riscv/errata/andes/Makefile create mode 100644 arch/riscv/errata/andes/errata.c diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 0c8f4652cd82..92c779764b27 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -1,5 +1,26 @@ menu "CPU errata selection" =20 +config ERRATA_ANDES + bool "Andes AX45MP errata" + depends on RISCV_ALTERNATIVE + help + All Andes errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all Andes errata. Please say "Y" + here if your platform uses Andes CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + +config ERRATA_ANDES_CMO + bool "Apply Andes cache management errata" + depends on ERRATA_ANDES && MMU && ARCH_R9A07G043 + select RISCV_DMA_NONCOHERENT + default y + help + This will apply the cache management errata to handle the + non-standard handling on non-coherent operations on Andes cores. + + If you don't know what to do here, say "Y". + config ERRATA_SIFIVE bool "SiFive errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index a1055965fbee..6f1c693af92d 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -1,2 +1,3 @@ +obj-$(CONFIG_ERRATA_ANDES) +=3D andes/ obj-$(CONFIG_ERRATA_SIFIVE) +=3D sifive/ obj-$(CONFIG_ERRATA_THEAD) +=3D thead/ diff --git a/arch/riscv/errata/andes/Makefile b/arch/riscv/errata/andes/Mak= efile new file mode 100644 index 000000000000..2d644e19caef --- /dev/null +++ b/arch/riscv/errata/andes/Makefile @@ -0,0 +1 @@ +obj-y +=3D errata.o diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/err= ata.c new file mode 100644 index 000000000000..49315f36022e --- /dev/null +++ b/arch/riscv/errata/andes/errata.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Erratas to be applied for Andes CPU cores + * + * Copyright (C) 2023 Renesas Electronics Corporation. + * + * Author: Lad Prabhakar + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL +#define ANDESTECH_AX45MP_MIMPID 0x500UL +#define ANDESTECH_SBI_EXT_ANDES 0x0900031E + +#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1 + +static long ax45mp_iocp_sw_workaround(void) +{ + struct sbiret ret; + + /* + * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing= and + * cache is controllable only then CMO will be applied to the platform. + */ + ret =3D sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROU= ND, + 0, 0, 0, 0, 0, 0); + + return ret.error ? 0 : ret.value; +} + +static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, u= nsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO)) + return false; + + if (arch_id !=3D ANDESTECH_AX45MP_MARCHID || impid !=3D ANDESTECH_AX45MP_= MIMPID) + return false; + + if (!ax45mp_iocp_sw_workaround()) + return false; + + /* Set this just to make core cbo code happy */ + riscv_cbom_block_size =3D 1; + riscv_noncoherent_supported(); + + return true; +} + +static u32 andes_errata_probe(unsigned int stage, unsigned long archid, un= signed long impid) +{ + u32 cpu_req_errata =3D 0; + + /* + * In the absence of the I/O Coherency Port, access to certain peripherals + * requires vendor specific DMA handling. + */ + if (errata_probe_iocp(stage, archid, impid)) + cpu_req_errata |=3D BIT(ERRATA_ANDESTECH_NO_IOCP); + + return cpu_req_errata; +} + +void __init_or_module andes_errata_patch_func(struct alt_entry *begin, str= uct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage) +{ + u32 cpu_req_errata =3D andes_errata_probe(stage, archid, impid); + void *oldptr, *altptr; + struct alt_entry *alt; + u32 tmp; + + if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) + return; + + for (alt =3D begin; alt < end; alt++) { + if (alt->vendor_id !=3D ANDESTECH_VENDOR_ID) + continue; + if (alt->patch_id >=3D ERRATA_ANDESTECH_NUMBER) + continue; + + tmp =3D BIT(alt->patch_id); + if (cpu_req_errata & tmp) { + oldptr =3D ALT_OLD_PTR(alt); + altptr =3D ALT_ALT_PTR(alt); + + mutex_lock(&text_mutex); + patch_text_nosync(oldptr, altptr, alt->alt_len); + + riscv_alternative_fix_offsets(oldptr, alt->alt_len, + oldptr - altptr); + mutex_unlock(&text_mutex); + } + } +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/= alternative.h index 58ccd2f8cab7..3c2b59b25017 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -45,6 +45,9 @@ struct alt_entry { u32 patch_id; /* The patch ID (erratum ID or cpufeature ID) */ }; =20 +void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *en= d, + unsigned long archid, unsigned long impid, + unsigned int stage); void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *e= nd, unsigned long archid, unsigned long impid, unsigned int stage); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index fb1a810f3d8c..e2ecd01bfac7 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -11,6 +11,11 @@ #include #include =20 +#ifdef CONFIG_ERRATA_ANDES +#define ERRATA_ANDESTECH_NO_IOCP 0 +#define ERRATA_ANDESTECH_NUMBER 1 +#endif + #ifdef CONFIG_ERRATA_SIFIVE #define ERRATA_SIFIVE_CIP_453 0 #define ERRATA_SIFIVE_CIP_1200 1 diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternativ= e.c index 2354c69dc7d1..8a34e72c2b5e 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -42,6 +42,11 @@ static void __init_or_module riscv_fill_cpu_mfr_info(str= uct cpu_manufacturer_inf #endif =20 switch (cpu_mfr_info->vendor_id) { +#ifdef CONFIG_ERRATA_ANDES + case ANDESTECH_VENDOR_ID: + cpu_mfr_info->patch_func =3D andes_errata_patch_func; + break; +#endif #ifdef CONFIG_ERRATA_SIFIVE case SIFIVE_VENDOR_ID: cpu_mfr_info->patch_func =3D sifive_errata_patch_func; --=20 2.25.1 From nobody Mon Feb 9 16:57:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8360FC77B71 for ; Wed, 12 Apr 2023 11:09:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230085AbjDLLJp (ORCPT ); Wed, 12 Apr 2023 07:09:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229575AbjDLLJh (ORCPT ); Wed, 12 Apr 2023 07:09:37 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 668605241; Wed, 12 Apr 2023 04:09:30 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id d9so10572086wrb.11; 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charset="utf-8" From: Lad Prabhakar Add DT binding documentation for L2 cache controller found on RZ/Five SoC. The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. The AX45MP core has an L2 cache controller, this patch describes the L2 cache block. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring Reviewed-by: Conor Dooley --- v7 -> v8 * Updated commit header message v6 -> v7 * No Change v5 -> v6 * Included RB tag from Rob v4 -> v5 * Dropped L2 cache configuration properties * Dropped PMA configuration properties * Ordered the required list to match the properties list RFC v3 -> v4 * Dropped l2 cache configuration parameters * s/larger/large * Added minItems/maxItems for andestech,pma-regions --- .../cache/andestech,ax45mp-cache.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45m= p-cache.yaml diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache= .yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml new file mode 100644 index 000000000000..9ab5f0c435d4 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andestech AX45MP L2 Cache Controller + +maintainers: + - Lad Prabhakar + +description: + A level-2 cache (L2C) is used to improve the system performance by provi= ding + a large amount of cache line entries and reasonable access delays. The L= 2C + is shared between cores, and a non-inclusive non-exclusive policy is use= d. + +select: + properties: + compatible: + contains: + enum: + - andestech,ax45mp-cache + + required: + - compatible + +properties: + compatible: + items: + - const: andestech,ax45mp-cache + - const: cache + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cache-line-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + enum: [131072, 262144, 524288, 1048576, 2097152] + + cache-unified: true + + next-level-cache: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - cache-line-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +examples: + - | + #include + + cache-controller@2010000 { + compatible =3D "andestech,ax45mp-cache", "cache"; + reg =3D <0x13400000 0x100000>; + interrupts =3D <508 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1024>; + cache-size =3D <262144>; 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Wed, 12 Apr 2023 04:09:30 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:783d:9280:20c4:db22]) by smtp.gmail.com with ESMTPSA id l13-20020a5d668d000000b002e61e002943sm16863582wru.116.2023.04.12.04.09.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:09:29 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Arnd Bergmann , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-riscv@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v8 5/7] cache: Add L2 cache management for Andes AX45MP RISC-V core Date: Wed, 12 Apr 2023 12:08:58 +0100 Message-Id: <20230412110900.69738-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason IP blocks using DMA will fail. The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. Below are the memory attributes supported: * Device, Non-bufferable * Device, bufferable * Memory, Non-cacheable, Non-bufferable * Memory, Non-cacheable, Bufferable * Memory, Write-back, No-allocate * Memory, Write-back, Read-allocate * Memory, Write-back, Write-allocate * Memory, Write-back, Read and Write-allocate More info about PMA (section 10.3): Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Data= sheet.pdf As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. Example PMA region passes as a DT node from OpenSBI: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; pma_resv0@58000000 { compatible =3D "shared-dma-pool"; reg =3D <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley --- v7 -> v8 * Dropped function pointer usage * Now exporting the functions for clean/inval/flush * Switched to using early_initcall instead of arch_initcall * Dropped entry for "include/cache" from MAINTAINERS * Dropped dependency of RISCV on AX45MP_L2_CACHE * Returning error in case of cache line mismatch * Renamed clean/inval/flush functions v6 -> v7 * Implemented flush callback * Dropped using riscv_dma_noncoherent_cmo_ops v5 -> v6 * Moved driver to cache folder * Switched to new API for CMO v4 -> v5 * Dropped code for configuring L2 cache * Dropped code for configuring PMA * Updated commit message * Added comments * Changed static branch enable/disable order RFC v3 -> v4 * Made use of runtime patching instead of compile time * Now just exposing single function ax45mp_no_iocp_cmo() for CMO handling * Added a check to make sure cache line size is always 64 bytes * Renamed folder rzf -> rzfive * Improved Kconfig description * Dropped L2 cache configuration * Dropped unnecessary casts * Fixed comments pointed by Geert. --- MAINTAINERS | 7 ++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/cache/Kconfig | 10 ++ drivers/cache/Makefile | 3 + drivers/cache/ax45mp_cache.c | 222 +++++++++++++++++++++++++++++++++++ 6 files changed, 245 insertions(+) create mode 100644 drivers/cache/Kconfig create mode 100644 drivers/cache/Makefile create mode 100644 drivers/cache/ax45mp_cache.c diff --git a/MAINTAINERS b/MAINTAINERS index 3afd45f71043..9afd39a23524 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19898,6 +19898,13 @@ S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git F: drivers/staging/ =20 +STANDALONE CACHE CONTROLLER DRIVERS +M: Conor Dooley +L: linux-riscv@lists.infradead.org +S: Maintained +T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +F: drivers/cache + STARFIRE/DURALAN NETWORK DRIVER M: Ion Badulescu S: Odd Fixes diff --git a/drivers/Kconfig b/drivers/Kconfig index 968bd0a6fd78..44abd2cba3a3 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -15,6 +15,8 @@ source "drivers/base/Kconfig" =20 source "drivers/bus/Kconfig" =20 +source "drivers/cache/Kconfig" + source "drivers/connector/Kconfig" =20 source "drivers/firmware/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 20b118dca999..db5a8115093f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -11,6 +11,7 @@ ifdef building_out_of_srctree MAKEFLAGS +=3D --include-dir=3D$(srctree) endif =20 +obj-y +=3D cache/ obj-y +=3D irqchip/ obj-y +=3D bus/ =20 diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig new file mode 100644 index 000000000000..b97269cbd149 --- /dev/null +++ b/drivers/cache/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +menu "Cache Drivers" + +config AX45MP_L2_CACHE + bool "Andes Technology AX45MP L2 Cache controller" + depends on RISCV_DMA_NONCOHERENT + help + Support for the L2 cache controller on Andes Technology AX45MP platform= s. + +endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile new file mode 100644 index 000000000000..2012e7fb978d --- /dev/null +++ b/drivers/cache/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_AX45MP_L2_CACHE) +=3D ax45mp_cache.o diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c new file mode 100644 index 000000000000..cfc40b967c55 --- /dev/null +++ b/drivers/cache/ax45mp_cache.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * non-coherent cache functions for Andes AX45MP + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include + +/* L2 cache registers */ +#define AX45MP_L2C_REG_CTL_OFFSET 0x8 + +#define AX45MP_L2C_REG_C0_CMD_OFFSET 0x40 +#define AX45MP_L2C_REG_C0_ACC_OFFSET 0x48 +#define AX45MP_L2C_REG_STATUS_OFFSET 0x80 + +/* D-cache operation */ +#define AX45MP_CCTL_L1D_VA_INVAL 0 /* Invalidate an L1 cache entry */ +#define AX45MP_CCTL_L1D_VA_WB 1 /* Write-back an L1 cache entry */ + +/* L2 CCTL status */ +#define AX45MP_CCTL_L2_STATUS_IDLE 0 + +/* L2 CCTL status cores mask */ +#define AX45MP_CCTL_L2_STATUS_C0_MASK 0xf + +/* L2 cache operation */ +#define AX45MP_CCTL_L2_PA_INVAL 0x8 /* Invalidate an L2 cache entry */ +#define AX45MP_CCTL_L2_PA_WB 0x9 /* Write-back an L2 cache entry */ + +#define AX45MP_L2C_REG_PER_CORE_OFFSET 0x10 +#define AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET 4 + +#define AX45MP_L2C_REG_CN_CMD_OFFSET(n) \ + (AX45MP_L2C_REG_C0_CMD_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET)) +#define AX45MP_L2C_REG_CN_ACC_OFFSET(n) \ + (AX45MP_L2C_REG_C0_ACC_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET)) +#define AX45MP_CCTL_L2_STATUS_CN_MASK(n) \ + (AX45MP_CCTL_L2_STATUS_C0_MASK << ((n) * AX45MP_CCTL_L2_STATUS_PER_CORE_O= FFSET)) + +#define AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM 0x80b +#define AX45MP_CCTL_REG_UCCTLCOMMAND_NUM 0x80c + +#define AX45MP_CACHE_LINE_SIZE 64 + +struct ax45mp_priv { + void __iomem *l2c_base; + u32 ax45mp_cache_line_size; +}; + +static struct ax45mp_priv ax45mp_priv; + +/* L2 Cache operations */ +static inline uint32_t ax45mp_cpu_l2c_get_cctl_status(void) +{ + return readl(ax45mp_priv.l2c_base + AX45MP_L2C_REG_STATUS_OFFSET); +} + +static void ax45mp_cpu_cache_operation(unsigned long start, unsigned long = end, + unsigned long line_size, unsigned int l1_op, + unsigned int l2_op) +{ + void __iomem *base =3D ax45mp_priv.l2c_base; + int mhartid =3D smp_processor_id(); + unsigned long pa; + + while (end > start) { + csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start); + csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, l1_op); + + pa =3D virt_to_phys((void *)start); + writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid)); + writel(l2_op, base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid)); + while ((ax45mp_cpu_l2c_get_cctl_status() & + AX45MP_CCTL_L2_STATUS_CN_MASK(mhartid)) !=3D + AX45MP_CCTL_L2_STATUS_IDLE) + ; + + start +=3D line_size; + } +} + +/* Write-back L1 and L2 cache entry */ +static inline void ax45mp_cpu_dcache_wb_range(unsigned long start, unsigne= d long end, + unsigned long line_size) +{ + ax45mp_cpu_cache_operation(start, end, line_size, + AX45MP_CCTL_L1D_VA_WB, + AX45MP_CCTL_L2_PA_WB); +} + +/* Invalidate the L1 and L2 cache entry */ +static inline void ax45mp_cpu_dcache_inval_range(unsigned long start, unsi= gned long end, + unsigned long line_size) +{ + ax45mp_cpu_cache_operation(start, end, line_size, + AX45MP_CCTL_L1D_VA_INVAL, + AX45MP_CCTL_L2_PA_INVAL); +} + +void ax45mp_dma_cache_inv(void *vaddr, unsigned long size) +{ + unsigned long start =3D (unsigned long)vaddr; + char cache_buf[2][AX45MP_CACHE_LINE_SIZE]; + unsigned long end =3D start + size; + unsigned long old_start =3D start; + unsigned long old_end =3D end; + unsigned long line_size; + unsigned long flags; + + if (unlikely(start =3D=3D end)) + return; + + line_size =3D ax45mp_priv.ax45mp_cache_line_size; + + memset(&cache_buf, 0x0, sizeof(cache_buf)); + start =3D start & (~(line_size - 1)); + end =3D ((end + line_size - 1) & (~(line_size - 1))); + + local_irq_save(flags); + if (unlikely(start !=3D old_start)) + memcpy(&cache_buf[0][0], (void *)start, line_size); + + if (unlikely(end !=3D old_end)) + memcpy(&cache_buf[1][0], (void *)(old_end & (~(line_size - 1))), line_si= ze); + + ax45mp_cpu_dcache_inval_range(start, end, line_size); + + if (unlikely(start !=3D old_start)) + memcpy((void *)start, &cache_buf[0][0], (old_start & (line_size - 1))); + + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ax45mp_dma_cache_inv); + +void ax45mp_dma_cache_wback(void *vaddr, unsigned long size) +{ + unsigned long start =3D (unsigned long)vaddr; + unsigned long end =3D start + size; + unsigned long line_size; + unsigned long flags; + + line_size =3D ax45mp_priv.ax45mp_cache_line_size; + start =3D start & (~(line_size - 1)); + local_irq_save(flags); + ax45mp_cpu_dcache_wb_range(start, end, line_size); + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ax45mp_dma_cache_wback); + +void ax45mp_dma_cache_wback_inv(void *vaddr, unsigned long size) +{ + ax45mp_dma_cache_wback(vaddr, size); + ax45mp_dma_cache_inv(vaddr, size); +} +EXPORT_SYMBOL_GPL(ax45mp_dma_cache_wback_inv); + +static int ax45mp_get_l2_line_size(struct device_node *np) +{ + int ret; + + ret =3D of_property_read_u32(np, "cache-line-size", &ax45mp_priv.ax45mp_c= ache_line_size); + if (ret) { + pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n"); + return ret; + } + + if (ax45mp_priv.ax45mp_cache_line_size !=3D AX45MP_CACHE_LINE_SIZE) { + pr_err("Expected cache-line-size to be 64 bytes (found:%u)\n", + ax45mp_priv.ax45mp_cache_line_size); + return ret; + } + + return 0; +} + +static const struct of_device_id ax45mp_cache_ids[] =3D { + { .compatible =3D "andestech,ax45mp-cache" }, + { /* sentinel */ } +}; + +static int __init ax45mp_cache_init(void) +{ + struct device_node *np; + struct resource res; + int ret; + + np =3D of_find_matching_node(NULL, ax45mp_cache_ids); + if (!of_device_is_available(np)) + return -ENODEV; + + ret =3D of_address_to_resource(np, 0, &res); + if (ret) + return ret; + + /* + * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size + * will be 0 for sure, so we can definitely rely on it. If + * riscv_cbom_block_size =3D 0 we don't need to handle CMO using SW any + * more so we just return success here and only if its being set we + * continue further in the probe path. + */ + if (!riscv_cbom_block_size) + return 0; + + ax45mp_priv.l2c_base =3D ioremap(res.start, resource_size(&res)); + if (!ax45mp_priv.l2c_base) + return -ENOMEM; + + ret =3D ax45mp_get_l2_line_size(np); + if (ret) { + iounmap(ax45mp_priv.l2c_base); + return ret; + } + + return 0; +} +early_initcall(ax45mp_cache_init); --=20 2.25.1 From nobody Mon Feb 9 16:57:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A9FCC77B71 for ; Wed, 12 Apr 2023 11:14:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229990AbjDLLOv (ORCPT ); Wed, 12 Apr 2023 07:14:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229945AbjDLLJi (ORCPT ); Wed, 12 Apr 2023 07:09:38 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F186E6E9A; Wed, 12 Apr 2023 04:09:32 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id g5so13867310wrb.5; Wed, 12 Apr 2023 04:09:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681297771; x=1683889771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nB3sPVEcrgu6W+ilG7iG45RRlHi0fVznqs8qRjeeZzA=; b=nG67AZDgYKdJnkqDzdBqL7IETA6Nq75bT/jKzTrBr0Rp8gJDxALJsSSAbhwkH/+mr9 C/UfJ9aEvNz4Bic4fi+Xz/nZH+6/rajKZuQEo+934ySYt/Hp/pM01sfrd/ejBeb2Zaej efWKvkx2OjdciaTTIaH+ZZ3bXbg1tZXeFUHsjjzxl+xkbVLf50bDYx6BVlj+qQTuFoeW lnG20h5N1VxrmIWlhuMB3EWvjzlhsEd4SrQp9fqEW5Dx4JIShONrkjvt+HsnXu3zMRZJ KoLA912TXPOJL/D5SB/8G6IZcLcRC8q4KH+W9Jl845Hwba5FVro/vgPciPrNMkXfCfYb 6B0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681297771; x=1683889771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nB3sPVEcrgu6W+ilG7iG45RRlHi0fVznqs8qRjeeZzA=; b=wjWkDhcFoxfoveALMLII2cE3LRA9idgzhVgOITYlgnrzfLyIjjmFkVgzBbckFCD9YC 1kY45tltYO6esaW6DoczlojrQIJ5yszCuGe+MWceV1AWYFc1IOPVAMg3n/10mgLN9w8j B1ifHDHDv3mjzaOgc9iQ/CQvsffO3wO7YH07eZShNSZ60DL9cY6sjDIzVqCMKVK44nmS aQ+ozXmPISo/PjHCqAIWNEQ/cyjQwfmMjkgnMS1nK04HsyCtl1EpMjMfZl+RajN1RQYW yC5tYoTNPL/H0RjoGTpBkn75YQkpotti638WeLKuMDbRMSsTFNYAYcBBsQy+WVx769Jb DiXg== X-Gm-Message-State: AAQBX9cjS+EFac4ypli7rt4r5jM9b9kGIothMQMBOz6f8WAr2YvOVVDb 9ClEzc/8flOvcRcvVyK77ds= X-Google-Smtp-Source: AKy350baFT53FrVZDDIYkVxi/WMtlVuaA05Nl+WNWc4qmRoasQeQvrWT71zHJavpnqvcSwx3li5Y1w== X-Received: by 2002:a5d:6189:0:b0:2ce:9d06:58c6 with SMTP id j9-20020a5d6189000000b002ce9d0658c6mr1637641wru.53.1681297771385; Wed, 12 Apr 2023 04:09:31 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:783d:9280:20c4:db22]) by smtp.gmail.com with ESMTPSA id l13-20020a5d668d000000b002e61e002943sm16863582wru.116.2023.04.12.04.09.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:09:30 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Arnd Bergmann , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-riscv@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v8 6/7] riscv: errata: Hookup the Andes AX45MP non-coherent handling Date: Wed, 12 Apr 2023 12:08:59 +0100 Message-Id: <20230412110900.69738-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Hookup the Andes AX45MP non-coherent handling by updating the ALT_CMO_OP() macro which will be used by dma-noncoherent.c for non-coherent platforms. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley --- v7->v8 * New patch --- arch/riscv/include/asm/cacheflush.h | 9 ++++++++ arch/riscv/include/asm/errata_list.h | 33 ++++++++++++++++++++++------ 2 files changed, 35 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/c= acheflush.h index 8091b8bf4883..a8503cc04fdb 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -59,6 +59,15 @@ void riscv_noncoherent_supported(void); static inline void riscv_noncoherent_supported(void) {} #endif =20 +#ifdef CONFIG_AX45MP_L2_CACHE +extern asmlinkage void ax45mp_dma_cache_wback_inv(void *vaddr, unsigned lo= ng size); +extern asmlinkage void ax45mp_dma_cache_wback(void *vaddr, unsigned long s= ize); +extern asmlinkage void ax45mp_dma_cache_inv(void *vaddr, unsigned long siz= e); +#else +static inline void ax45mp_dma_cache_wback_inv(void *vaddr, unsigned long s= ize) {} +static inline void ax45mp_dma_cache_wback(void *vaddr, unsigned long size)= {} +static inline void ax45mp_dma_cache_inv(void *vaddr, unsigned long size) {} +#endif /* * Bits in sys_riscv_flush_icache()'s flags argument. */ diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index e2ecd01bfac7..8e9811c14ba3 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -122,9 +122,13 @@ asm volatile(ALTERNATIVE( \ #define THEAD_flush_A0 ".long 0x0275000b" #define THEAD_SYNC_S ".long 0x0190000b" =20 +#define ANDESTECH_AX45MP_clean "call ax45mp_dma_cache_wback" +#define ANDESTECH_AX45MP_inval "call ax45mp_dma_cache_inv" +#define ANDESTECH_AX45MP_flush "call ax45mp_dma_cache_wback_inv" + #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ -asm volatile(ALTERNATIVE_2( \ - __nops(6), \ +asm volatile(ALTERNATIVE_3( \ + __nops(11), \ "mv a0, %1\n\t" \ "j 2f\n\t" \ "3:\n\t" \ @@ -132,7 +136,7 @@ asm volatile(ALTERNATIVE_2( \ "add a0, a0, %0\n\t" \ "2:\n\t" \ "bltu a0, %2, 3b\n\t" \ - "nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ + __nops(6), 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ "mv a0, %1\n\t" \ "j 2f\n\t" \ "3:\n\t" \ @@ -140,12 +144,27 @@ asm volatile(ALTERNATIVE_2( \ "add a0, a0, %0\n\t" \ "2:\n\t" \ "bltu a0, %2, 3b\n\t" \ - THEAD_SYNC_S, THEAD_VENDOR_ID, \ - ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ + THEAD_SYNC_S "\n\t" \ + __nops(5), THEAD_VENDOR_ID, \ + ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO, \ + "addi sp,sp,-16\n\t" \ + "sd s0,0(sp)\n\t" \ + "sd ra,8(sp)\n\t" \ + "addi s0,sp,16\n\t" \ + "mv a1,%4\n\t" \ + "mv a0,%3\n\t" \ + ANDESTECH_AX45MP_##_op "\n\t" \ + "ld ra,8(sp)\n\t" \ + "ld s0,0(sp)\n\t" \ + "addi sp,sp,16\n\t", \ + ANDESTECH_VENDOR_ID, ERRATA_ANDESTECH_NO_IOCP, \ + CONFIG_ERRATA_ANDES) \ : : "r"(_cachesize), \ "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ - "r"((unsigned long)(_start) + (_size)) \ - : "a0") + "r"((unsigned long)(_start) + (_size)), \ + "r"((void *)(_start)), \ + "r"((unsigned long)(_size)) \ + : "a0", "a1") =20 #define THEAD_C9XX_RV_IRQ_PMU 17 #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 --=20 2.25.1 From nobody Mon Feb 9 16:57:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7090C7619A for ; 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Wed, 12 Apr 2023 04:09:32 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Arnd Bergmann , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-riscv@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v8 7/7] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Date: Wed, 12 Apr 2023 12:09:00 +0100 Message-Id: <20230412110900.69738-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Explicitly select the required Cache management and Errata configs required for the RZ/Five SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Acked-by: Geert Uytterhoeven --- v7->v8 * Included RB tag from Geert v6->v7 * Included RB tag from Conor v5->v6 * New patch --- drivers/soc/renesas/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index de31589ed054..67604f24973e 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -334,6 +334,10 @@ if RISCV config ARCH_R9A07G043 bool "RISC-V Platform support for RZ/Five" select ARCH_RZG2L + select AX45MP_L2_CACHE + select DMA_GLOBAL_POOL + select ERRATA_ANDES + select ERRATA_ANDES_CMO help This enables support for the Renesas RZ/Five SoC. =20 --=20 2.25.1