From nobody Wed Feb 11 21:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5D6AC77B77 for ; Wed, 12 Apr 2023 08:51:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231352AbjDLIvC (ORCPT ); Wed, 12 Apr 2023 04:51:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231356AbjDLIuy (ORCPT ); Wed, 12 Apr 2023 04:50:54 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02C089746; Wed, 12 Apr 2023 01:50:38 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33C8nbgf024977; Wed, 12 Apr 2023 03:49:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681289377; bh=jbvGTc2zQFGXJn4sFTD++tPXW6H86WKnMQp0kwWWGkY=; h=From:To:CC:Subject:Date; b=MAdTE5VhAzc1HAnR7FtS4/v5Y6Uc75HNToRQTJsbnxjGnrHmdj33119LEv2Valk45 Vkezo+ns1FtWqUl4h/EfBD3zqSBVjmzbgfr/937wp1IvFRdgzSZ/yiRfc5Q8XFWxp/ aoKqZRqfEq24pyfVbggJQeEucV8YLjPgqYwV4jvQ= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33C8nbRP004958 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 12 Apr 2023 03:49:37 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 12 Apr 2023 03:49:37 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 12 Apr 2023 03:49:37 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33C8naHk118305; Wed, 12 Apr 2023 03:49:36 -0500 From: Bhavya Kapoor To: , CC: , , , , , , , Subject: [PATCH] arm64: dts: ti: k3-j721s2: Add support for CAN instances 3 and 5 in main domain Date: Wed, 12 Apr 2023 14:19:35 +0530 Message-ID: <20230412084935.699791-1-b-kapoor@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CAN instances 3 and 5 in the main domain are brought on the common processor board through header J27 and J28. The CAN High and Low lines from the SoC are routed through a mux on the SoM. The select lines need to be set for the CAN signals to get connected to the transceivers on the common processor board. Threfore, add respective mux, transceiver dt nodes to add support for these CAN instances. Signed-off-by: Bhavya Kapoor --- .../dts/ti/k3-j721s2-common-proc-board.dts | 46 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 12 +++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a7aa6cf08acd..f07663bbea16 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -27,6 +27,8 @@ aliases { can0 =3D &main_mcan16; can1 =3D &mcu_mcan0; can2 =3D &mcu_mcan1; + can3 =3D &main_mcan3; + can4 =3D &main_mcan5; }; =20 evm_12v0: fixedregulator-evm12v0 { @@ -107,6 +109,22 @@ transceiver2: can-phy2 { standby-gpios =3D <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; }; =20 + transceiver3: can-phy3 { + compatible =3D "ti,tcan1043"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + standby-gpios =3D <&exp2 7 GPIO_ACTIVE_LOW>; + enable-gpios =3D <&exp2 6 GPIO_ACTIVE_HIGH>; + mux-states =3D <&mux0 1>; + }; + + transceiver4: can-phy4 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + standby-gpios =3D <&exp_som 7 GPIO_ACTIVE_HIGH>; + mux-states =3D <&mux1 1>; + }; }; =20 &main_pmx0 { @@ -144,6 +162,20 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_mcan3_pins_default: main-mcan3-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */ + J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */ + >; + }; + + main_mcan5_pins_default: main-mcan5-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */ + J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ + >; + }; }; =20 &wkup_pmx0 { @@ -309,3 +341,17 @@ &mcu_mcan1 { pinctrl-0 =3D <&mcu_mcan1_pins_default>; phys =3D <&transceiver2>; }; + +&main_mcan3 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan3_pins_default>; + phys =3D <&transceiver3>; +}; + +&main_mcan5 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan5_pins_default>; + phys =3D <&transceiver4>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index 6930efff8a5a..0b9926a64382 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -31,6 +31,18 @@ secure_ddr: optee@9e800000 { }; }; =20 + mux0: mux-controller0 { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp_som 1 GPIO_ACTIVE_HIGH>; + }; + + mux1: mux-controller1 { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp_som 2 GPIO_ACTIVE_HIGH>; + }; + transceiver0: can-phy0 { /* standby pin has been grounded by default */ compatible =3D "ti,tcan1042"; --=20 2.34.1