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[104.53.165.62]) by smtp.gmail.com with ESMTPSA id a6-20020a056808120600b003874631e249sm5976710oil.36.2023.04.11.13.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 13:20:28 -0700 (PDT) From: Andrew Halaney To: linux-kernel@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, bmasney@redhat.com, echanude@redhat.com, ncai@quicinc.com, jsuraj@qti.qualcomm.com, hisunil@quicinc.com, Andrew Halaney Subject: [PATCH v4 1/3] clk: qcom: gcc-sc8280xp: Add EMAC GDSCs Date: Tue, 11 Apr 2023 15:20:07 -0500 Message-Id: <20230411202009.460650-2-ahalaney@redhat.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411202009.460650-1-ahalaney@redhat.com> References: <20230411202009.460650-1-ahalaney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the EMAC GDSCs to allow the EMAC hardware to be enabled. Acked-by: Stephen Boyd Reviewed-by: Konrad Dybcio Signed-off-by: Andrew Halaney Tested-by: Brian Masney --- Changes since v3: * None Changes since v2: * Add Konrad's Reviewed-by Changes since v1: * Add Stephen's Acked-by * Explicitly tested on x13s laptop with no noticeable side effect (Konr= ad) drivers/clk/qcom/gcc-sc8280xp.c | 18 ++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc8280xp.h | 2 ++ 2 files changed, 20 insertions(+) diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280x= p.c index b3198784e1c3..04a99dbaa57e 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -6873,6 +6873,22 @@ static struct gdsc usb30_sec_gdsc =3D { .pwrsts =3D PWRSTS_RET_ON, }; =20 +static struct gdsc emac_0_gdsc =3D { + .gdscr =3D 0xaa004, + .pd =3D { + .name =3D "emac_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc emac_1_gdsc =3D { + .gdscr =3D 0xba004, + .pd =3D { + .name =3D "emac_1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_sc8280xp_clocks[] =3D { [GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK] =3D &gcc_aggre_noc_pcie0_tunnel_axi_= clk.clkr, [GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK] =3D &gcc_aggre_noc_pcie1_tunnel_axi_= clk.clkr, @@ -7351,6 +7367,8 @@ static struct gdsc *gcc_sc8280xp_gdscs[] =3D { [USB30_MP_GDSC] =3D &usb30_mp_gdsc, [USB30_PRIM_GDSC] =3D &usb30_prim_gdsc, [USB30_SEC_GDSC] =3D &usb30_sec_gdsc, + [EMAC_0_GDSC] =3D &emac_0_gdsc, + [EMAC_1_GDSC] =3D &emac_1_gdsc, }; =20 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] =3D { diff --git a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h b/include/dt-bin= dings/clock/qcom,gcc-sc8280xp.h index cb2fb638825c..721105ea4fad 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h @@ -492,5 +492,7 @@ #define USB30_MP_GDSC 9 #define USB30_PRIM_GDSC 10 #define USB30_SEC_GDSC 11 +#define EMAC_0_GDSC 12 +#define EMAC_1_GDSC 13 =20 #endif --=20 2.39.2 From nobody Wed Feb 11 20:02:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1AECC76196 for ; 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[104.53.165.62]) by smtp.gmail.com with ESMTPSA id a6-20020a056808120600b003874631e249sm5976710oil.36.2023.04.11.13.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 13:20:33 -0700 (PDT) From: Andrew Halaney To: linux-kernel@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, bmasney@redhat.com, echanude@redhat.com, ncai@quicinc.com, jsuraj@qti.qualcomm.com, hisunil@quicinc.com, Andrew Halaney Subject: [PATCH v4 2/3] arm64: dts: qcom: sc8280xp: Add ethernet nodes Date: Tue, 11 Apr 2023 15:20:08 -0500 Message-Id: <20230411202009.460650-3-ahalaney@redhat.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411202009.460650-1-ahalaney@redhat.com> References: <20230411202009.460650-1-ahalaney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This platform has 2 MACs integrated in it, go ahead and describe them. Reviewed-by: Konrad Dybcio Signed-off-by: Andrew Halaney Tested-by: Brian Masney --- Changes since v3: * Order soc node via unit address (Konrad) * Add Reviewed-by (Konrad) Changes since v2: * Fix spacing (Konrad) Changes since v1: * None arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 59 ++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 42bfa9fa5b96..fdac7f0b05ee 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -761,6 +761,35 @@ soc: soc@0 { ranges =3D <0 0 0 0 0x10 0>; dma-ranges =3D <0 0 0 0 0x10 0>; =20 + ethernet0: ethernet@20000 { + compatible =3D "qcom,sc8280xp-ethqos"; + reg =3D <0x0 0x00020000 0x0 0x10000>, + <0x0 0x00036000 0x0 0x100>; + reg-names =3D "stmmaceth", "rgmii"; + + clocks =3D <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_SLV_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_RGMII_CLK>; + clock-names =3D "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts =3D , + ; + interrupt-names =3D "macirq", "eth_lpi"; + iommus =3D <&apps_smmu 0x4c0 0xf>; + power-domains =3D <&gcc EMAC_0_GDSC>; + + snps,tso; + snps,pbl =3D <32>; + rx-fifo-depth =3D <4096>; + tx-fifo-depth =3D <4096>; + + status =3D "disabled"; + }; + gcc: clock-controller@100000 { compatible =3D "qcom,gcc-sc8280xp"; reg =3D <0x0 0x00100000 0x0 0x1f0000>; @@ -4681,6 +4710,36 @@ dispcc1: clock-controller@22100000 { =20 status =3D "disabled"; }; + + ethernet1: ethernet@23000000 { + compatible =3D "qcom,sc8280xp-ethqos"; + reg =3D <0x0 0x23000000 0x0 0x10000>, + <0x0 0x23016000 0x0 0x100>; + reg-names =3D "stmmaceth", "rgmii"; + + clocks =3D <&gcc GCC_EMAC1_AXI_CLK>, + <&gcc GCC_EMAC1_SLV_AHB_CLK>, + <&gcc GCC_EMAC1_PTP_CLK>, + <&gcc GCC_EMAC1_RGMII_CLK>; + clock-names =3D "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts =3D , + ; + interrupt-names =3D "macirq", "eth_lpi"; + + iommus =3D <&apps_smmu 0x40 0xf>; + power-domains =3D <&gcc EMAC_1_GDSC>; + + snps,tso; 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[104.53.165.62]) by smtp.gmail.com with ESMTPSA id a6-20020a056808120600b003874631e249sm5976710oil.36.2023.04.11.13.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 13:20:36 -0700 (PDT) From: Andrew Halaney To: linux-kernel@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, bmasney@redhat.com, echanude@redhat.com, ncai@quicinc.com, jsuraj@qti.qualcomm.com, hisunil@quicinc.com, Andrew Halaney Subject: [PATCH v4 3/3] arm64: dts: qcom: sa8540p-ride: Add ethernet nodes Date: Tue, 11 Apr 2023 15:20:09 -0500 Message-Id: <20230411202009.460650-4-ahalaney@redhat.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411202009.460650-1-ahalaney@redhat.com> References: <20230411202009.460650-1-ahalaney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable both the MACs found on the board. ethernet0 and ethernet1 both ultimately go to a series of on board switches which aren't managed by this processor. ethernet0 is connected to a Marvell 88EA1512 phy via RGMII. That goes to the series of switches via SGMII on the "media" side of the phy. RGMII_SGMII mode is enabled via devicetree register descriptions. The switch on the "media" side has auto-negotiation disabled, so configuration from userspace similar to: ethtool -s eth0 autoneg off speed 1000 duplex full is necessary to get traffic flowing on that interface. ethernet1 is in a mac2mac/fixed-link configuration going to the same series of switches directly via RGMII. Signed-off-by: Andrew Halaney Tested-by: Brian Masney --- Changes since v3: * Compatible goes first in node (Krzysztof) Changes since v1 and v2: * None arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 180 ++++++++++++++++++++++ 1 file changed, 180 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8540p-ride.dts index 40db5aa0803c..caad955969bc 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -28,6 +28,65 @@ aliases { chosen { stdout-path =3D "serial0:115200n8"; }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; }; =20 &apps_rsc { @@ -151,6 +210,67 @@ vreg_l8g: ldo8 { }; }; =20 +ðernet0 { + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + + max-speed =3D <1000>; + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii-txid"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <ðernet0_default>; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + + /* Marvell 88EA1512 */ + rgmii_phy: phy@8 { + reg =3D <0x8>; + + interrupt-parent =3D <&tlmm>; + interrupts-extended =3D <&tlmm 127 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios =3D <&pmm8540c_gpios 1 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + + device_type =3D "ethernet-phy"; + + /* Set to RGMII_SGMII mode and soft reset. Turn off auto-negotiation + * from userspace to talk to the switch on the SGMII side of things + */ + marvell,reg-init =3D + /* Set MODE[2:0] to RGMII_SGMII */ + <0x12 0x14 0xfff8 0x4>, + /* Soft reset required after changing MODE[2:0] */ + <0x12 0x14 0x7fff 0x8000>; + }; + }; +}; + +ðernet1 { + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + + max-speed =3D <1000>; + phy-mode =3D "rgmii-txid"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <ðernet1_default>; + + status =3D "okay"; + + fixed-link { + speed =3D <1000>; + full-duplex; + }; +}; + &i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c0_default>; @@ -316,6 +436,66 @@ &xo_board_clk { /* PINCTRL */ =20 &tlmm { + ethernet0_default: ethernet0-default-state { + mdc-pins { + pins =3D "gpio175"; + function =3D "rgmii_0"; + drive-strength =3D <16>; + bias-pull-up; + }; + + mdio-pins { + pins =3D "gpio176"; + function =3D "rgmii_0"; + drive-strength =3D <16>; + bias-pull-up; + }; + + rgmii-tx-pins { + pins =3D "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio18= 8"; + function =3D "rgmii_0"; + drive-strength =3D <16>; + bias-pull-up; + }; + + rgmii-rx-pins { + pins =3D "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio18= 2"; + function =3D "rgmii_0"; + drive-strength =3D <16>; + bias-disable; + }; + }; + + ethernet1_default: ethernet1-default-state { + mdc-pins { + pins =3D "gpio97"; + function =3D "rgmii_1"; + drive-strength =3D <16>; + bias-pull-up; + }; + + mdio-pins { + pins =3D "gpio98"; + function =3D "rgmii_1"; + drive-strength =3D <16>; + bias-pull-up; + }; + + rgmii-tx-pins { + pins =3D "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio11= 0"; + function =3D "rgmii_1"; + drive-strength =3D <16>; + bias-pull-up; + }; + + rgmii-rx-pins { + pins =3D "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104= "; + function =3D "rgmii_1"; + drive-strength =3D <16>; + bias-disable; + }; + }; + i2c0_default: i2c0-default-state { /* To USB7002T-I/KDXVA0 USB hub (SIP1 only) */ pins =3D "gpio135", "gpio136"; --=20 2.39.2