From nobody Wed Feb 11 21:30:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB492C77B74 for ; Tue, 11 Apr 2023 12:59:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230195AbjDKM7g (ORCPT ); Tue, 11 Apr 2023 08:59:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230077AbjDKM73 (ORCPT ); Tue, 11 Apr 2023 08:59:29 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 666674EEE for ; Tue, 11 Apr 2023 05:59:17 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id he13so9485858wmb.2 for ; Tue, 11 Apr 2023 05:59:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1681217956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oA3SCmMmUD/IAk9Z1v5rltTbTYq+SKdjhm6lfHHp658=; b=JQNE1IfchbIn2GVpDDiaQ/zSPZ4+3Hd8CBeaUohmmz370EsZdeXyd3ZiFZ2RokeCHL GYlLLNw9h7PDbGYhKHqKk9UZURSHFaBYBuuKRO+vlFn+fJ9D0MxAWkpBcePyzlROQxSk UrVHGX3TqwoBBDKvBU4oWlpvdUTapDOx1w13AadmfrMjU0JSu2xWru80cnTKUzTSCuU2 F1URxs3NbTxBIC1lpP9SLwEbAF9RDK4mlTDRyQetTqX1XYXFexQwV+vS0DKma5onroEP Ox1+Ouc5QgxWp8EQIwwcuWBRvDMojNocEQFC346/v3Czk2vepE37cGpv2FValB5YJhzi Izag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681217956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oA3SCmMmUD/IAk9Z1v5rltTbTYq+SKdjhm6lfHHp658=; b=hJWC4jT25CHNKv2vsakFGS44Kv//eFeOTqI9by8BTDxB8axs0biGbCGVy/3QuAjAWb o1S+GoSSMWeC0tg8l3NCPJZi3ENrPVAGNcCC40ILyv1l16SNOkBcpFB+PilSvYngj2JJ p1MpVv9ybc5CHLZq4j9ZG2zu+WC3reI7U1uTGRagrQpgzc830ebdVxYxiX3ck730smWS 7TO/P6ssLVpv2HavtpeeeSwLeWrofjZLyh7Aok1T2VgEXiUlemaa7v2NTOasRewrGJsb xtbUbFqeThBHJJ4bba5qbezzZmiyJ/afXxH6wkQuHclrVuCVmky/kk8/Fkmohj1RxhDs Z9HA== X-Gm-Message-State: AAQBX9dNyEs5/xYYalghtdfWmiAyjmc/ch6ICwU/Ke9iBqtnahBwClPd jTO7wj+FrVUiI/RUZ0lpuqZRmg== X-Google-Smtp-Source: AKy350baywg3HOg439/TevC2LolspPa+LK7BM0K/XWVinG0RZSlL/iGwnRcymLvmvmEhHVb4axzPBA== X-Received: by 2002:a7b:c842:0:b0:3ed:88f5:160a with SMTP id c2-20020a7bc842000000b003ed88f5160amr2005327wml.11.1681217955867; Tue, 11 Apr 2023 05:59:15 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:15 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski , Krzysztof Kozlowski Subject: [PATCH v3 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Date: Tue, 11 Apr 2023 14:59:04 +0200 Message-Id: <20230411125910.401075-2-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Add the compatible for the Qualcomm Graphics Clock control module present on sa8775p platforms. It matches the generic QCom GPUCC description. Add device-specific DT bindings defines as well. Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski Acked-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 + .../dt-bindings/clock/qcom,sa8775p-gpucc.h | 50 +++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sa8775p-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Docu= mentation/devicetree/bindings/clock/qcom,gpucc.yaml index db53eb288995..1e3dc9deded9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -15,6 +15,7 @@ description: | =20 See also:: include/dt-bindings/clock/qcom,gpucc-sdm845.h + include/dt-bindings/clock/qcom,gpucc-sa8775p.h include/dt-bindings/clock/qcom,gpucc-sc7180.h include/dt-bindings/clock/qcom,gpucc-sc7280.h include/dt-bindings/clock/qcom,gpucc-sc8280xp.h @@ -27,6 +28,7 @@ properties: compatible: enum: - qcom,sdm845-gpucc + - qcom,sa8775p-gpucc - qcom,sc7180-gpucc - qcom,sc7280-gpucc - qcom,sc8180x-gpucc diff --git a/include/dt-bindings/clock/qcom,sa8775p-gpucc.h b/include/dt-bi= ndings/clock/qcom,sa8775p-gpucc.h new file mode 100644 index 000000000000..a5fd784b1ea2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H +#define _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CB_CLK 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_FF_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CX_SNOC_DVM_CLK 7 +#define GPU_CC_CXO_AON_CLK 8 +#define GPU_CC_CXO_CLK 9 +#define GPU_CC_DEMET_CLK 10 +#define GPU_CC_DEMET_DIV_CLK_SRC 11 +#define GPU_CC_FF_CLK_SRC 12 +#define GPU_CC_GMU_CLK_SRC 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 15 +#define GPU_CC_HUB_AON_CLK 16 +#define GPU_CC_HUB_CLK_SRC 17 +#define GPU_CC_HUB_CX_INT_CLK 18 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 19 +#define GPU_CC_MEMNOC_GFX_CLK 20 +#define GPU_CC_SLEEP_CLK 21 +#define GPU_CC_XO_CLK_SRC 22 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_FF_BCR 4 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 5 +#define GPUCC_GPU_CC_GMU_BCR 6 +#define GPUCC_GPU_CC_GX_BCR 7 +#define GPUCC_GPU_CC_XO_BCR 8 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +#endif /* _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H */ --=20 2.37.2 From nobody Wed Feb 11 21:30:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CF98C77B6F for ; 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Tue, 11 Apr 2023 05:59:16 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:16 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Shazad Hussain , Bartosz Golaszewski Subject: [PATCH v3 2/7] clk: qcom: add the GPUCC driver for sa8775p Date: Tue, 11 Apr 2023 14:59:05 +0200 Message-Id: <20230411125910.401075-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Shazad Hussain Add the clock driver for the Qualcomm Graphics Clock control module. Signed-off-by: Shazad Hussain [Bartosz: make ready for upstream] Co-authored-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sa8775p.c | 625 +++++++++++++++++++++++++++++++ 3 files changed, 635 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sa8775p.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d71c9d6036bb..12be3e2371b3 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -445,6 +445,15 @@ config SA_GCC_8775P Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SDCC, etc. =20 +config SA_GPUCC_8775P + tristate "SA8775P Graphics clock controller" + select QCOM_GDSC + select SA_GCC_8775P + help + Support for the graphics clock controller on SA8775P devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SC_GCC_7180 tristate "SC7180 Global Clock Controller" select QCOM_GDSC diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b54085e579a0..9ff4c373ad95 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_SC_DISPCC_7180) +=3D dispcc-sc7180.o obj-$(CONFIG_SC_DISPCC_7280) +=3D dispcc-sc7280.o obj-$(CONFIG_SC_DISPCC_8280XP) +=3D dispcc-sc8280xp.o obj-$(CONFIG_SA_GCC_8775P) +=3D gcc-sa8775p.o +obj-$(CONFIG_SA_GPUCC_8775P) +=3D gpucc-sa8775p.o obj-$(CONFIG_SC_GCC_7180) +=3D gcc-sc7180.o obj-$(CONFIG_SC_GCC_7280) +=3D gcc-sc7280.o obj-$(CONFIG_SC_GCC_8180X) +=3D gcc-sc8180x.o diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa87= 75p.c new file mode 100644 index 000000000000..18d23be8d435 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -0,0 +1,625 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights re= served. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" +#include "gdsc.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static const struct clk_parent_data parent_data_tcxo =3D { .index =3D DT_B= I_TCXO }; + +static const struct pll_vco lucid_evo_vco[] =3D { + { 249600000, 2020000000, 0 }, +}; + +/* 810MHz configuration */ +static struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x2a, + .alpha =3D 0x3000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00000001, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_pll0", + .parent_data =3D &parent_data_tcxo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1000MHz configuration */ +static struct alpha_pll_config gpu_cc_pll1_config =3D { + .l =3D 0x34, + .alpha =3D 0x1555, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00000001, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll gpu_cc_pll1 =3D { + .offset =3D 0x1000, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_pll1", + .parent_data =3D &parent_data_tcxo, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index =3D DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .index =3D DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index =3D DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .index =3D DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index =3D DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_ff_clk_src =3D { + .cmd_rcgr =3D 0x9474, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_0, + .freq_tbl =3D ftbl_gpu_cc_ff_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_ff_clk_src", + .parent_data =3D gpu_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x9318, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] =3D { + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x93ec, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_2, + .freq_tbl =3D ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_2), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x9010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_3, + .freq_tbl =3D ftbl_gpu_cc_xo_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_xo_clk_src", + .parent_data =3D gpu_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_3), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_demet_div_clk_src =3D { + .reg =3D 0x9054, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_demet_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src =3D { + .reg =3D 0x9430, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_ahb_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src =3D { + .reg =3D 0x942c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x911c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x911c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cb_clk =3D { + .halt_reg =3D 0x93a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x93a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_cb_clk", + .flags =3D CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk =3D { + .halt_reg =3D 0x9120, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9120, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_crc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_ff_clk =3D { + .halt_reg =3D 0x914c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x914c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_cx_ff_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x913c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x913c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk =3D { + .halt_reg =3D 0x9130, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9130, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_cx_snoc_dvm_clk", + .flags =3D CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk =3D { + .halt_reg =3D 0x9004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_cxo_aon_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x9144, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9144, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_cxo_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk =3D { + .halt_reg =3D 0x900c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x900c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_demet_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_demet_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_hlos1_vote_gpu_smmu_clk", + .flags =3D CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x93e8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x93e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x9148, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9148, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk =3D { + .halt_reg =3D 0x9150, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9150, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_memnoc_gfx_clk", + .flags =3D CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk =3D { + .halt_reg =3D 0x9134, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9134, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_sleep_clk", + .flags =3D CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gpu_cc_sa8775p_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CB_CLK] =3D &gpu_cc_cb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_FF_CLK] =3D &gpu_cc_cx_ff_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] =3D &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] =3D &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] =3D &gpu_cc_demet_clk.clkr, + [GPU_CC_DEMET_DIV_CLK_SRC] =3D &gpu_cc_demet_div_clk_src.clkr, + [GPU_CC_FF_CLK_SRC] =3D &gpu_cc_ff_clk_src.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AHB_DIV_CLK_SRC] =3D &gpu_cc_hub_ahb_div_clk_src.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] =3D &gpu_cc_hub_cx_int_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] =3D &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] =3D &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] =3D &gpu_cc_sleep_clk.clkr, + [GPU_CC_XO_CLK_SRC] =3D &gpu_cc_xo_clk_src.clkr, +}; + +static struct gdsc cx_gdsc =3D { + .gdscr =3D 0x9108, + .gds_hw_ctrl =3D 0x953c, + .pd =3D { + .name =3D "cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, +}; + +static struct gdsc gx_gdsc =3D { + .gdscr =3D 0x905c, + .pd =3D { + .name =3D "gx_gdsc", + .power_on =3D gdsc_gx_do_nothing_enable, + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D AON_RESET | RETAIN_FF_ENABLE, +}; + +static struct gdsc *gpu_cc_sa8775p_gdscs[] =3D { + [GPU_CC_CX_GDSC] =3D &cx_gdsc, + [GPU_CC_GX_GDSC] =3D &gx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_sa8775p_resets[] =3D { + [GPUCC_GPU_CC_ACD_BCR] =3D { 0x9358 }, + [GPUCC_GPU_CC_CB_BCR] =3D { 0x93a0 }, + [GPUCC_GPU_CC_CX_BCR] =3D { 0x9104 }, + [GPUCC_GPU_CC_FAST_HUB_BCR] =3D { 0x93e4 }, + [GPUCC_GPU_CC_FF_BCR] =3D { 0x9470 }, + [GPUCC_GPU_CC_GFX3D_AON_BCR] =3D { 0x9198 }, + [GPUCC_GPU_CC_GMU_BCR] =3D { 0x9314 }, + [GPUCC_GPU_CC_GX_BCR] =3D { 0x9058 }, + [GPUCC_GPU_CC_XO_BCR] =3D { 0x9000 }, +}; + +static const struct regmap_config gpu_cc_sa8775p_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9988, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gpu_cc_sa8775p_desc =3D { + .config =3D &gpu_cc_sa8775p_regmap_config, + .clks =3D gpu_cc_sa8775p_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_sa8775p_clocks), + .resets =3D gpu_cc_sa8775p_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_sa8775p_resets), + .gdscs =3D gpu_cc_sa8775p_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_sa8775p_gdscs), +}; + +static const struct of_device_id gpu_cc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,sa8775p-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sa8775p_match_table); + +static int gpu_cc_sa8775p_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap =3D qcom_cc_map(pdev, &gpu_cc_sa8775p_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpu_cc_sa8775p_desc, regmap); +} + +static struct platform_driver gpu_cc_sa8775p_driver =3D { + .probe =3D gpu_cc_sa8775p_probe, + .driver =3D { + .name =3D "gpu_cc-sa8775p", + .of_match_table =3D gpu_cc_sa8775p_match_table, + }, +}; + +static int __init gpu_cc_sa8775p_init(void) +{ + return platform_driver_register(&gpu_cc_sa8775p_driver); +} +subsys_initcall(gpu_cc_sa8775p_init); + +static void __exit gpu_cc_sa8775p_exit(void) +{ + platform_driver_unregister(&gpu_cc_sa8775p_driver); +} +module_exit(gpu_cc_sa8775p_exit); + +MODULE_DESCRIPTION("SA8775P GPUCC driver"); +MODULE_LICENSE("GPL"); --=20 2.37.2 From nobody Wed Feb 11 21:30:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CBCEC76196 for ; Tue, 11 Apr 2023 12:59:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230215AbjDKM7k (ORCPT ); Tue, 11 Apr 2023 08:59:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230044AbjDKM7a (ORCPT ); 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Tue, 11 Apr 2023 05:59:17 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski Subject: [PATCH v3 3/7] arm64: defconfig: enable the SA8775P GPUCC driver Date: Tue, 11 Apr 2023 14:59:06 +0200 Message-Id: <20230411125910.401075-4-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Enable the GPUCC module for SA8775P platforms in the arm64 defconfig. Signed-off-by: Bartosz Golaszewski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b6342b40c600..e1063ab32658 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1164,6 +1164,7 @@ CONFIG_MSM_GCC_8998=3Dy CONFIG_QCS_GCC_404=3Dy CONFIG_SA_GCC_8775P=3Dy CONFIG_SC_DISPCC_8280XP=3Dm +CONFIG_SA_GPUCC_8775P=3Dm CONFIG_SC_GCC_7180=3Dy CONFIG_SC_GCC_7280=3Dy CONFIG_SC_GCC_8180X=3Dy --=20 2.37.2 From nobody Wed Feb 11 21:30:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5D85C76196 for ; Tue, 11 Apr 2023 12:59:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230227AbjDKM7n (ORCPT ); Tue, 11 Apr 2023 08:59:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230177AbjDKM7c (ORCPT ); Tue, 11 Apr 2023 08:59:32 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 483A049EF for ; Tue, 11 Apr 2023 05:59:21 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id i8-20020a05600c354800b003ee93d2c914so5713295wmq.2 for ; Tue, 11 Apr 2023 05:59:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1681217959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TuLAeQGEV5K3iInBKoewzkhME+2oUBqCQOoUHj0zOJc=; b=PyPA+z9wzuCADbJtJNpxfh193DbvsBKQKRFsnEfdj2lux9LDV4aSpKu/Sl/j/gaY6D ff1p7jAPq70oW11rHUG0e/JHYABUvaI5p6p9GAY8Ed6gQvH3EyelCkOXAmD0OLsu5IvE 3On13qxxWDP8hytuA7PMIGBmRRi3Ajv35irx15owRr11QSYeL1uZ/S+ci5YMEt25UfFz J3jUc7nvNQGsFxBDwZgQVmuwS1wEMY75SVRm9ZLYiWMgtw5rXZ9grW2MwCw+D6srA522 d17sR+X/yCvaFxX6XaJ+jMVpEjFuaX3+dTC4FAUqWUG8Co7PMz4BS3urZXyS0wJGih8n 2Idg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681217959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TuLAeQGEV5K3iInBKoewzkhME+2oUBqCQOoUHj0zOJc=; b=PCFap2vF7uBKxeiw3iuzy1P2Qm2L7W6fPNV+wZOBoV2fizVmM4gvQOHzrcpnwm7FUX kBH19mcCKUJJ3DYJeYvBr4ucO9LoFITJ+FdxiBLu72JA2RIhv+ZCoHUOWO8jv6/0dHGF UL0h0/jQ42dTnnwhBZ5w0SbXH0DoNHZYXH9udWcSpCVf/kAt2ZjN8MsN4PcnIoUtMMWw 5HLGxpKFS43D/ql6fg02eV84mCa/Z3KXl7Cq9JvHvw9zJUCwCGF9qFwHzvy5ed315/4Q mV7Abr4X7dVSNApYGsLeEXaMK9+zfAyNA00J5Tb5aOIBW438dFlODMOndrL60gr2nsKG Cnhw== X-Gm-Message-State: AAQBX9ehfkHmyZoHcE2kpQ2Hwa+UFOpRHT8WCneC19l3nmzir5KHJtvS W8R4dx8WP/fZbC5ytpswtazgmw== X-Google-Smtp-Source: AKy350bBn4WjRe9oZZ13H+/2ZdNlHiC6u5ndF+nHtCFdwE/SHGsCimjWqVYVI8eMvSCk4yMuQkOmNw== X-Received: by 2002:a05:600c:2189:b0:3ed:5d41:f95c with SMTP id e9-20020a05600c218900b003ed5d41f95cmr10128112wme.11.1681217959220; Tue, 11 Apr 2023 05:59:19 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:18 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski Subject: [PATCH v3 4/7] arm64: dts: qcom: sa8775p: add the pcie smmu node Date: Tue, 11 Apr 2023 14:59:07 +0200 Message-Id: <20230411125910.401075-5-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Add the PCIe SMMU node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 2343df7e0ea4..a23175352a20 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 { ; }; =20 + pcie_smmu: iommu@15200000 { + compatible =3D "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x15200000 0x0 0x80000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17a00000 { compatible =3D "arm,gic-v3"; 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charset="utf-8" From: Bartosz Golaszewski Add the GPUCC node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index a23175352a20..191b510b5a1a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -591,6 +591,20 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells =3D <1>; }; =20 + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sa8775p-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0xa000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names =3D "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sa8775p-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x30000>, --=20 2.37.2 From nobody Wed Feb 11 21:30:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BF1AC77B70 for ; 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Tue, 11 Apr 2023 05:59:21 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:21 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski Subject: [PATCH v3 6/7] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU Date: Tue, 11 Apr 2023 14:59:09 +0200 Message-Id: <20230411125910.401075-7-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski The GPU SMMU will require the clocks property to be set so put the relevant compatible into the adreno if-then block. Signed-off-by: Bartosz Golaszewski Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Docume= ntation/devicetree/bindings/iommu/arm,smmu.yaml index 807cb511fe18..d966dc65ce10 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -79,6 +79,7 @@ properties: - description: Qcom Adreno GPUs implementing "arm,smmu-500" items: - enum: + - qcom,sa8775p-smmu-500 - qcom,sc7280-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 @@ -317,7 +318,9 @@ allOf: properties: compatible: contains: - const: qcom,sc7280-smmu-500 + enum: + - qcom,sa8775p-smmu-500 + - qcom,sc7280-smmu-500 then: properties: clock-names: @@ -375,7 +378,6 @@ allOf: - nvidia,smmu-500 - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 - - qcom,sa8775p-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 --=20 2.37.2 From nobody Wed Feb 11 21:30:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0381C76196 for ; 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Tue, 11 Apr 2023 05:59:22 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:a099:fc1d:c99a:bfc3]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003eae73f0fc1sm16944591wme.18.2023.04.11.05.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 05:59:22 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski Subject: [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Date: Tue, 11 Apr 2023 14:59:10 +0200 Message-Id: <20230411125910.401075-8-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230411125910.401075-1-brgl@bgdev.pl> References: <20230411125910.401075-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Add the Adreno GPU IOMMU for sa8775p-based platforms. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 191b510b5a1a..11f3d80dd869 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 { #power-domain-cells =3D <1>; }; =20 + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", + "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + dma-coherent; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + clocks =3D <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names =3D "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sa8775p-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x30000>, --=20 2.37.2