From nobody Wed Feb 11 19:46:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90B5EC7EE25 for ; Tue, 11 Apr 2023 10:05:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229710AbjDKKEn (ORCPT ); Tue, 11 Apr 2023 06:04:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229699AbjDKKET (ORCPT ); Tue, 11 Apr 2023 06:04:19 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8C172359F; Tue, 11 Apr 2023 03:04:15 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.98,336,1673881200"; d="scan'208";a="155587951" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 11 Apr 2023 19:04:14 +0900 Received: from localhost.localdomain (unknown [10.226.93.123]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 61B12400F2DA; Tue, 11 Apr 2023 19:04:11 +0900 (JST) From: Biju Das To: Rob Herring , Mauro Carvalho Chehab , Krzysztof Kozlowski Cc: Biju Das , Geert Uytterhoeven , Laurent Pinchart , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad Subject: [PATCH v2 5/8] arm64: dts: renesas: r9a07g044: Add DSI node Date: Tue, 11 Apr 2023 11:03:43 +0100 Message-Id: <20230411100346.299768-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411100346.299768-1-biju.das.jz@bp.renesas.com> References: <20230411100346.299768-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add DSI node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v1->v2: * Added Rb tag from Geert. * Reorder the patch based on the module fcpvd, vspd and then DSI for both RZ/G2L and RZ/V2L. --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/d= ts/renesas/r9a07g044.dtsi index 7698752742df..23bd28dd4d95 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -618,6 +618,34 @@ sbc: spi@10060000 { status =3D "disabled"; }; =20 + dsi: dsi@10850000 { + compatible =3D "renesas,r9a07g044-mipi-dsi", + "renesas,rzg2l-mipi-dsi"; + reg =3D <0 0x10850000 0 0x20000>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks =3D <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; + clock-names =3D "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets =3D <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, + <&cpg R9A07G044_MIPI_DSI_ARESET_N>, + <&cpg R9A07G044_MIPI_DSI_PRESET_N>; + reset-names =3D "rst", "arst", "prst"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + vspd: vsp@10870000 { compatible =3D "renesas,r9a07g044-vsp2"; reg =3D <0 0x10870000 0 0x10000>; --=20 2.25.1