From nobody Wed Feb 11 19:42:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF7ACC7619A for ; Tue, 11 Apr 2023 06:50:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230413AbjDKGuS (ORCPT ); Tue, 11 Apr 2023 02:50:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229766AbjDKGtu (ORCPT ); Tue, 11 Apr 2023 02:49:50 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 275922D6B for ; Mon, 10 Apr 2023 23:49:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681195755; x=1712731755; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BV5LLOlacNTt4g++kWcPPRqikSTDi86tcqNaVPEHCy0=; b=WXJ3PtYfwrE0YDj0S1yGMr/0aaNQoCWDT3x4QcCajDQhxXaynhXZ9a1Y Hw5di0n+GXUmCjsQ6PFqRW2JqVRZ6MHm+N1Otudr0ryh0ttzRjWh/2KWb 8TlST+JP5UhvqRGIu8ULTKJX+Anp9HcqbjVlagdV3oGY190PbUT/UX1EH 6+OOaBj5FLIqo4s1mKM/6kNRTZ/hgL2jhBwI/IS889Xr44b0mIMRdJgD5 XkV/rsC9Pi34czv+MCcGeSyKW2E0Gn0CHZA2pXz3TbOJiJEe6xs22F5Vs C32NM1OjfBMigNn+evfp7LRTPSLXpxXguVFtn6IYjZdqBsaHR3ZdPu7gm w==; X-IronPort-AV: E=McAfee;i="6600,9927,10676"; a="341028574" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="341028574" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2023 23:48:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10676"; a="1018256606" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="1018256606" Received: from allen-box.sh.intel.com ([10.239.159.127]) by fmsmga005.fm.intel.com with ESMTP; 10 Apr 2023 23:48:29 -0700 From: Lu Baolu To: Joerg Roedel Cc: Vinod Koul , Tina Zhang , Jacob Pan , Christophe JAILLET , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 09/17] iommu/vt-d: Use non-privileged mode for all PASIDs Date: Tue, 11 Apr 2023 14:48:07 +0800 Message-Id: <20230411064815.31456-10-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230411064815.31456-1-baolu.lu@linux.intel.com> References: <20230411064815.31456-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jacob Pan Supervisor Request Enable (SRE) bit in a PASID entry is for permission checking on DMA requests. When SRE =3D 0, DMA with supervisor privilege will be blocked. However, for in-kernel DMA this is not necessary in that we are targeting kernel memory anyway. There's no need to differentiate user and kernel for in-kernel DMA. Let's use non-privileged (user) permission for all PASIDs used in kernel, it will be consistent with DMA without PASID (RID_PASID) as well. Signed-off-by: Jacob Pan Link: https://lore.kernel.org/r/20230331231137.1947675-2-jacob.jun.pan@linu= x.intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index c771233d6f2a..f4e536fd5a28 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2316,8 +2316,6 @@ static int domain_setup_first_level(struct intel_iomm= u *iommu, if (level !=3D 4 && level !=3D 5) return -EINVAL; =20 - if (pasid !=3D PASID_RID2PASID) - flags |=3D PASID_FLAG_SUPERVISOR_MODE; if (level =3D=3D 5) flags |=3D PASID_FLAG_FL5LP; =20 --=20 2.34.1