From nobody Wed Feb 11 18:26:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B52B7C76196 for ; Tue, 11 Apr 2023 06:48:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230288AbjDKGsJ convert rfc822-to-8bit (ORCPT ); Tue, 11 Apr 2023 02:48:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230222AbjDKGry (ORCPT ); Tue, 11 Apr 2023 02:47:54 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C26F72D70; Mon, 10 Apr 2023 23:47:47 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id BF0FC24DB89; Tue, 11 Apr 2023 14:47:45 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:45 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:44 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 1/7] dt-bindings: power: Constrain properties for JH7110 PMU Date: Mon, 10 Apr 2023 23:47:37 -0700 Message-ID: <20230411064743.273388-2-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When use "starfive,jh7110-pmu-dphy" compatible, do not need the reg and interrupts properties. Signed-off-by: Changhuang Liang --- .../bindings/power/starfive,jh7110-pmu.yaml | 14 ++++++++++++-- include/dt-bindings/power/starfive,jh7110-pmu.h | 3 +++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.ya= ml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml index 98eb8b4110e7..ffb4406c2e56 100644 --- a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml +++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml @@ -8,6 +8,7 @@ title: StarFive JH7110 Power Management Unit =20 maintainers: - Walker Chen + - Changhuang Liang =20 description: | StarFive JH7110 SoC includes support for multiple power domains which ca= n be @@ -17,6 +18,7 @@ properties: compatible: enum: - starfive,jh7110-pmu + - starfive,jh7110-pmu-dphy =20 reg: maxItems: 1 @@ -29,10 +31,18 @@ properties: =20 required: - compatible - - reg - - interrupts - "#power-domain-cells" =20 +if: + properties: + compatible: + contains: + const: starfive,jh7110-pmu +then: + required: + - reg + - interrupts + additionalProperties: false =20 examples: diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-b= indings/power/starfive,jh7110-pmu.h index 132bfe401fc8..0bfd6700c144 100644 --- a/include/dt-bindings/power/starfive,jh7110-pmu.h +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -14,4 +14,7 @@ #define JH7110_PD_ISP 5 #define JH7110_PD_VENC 6 =20 +#define JH7110_PD_DPHY_TX 0 +#define JH7110_PD_DPHY_RX 1 + #endif --=20 2.25.1 From nobody Wed Feb 11 18:26:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D824FC7619A for ; Tue, 11 Apr 2023 06:48:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230210AbjDKGsE convert rfc822-to-8bit (ORCPT ); Tue, 11 Apr 2023 02:48:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230166AbjDKGry (ORCPT ); Tue, 11 Apr 2023 02:47:54 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 701C0269E; Mon, 10 Apr 2023 23:47:49 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 8123E24E20F; Tue, 11 Apr 2023 14:47:46 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:46 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:45 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 2/7] soc: starfive: Replace SOC_STARFIVE with ARCH_SATRFIVE Date: Mon, 10 Apr 2023 23:47:38 -0700 Message-ID: <20230411064743.273388-3-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Using ARCH_FOO symbol is preferred than SOC_FOO. Signed-off-by: Changhuang Liang Reviewed-by: Conor Dooley --- drivers/soc/starfive/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig index bdb96dc4c989..1e9b0c414fec 100644 --- a/drivers/soc/starfive/Kconfig +++ b/drivers/soc/starfive/Kconfig @@ -3,8 +3,8 @@ config JH71XX_PMU bool "Support PMU for StarFive JH71XX Soc" depends on PM - depends on SOC_STARFIVE || COMPILE_TEST - default SOC_STARFIVE + depends on ARCH_STARFIVE || COMPILE_TEST + default ARCH_STARFIVE select PM_GENERIC_DOMAINS help Say 'y' here to enable support power domain support. --=20 2.25.1 From nobody Wed Feb 11 18:26:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57A2CC77B74 for ; Tue, 11 Apr 2023 06:48:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230054AbjDKGsB convert rfc822-to-8bit (ORCPT ); Tue, 11 Apr 2023 02:48:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230168AbjDKGry (ORCPT ); Tue, 11 Apr 2023 02:47:54 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 703822D66; Mon, 10 Apr 2023 23:47:49 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 445FD24E225; Tue, 11 Apr 2023 14:47:47 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:47 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:46 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 3/7] soc: starfive: Modify ioremap to regmap Date: Mon, 10 Apr 2023 23:47:39 -0700 Message-ID: <20230411064743.273388-4-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Modify ioremap to regmap, easy to simplify code. Signed-off-by: Changhuang Liang --- drivers/soc/starfive/jh71xx_pmu.c | 43 +++++++++++++++++-------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71x= x_pmu.c index 7d5f50d71c0d..306218c83691 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -6,13 +6,13 @@ */ =20 #include -#include -#include +#include #include #include #include #include #include +#include #include =20 /* register offset */ @@ -59,7 +59,7 @@ struct jh71xx_pmu_match_data { struct jh71xx_pmu { struct device *dev; const struct jh71xx_pmu_match_data *match_data; - void __iomem *base; + struct regmap *base; struct generic_pm_domain **genpd; struct genpd_onecell_data genpd_data; int irq; @@ -75,11 +75,14 @@ struct jh71xx_pmu_dev { static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= *is_on) { struct jh71xx_pmu *pmu =3D pmd->pmu; + unsigned int val; =20 if (!mask) return -EINVAL; =20 - *is_on =3D readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask; + regmap_read(pmu->base, JH71XX_PMU_CURR_POWER_MODE, &val); + + *is_on =3D val & mask; =20 return 0; } @@ -130,7 +133,7 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *= pmd, u32 mask, bool on) encourage_hi =3D JH71XX_PMU_SW_ENCOURAGE_DIS_HI; } =20 - writel(mask, pmu->base + mode); + regmap_write(pmu->base, mode, mask); =20 /* * 2.Write SW encourage command sequence to the Software Encourage Reg (o= ffset 0x44) @@ -140,21 +143,21 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev= *pmd, u32 mask, bool on) * Then write the lower bits of the command sequence, followed by the u= pper * bits. The sequence differs between powering on & off a domain. */ - writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE); - writel(encourage_lo, pmu->base + JH71XX_PMU_SW_ENCOURAGE); - writel(encourage_hi, pmu->base + JH71XX_PMU_SW_ENCOURAGE); + regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, JH71XX_PMU_SW_ENCOURAGE_= ON); + regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, encourage_lo); + regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, encourage_hi); =20 spin_unlock_irqrestore(&pmu->lock, flags); =20 /* Wait for the power domain bit to be enabled / disabled */ if (on) { - ret =3D readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE, - val, val & mask, - 1, JH71XX_PMU_TIMEOUT_US); + ret =3D regmap_read_poll_timeout_atomic(pmu->base, JH71XX_PMU_CURR_POWER= _MODE, + val, val & mask, + 1, JH71XX_PMU_TIMEOUT_US); } else { - ret =3D readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE, - val, !(val & mask), - 1, JH71XX_PMU_TIMEOUT_US); + ret =3D regmap_read_poll_timeout_atomic(pmu->base, JH71XX_PMU_CURR_POWER= _MODE, + val, !(val & mask), + 1, JH71XX_PMU_TIMEOUT_US); } =20 if (ret) { @@ -190,14 +193,14 @@ static void jh71xx_pmu_int_enable(struct jh71xx_pmu *= pmu, u32 mask, bool enable) unsigned long flags; =20 spin_lock_irqsave(&pmu->lock, flags); - val =3D readl(pmu->base + JH71XX_PMU_TIMER_INT_MASK); + regmap_read(pmu->base, JH71XX_PMU_TIMER_INT_MASK, &val); =20 if (enable) val &=3D ~mask; else val |=3D mask; =20 - writel(val, pmu->base + JH71XX_PMU_TIMER_INT_MASK); + regmap_write(pmu->base, JH71XX_PMU_TIMER_INT_MASK, val); spin_unlock_irqrestore(&pmu->lock, flags); } =20 @@ -206,7 +209,7 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *= data) struct jh71xx_pmu *pmu =3D data; u32 val; =20 - val =3D readl(pmu->base + JH71XX_PMU_INT_STATUS); + regmap_read(pmu->base, JH71XX_PMU_INT_STATUS, &val); =20 if (val & JH71XX_PMU_INT_SEQ_DONE) dev_dbg(pmu->dev, "sequence done.\n"); @@ -220,8 +223,8 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *= data) dev_err(pmu->dev, "p-channel fail event.\n"); =20 /* clear interrupts */ - writel(val, pmu->base + JH71XX_PMU_INT_STATUS); - writel(val, pmu->base + JH71XX_PMU_EVENT_STATUS); + regmap_write(pmu->base, JH71XX_PMU_INT_STATUS, val); + regmap_write(pmu->base, JH71XX_PMU_EVENT_STATUS, val); =20 return IRQ_HANDLED; } @@ -271,7 +274,7 @@ static int jh71xx_pmu_probe(struct platform_device *pde= v) if (!pmu) return -ENOMEM; =20 - pmu->base =3D devm_platform_ioremap_resource(pdev, 0); + pmu->base =3D device_node_to_regmap(np); if (IS_ERR(pmu->base)) return PTR_ERR(pmu->base); =20 --=20 2.25.1 From nobody Wed Feb 11 18:26:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CB68C7619A for ; Tue, 11 Apr 2023 06:48:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230350AbjDKGsR convert rfc822-to-8bit (ORCPT ); Tue, 11 Apr 2023 02:48:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230235AbjDKGry (ORCPT ); Tue, 11 Apr 2023 02:47:54 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7043530E0; Mon, 10 Apr 2023 23:47:49 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id F336D24E2B9; Tue, 11 Apr 2023 14:47:47 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:48 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:47 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 4/7] soc: starfive: Add pmu type operation Date: Mon, 10 Apr 2023 23:47:40 -0700 Message-ID: <20230411064743.273388-5-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add pmu type, make a distinction between different PMU. Signed-off-by: Changhuang Liang --- drivers/soc/starfive/jh71xx_pmu.c | 55 ++++++++++++++++++++++--------- 1 file changed, 39 insertions(+), 16 deletions(-) diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71x= x_pmu.c index 306218c83691..98f6849d61de 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -45,6 +45,12 @@ */ #define JH71XX_PMU_TIMEOUT_US 100 =20 +/* pmu type */ +enum pmu_type { + JH71XX_PMU_GENERAL, + JH71XX_PMU_DPHY, +}; + struct jh71xx_domain_info { const char * const name; unsigned int flags; @@ -54,6 +60,7 @@ struct jh71xx_domain_info { struct jh71xx_pmu_match_data { const struct jh71xx_domain_info *domain_info; int num_domains; + u8 pmu_type; }; =20 struct jh71xx_pmu { @@ -75,19 +82,23 @@ struct jh71xx_pmu_dev { static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= *is_on) { struct jh71xx_pmu *pmu =3D pmd->pmu; + unsigned int offset =3D 0; unsigned int val; =20 if (!mask) return -EINVAL; =20 - regmap_read(pmu->base, JH71XX_PMU_CURR_POWER_MODE, &val); + if (pmu->match_data->pmu_type =3D=3D JH71XX_PMU_GENERAL) + offset =3D JH71XX_PMU_CURR_POWER_MODE; + + regmap_read(pmu->base, offset, &val); =20 *is_on =3D val & mask; =20 return 0; } =20 -static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= on) +static int jh71xx_pmu_general_set_state(struct jh71xx_pmu_dev *pmd, u32 ma= sk, bool on) { struct jh71xx_pmu *pmu =3D pmd->pmu; unsigned long flags; @@ -95,22 +106,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *= pmd, u32 mask, bool on) u32 mode; u32 encourage_lo; u32 encourage_hi; - bool is_on; int ret; =20 - ret =3D jh71xx_pmu_get_state(pmd, mask, &is_on); - if (ret) { - dev_dbg(pmu->dev, "unable to get current state for %s\n", - pmd->genpd.name); - return ret; - } - - if (is_on =3D=3D on) { - dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", - pmd->genpd.name, on ? "en" : "dis"); - return 0; - } - spin_lock_irqsave(&pmu->lock, flags); =20 /* @@ -169,6 +166,31 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev = *pmd, u32 mask, bool on) return 0; } =20 +static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= on) +{ + struct jh71xx_pmu *pmu =3D pmd->pmu; + bool is_on; + int ret =3D 0; + + ret =3D jh71xx_pmu_get_state(pmd, mask, &is_on); + if (ret) { + dev_dbg(pmu->dev, "unable to get current state for %s\n", + pmd->genpd.name); + return ret; + } + + if (is_on =3D=3D on) { + dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", + pmd->genpd.name, on ? "en" : "dis"); + return 0; + } + + if (pmu->match_data->pmu_type =3D=3D JH71XX_PMU_GENERAL) + ret =3D jh71xx_pmu_general_set_state(pmd, mask, on); + + return ret; +} + static int jh71xx_pmu_on(struct generic_pm_domain *genpd) { struct jh71xx_pmu_dev *pmd =3D container_of(genpd, @@ -360,6 +382,7 @@ static const struct jh71xx_domain_info jh7110_power_dom= ains[] =3D { static const struct jh71xx_pmu_match_data jh7110_pmu =3D { .num_domains =3D ARRAY_SIZE(jh7110_power_domains), .domain_info =3D jh7110_power_domains, + .pmu_type =3D JH71XX_PMU_GENERAL, }; =20 static const struct of_device_id jh71xx_pmu_of_match[] =3D { --=20 2.25.1 From nobody Wed Feb 11 18:26:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28E48C7619A for ; Tue, 11 Apr 2023 06:48:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230259AbjDKGsM convert rfc822-to-8bit (ORCPT ); Tue, 11 Apr 2023 02:48:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230172AbjDKGry (ORCPT ); Tue, 11 Apr 2023 02:47:54 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25D431BD5; Mon, 10 Apr 2023 23:47:50 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id A84DE24E226; Tue, 11 Apr 2023 14:47:48 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:48 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:47 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 5/7] soc: starfive: Use call back to parse device tree resources Date: Mon, 10 Apr 2023 23:47:41 -0700 Message-ID: <20230411064743.273388-6-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Different compatible parse device tree resources work in different ways. Signed-off-by: Changhuang Liang --- drivers/soc/starfive/jh71xx_pmu.c | 54 ++++++++++++++++++++++--------- 1 file changed, 39 insertions(+), 15 deletions(-) diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71x= x_pmu.c index 98f6849d61de..990db6735c48 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -57,10 +57,14 @@ struct jh71xx_domain_info { u8 bit; }; =20 +struct jh71xx_pmu; + struct jh71xx_pmu_match_data { const struct jh71xx_domain_info *domain_info; int num_domains; u8 pmu_type; + int (*pmu_parse_dt)(struct platform_device *pdev, + struct jh71xx_pmu *pmu); }; =20 struct jh71xx_pmu { @@ -251,6 +255,31 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void = *data) return IRQ_HANDLED; } =20 +static int jh7110_pmu_general_parse_dt(struct platform_device *pdev, + struct jh71xx_pmu *pmu) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + int ret; + + pmu->base =3D device_node_to_regmap(np); + if (IS_ERR(pmu->base)) + return PTR_ERR(pmu->base); + + pmu->irq =3D platform_get_irq(pdev, 0); + if (pmu->irq < 0) + return pmu->irq; + + ret =3D devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, + 0, pdev->name, pmu); + if (ret) + dev_err(dev, "failed to request irq\n"); + + jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_= FAIL, true); + + return 0; +} + static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index) { struct jh71xx_pmu_dev *pmd; @@ -296,23 +325,20 @@ static int jh71xx_pmu_probe(struct platform_device *p= dev) if (!pmu) return -ENOMEM; =20 - pmu->base =3D device_node_to_regmap(np); - if (IS_ERR(pmu->base)) - return PTR_ERR(pmu->base); - - pmu->irq =3D platform_get_irq(pdev, 0); - if (pmu->irq < 0) - return pmu->irq; - - ret =3D devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, - 0, pdev->name, pmu); - if (ret) - dev_err(dev, "failed to request irq\n"); + spin_lock_init(&pmu->lock); =20 match_data =3D of_device_get_match_data(dev); if (!match_data) return -EINVAL; =20 + if (match_data->pmu_parse_dt) { + ret =3D match_data->pmu_parse_dt(pdev, pmu); + if (ret) { + dev_err(dev, "failed to parse dt\n"); + return ret; + } + } + pmu->genpd =3D devm_kcalloc(dev, match_data->num_domains, sizeof(struct generic_pm_domain *), GFP_KERNEL); @@ -332,9 +358,6 @@ static int jh71xx_pmu_probe(struct platform_device *pde= v) } } =20 - spin_lock_init(&pmu->lock); - jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_= FAIL, true); - ret =3D of_genpd_add_provider_onecell(np, &pmu->genpd_data); if (ret) { dev_err(dev, "failed to register genpd driver: %d\n", ret); @@ -383,6 +406,7 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = =3D { .num_domains =3D ARRAY_SIZE(jh7110_power_domains), .domain_info =3D jh7110_power_domains, .pmu_type =3D JH71XX_PMU_GENERAL, + .pmu_parse_dt =3D jh7110_pmu_general_parse_dt, }; =20 static const struct of_device_id jh71xx_pmu_of_match[] =3D { --=20 2.25.1 From nobody Wed Feb 11 18:26:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AD90C76196 for ; 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Tue, 11 Apr 2023 14:47:48 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 6/7] soc: starfive: Add dphy pmu support Date: Mon, 10 Apr 2023 23:47:42 -0700 Message-ID: <20230411064743.273388-7-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dphy pmu to turn on/off the dphy power switch. Signed-off-by: Changhuang Liang --- MAINTAINERS | 1 + drivers/soc/starfive/jh71xx_pmu.c | 65 +++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0b2170e1e4ff..4d958f02403e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19944,6 +19944,7 @@ F: include/dt-bindings/reset/starfive?jh71*.h =20 STARFIVE JH71XX PMU CONTROLLER DRIVER M: Walker Chen +M: Changhuang Liang S: Supported F: Documentation/devicetree/bindings/power/starfive* F: drivers/soc/starfive/jh71xx_pmu.c diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71x= x_pmu.c index 990db6735c48..d4092ca4dccf 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -24,6 +24,9 @@ #define JH71XX_PMU_EVENT_STATUS 0x88 #define JH71XX_PMU_INT_STATUS 0x8C =20 +/* DPHY pmu register offset */ +#define JH71XX_PMU_DPHY_SWITCH 0x00 + /* sw encourage cfg */ #define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05 #define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50 @@ -94,6 +97,8 @@ static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pm= d, u32 mask, bool *is_o =20 if (pmu->match_data->pmu_type =3D=3D JH71XX_PMU_GENERAL) offset =3D JH71XX_PMU_CURR_POWER_MODE; + else if (pmu->match_data->pmu_type =3D=3D JH71XX_PMU_DPHY) + offset =3D JH71XX_PMU_DPHY_SWITCH; =20 regmap_read(pmu->base, offset, &val); =20 @@ -170,6 +175,23 @@ static int jh71xx_pmu_general_set_state(struct jh71xx_= pmu_dev *pmd, u32 mask, bo return 0; } =20 +static int jh71xx_pmu_dphy_set_state(struct jh71xx_pmu_dev *pmd, u32 mask,= bool on) +{ + struct jh71xx_pmu *pmu =3D pmd->pmu; + unsigned long flags; + + spin_lock_irqsave(&pmu->lock, flags); + + if (on) + regmap_update_bits(pmu->base, JH71XX_PMU_DPHY_SWITCH, mask, mask); + else + regmap_update_bits(pmu->base, JH71XX_PMU_DPHY_SWITCH, mask, 0); + + spin_unlock_irqrestore(&pmu->lock, flags); + + return 0; +} + static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= on) { struct jh71xx_pmu *pmu =3D pmd->pmu; @@ -191,6 +213,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *= pmd, u32 mask, bool on) =20 if (pmu->match_data->pmu_type =3D=3D JH71XX_PMU_GENERAL) ret =3D jh71xx_pmu_general_set_state(pmd, mask, on); + else if (pmu->match_data->pmu_type =3D=3D JH71XX_PMU_DPHY) + ret =3D jh71xx_pmu_dphy_set_state(pmd, mask, on); =20 return ret; } @@ -280,6 +304,25 @@ static int jh7110_pmu_general_parse_dt(struct platform= _device *pdev, return 0; } =20 +static int jh7110_pmu_dphy_parse_dt(struct platform_device *pdev, + struct jh71xx_pmu *pmu) +{ + struct device *parent; + struct device *dev =3D &pdev->dev; + + parent =3D pdev->dev.parent; + if (!parent) { + dev_err(dev, "No parent for syscon pmu\n"); + return -ENODEV; + } + + pmu->base =3D syscon_node_to_regmap(parent->of_node); + if (IS_ERR(pmu->base)) + return PTR_ERR(pmu->base); + + return 0; +} + static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index) { struct jh71xx_pmu_dev *pmd; @@ -409,10 +452,31 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = =3D { .pmu_parse_dt =3D jh7110_pmu_general_parse_dt, }; =20 +static const struct jh71xx_domain_info jh7110_dphy_power_domains[] =3D { + [JH7110_PD_DPHY_TX] =3D { + .name =3D "DPHY-TX", + .bit =3D 30, + }, + [JH7110_PD_DPHY_RX] =3D { + .name =3D "DPHY-RX", + .bit =3D 31, + }, +}; + +static const struct jh71xx_pmu_match_data jh7110_pmu_dphy =3D { + .num_domains =3D ARRAY_SIZE(jh7110_dphy_power_domains), + .domain_info =3D jh7110_dphy_power_domains, + .pmu_type =3D JH71XX_PMU_DPHY, + .pmu_parse_dt =3D jh7110_pmu_dphy_parse_dt, +}; + static const struct of_device_id jh71xx_pmu_of_match[] =3D { { .compatible =3D "starfive,jh7110-pmu", .data =3D (void *)&jh7110_pmu, + }, { + .compatible =3D "starfive,jh7110-pmu-dphy", + .data =3D (void *)&jh7110_pmu_dphy, }, { /* sentinel */ } @@ -429,5 +493,6 @@ static struct platform_driver jh71xx_pmu_driver =3D { builtin_platform_driver(jh71xx_pmu_driver); =20 MODULE_AUTHOR("Walker Chen "); +MODULE_AUTHOR("Changhuang Liang "); MODULE_DESCRIPTION("StarFive JH71XX PMU Driver"); MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Wed Feb 11 18:26:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34D27C76196 for ; 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Tue, 11 Apr 2023 14:47:50 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:49 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 7/7] riscv: dts: starfive: Add dphy rx pmu node Date: Mon, 10 Apr 2023 23:47:43 -0700 Message-ID: <20230411064743.273388-8-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dphy rx pmu node to configure dphy power. Signed-off-by: Changhuang Liang Reviewed-by: Walker Chen --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index f271c3184d3a..a82374afcc91 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -499,6 +499,11 @@ aoncrg: clock-controller@17000000 { aon_syscon: syscon@17010000 { compatible =3D "starfive,jh7110-aon-syscon", "syscon", "simple-mfd"; reg =3D <0x0 0x17010000 0x0 0x1000>; + + pwrc_dphy: power-controller { + compatible =3D "starfive,jh7110-pmu-dphy"; + #power-domain-cells =3D <1>; + }; }; =20 aongpio: pinctrl@17020000 { --=20 2.25.1