From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E57A5C7EE23 for ; Tue, 23 May 2023 08:25:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235825AbjEWIZy (ORCPT ); Tue, 23 May 2023 04:25:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236257AbjEWIY5 (ORCPT ); Tue, 23 May 2023 04:24:57 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B841E7B for ; Tue, 23 May 2023 01:22:55 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-510d6e1f1b2so1026078a12.3 for ; Tue, 23 May 2023 01:22:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684830174; x=1687422174; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=G7VSJ860e4Fh6HjTKl0hZQ20ZjzePmB9hlOaoC2DjYs=; b=AqrheRnUfrVTEhtq8rROFiX4T4egyD/vbOOpiNzm6AXJQV37ly2mH1W5jMHuQWXKNy 1wUOa359bgg901y9fxhjIEV6VqiaPUSo+WEkmPGwK7CkK1WICl5FXtuCzBkZxherNFbF 6vEtfpFuuw4w33vNN9JZeeS8RujXDXPvMAiazBaeUXMxIe5W3mAfuEU8eeBNdRCW9ZrE y2z9oAuhEfMJ+stV7MvTcxGt7I198ZOCZrVD6/plnouAMr8/icUkCqmtUVsgC7lCj+TJ mUX9lQ0U55zweXAsZ7Dk4oK+rflT5d16Cxa018AF2fZ3afE1/jYaiGFsTnfFOPJ7qegn +IBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684830174; x=1687422174; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G7VSJ860e4Fh6HjTKl0hZQ20ZjzePmB9hlOaoC2DjYs=; b=baU/mBP12aX8tPaRjKSdzU8JzrYY61UjkOhKomoFkdhMR4Xfr7nrucsWl+B2ZqnB5m eegm3Wvwq40swafOxkiIbuEaUUaWD0/OZTJrYtsM46UOD87mcmAp+Xs3dVI0YXLJfAbX v4ANfMvGukL8qcB5/O87MKdj56/vJKXPLvm9rAMCXc5WZtErYfc6ATX1QeNjvERR/5c3 QZUgF4cIvMGTj75sTmM7uGyLYCrbg6gZq83yChGcCF5yJ461i9U+k73mmvG7QBv+j1km se1i/LoTM4rwB6vfRrVezdd13L3R7WOiV7A0Ef3KOez3BBOT/+OIu3hmUm5vtD0GdytO lXgg== X-Gm-Message-State: AC+VfDxu35A5eZs/GuEITYvvu/jdTC4C/bPzu9ldlpFHMN9dqAoomH35 BcNJoC26sDuZqJxYhRM8e1UnQmqwHzdlFh8zHf0= X-Google-Smtp-Source: ACHHUZ4oGEBIae4rCVIdVQNqFVVBGfjQ0jdDLbNbELtK18p4kgkGWGFnwSZMy6yGRkihBvncLHQarw== X-Received: by 2002:a19:f610:0:b0:4f4:b3e2:ff5a with SMTP id x16-20020a19f610000000b004f4b3e2ff5amr960851lfe.50.1684828006998; Tue, 23 May 2023 00:46:46 -0700 (PDT) Received: from [192.168.1.101] (abyk138.neoplus.adsl.tpnet.pl. [83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:46:46 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:12 +0200 Subject: [PATCH v5 01/12] dt-bindings: display/msm: dsi-controller-main: Add SM6350 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-1-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Rob Herring X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=1129; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=YH8eQbnbg0vjMQ5V3QSyUBMSn5oiwSvn85ByrDyOEfM=; b=iJOYYgaeSN0oSmq0j2H96FoSofQ6aG73eXrUH3db2gWxCPO3+Q2hzxrJvjTFj0XZSqpdnvZ1b eFNviWtWfF6ByrnsPcGQl6tIX9XWsO48jcxiKfqtGeYi79yI4815nIR X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the DSI host found on SM6350. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2= ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index 130e16d025bc..43f801a94d79 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6350-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl @@ -297,6 +298,7 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl + - qcom,sm6350-dsi-ctrl then: properties: clocks: --=20 2.40.1 From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A072C77B75 for ; Tue, 23 May 2023 08:25:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235573AbjEWIZt (ORCPT ); Tue, 23 May 2023 04:25:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236229AbjEWIYx (ORCPT ); Tue, 23 May 2023 04:24:53 -0400 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C42572111 for ; Tue, 23 May 2023 01:22:20 -0700 (PDT) Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-4f3b9755961so3104120e87.0 for ; Tue, 23 May 2023 01:22:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684830079; x=1687422079; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+njLtj9xbvOIFM7dHEkaORkCFR8dY1HcWLWxadiCjHQ=; b=XAOsXQw2lAaRRnIy4XpH/8q6eFR6AzCz4vuatCcTJ2gv86nTxBndezEUE4DRpsRFB4 UKBEgY8HxRdXFAg1QT0jpYK92whTjyvCKSN2T2Hr3Qb1DuX6HeaAmyi80UZaOt0oo9rO 12RpW7PlV6vXngud6A/JW5lrYQrSlQfya4O524TjrdpzxssrALZ8DEAvmpXoTpaLi3mq VUK9H7tJ2AOPGlB+Znd9d9wRo3MH3T+CsykUkYmJ5kWj9he6/tBFQaJVGXDKaTyQRxjF nI+UYdC7r6kX95Idy6QYstOOft5PAIdn7wDqBTLxB0B07hCobJeP5oCZfKC+QFRk6ldm RQZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684830079; x=1687422079; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+njLtj9xbvOIFM7dHEkaORkCFR8dY1HcWLWxadiCjHQ=; b=LgZLXr0uItxv7FafH+mcyOyJcWGzCIKCeIol6qZtX/r2FfAaEcYy9nXrXHzZMo7+PA BDlmkFS13jU6Xdkv5Vxlvx/fiHoFRWN4s35VZ6/f+tyOKBVZj6CMaOZWy1u1dzeOnYoa Y7+UdyJi/KDyyDu9j1WWocEuUQCABLys81uzBbKXoPqSN7Txm0gJmx3lE+eEGHYLgH+p f8VOtF75/6+ptDD1C80+sXLaWNIcyEITRVkPkcCQX3ntQZnfJee+IJs7luhEATeAKhbx 08M41hq2UFDloCXyCjjK9BgoxiGXs1lfhjT5blrKqPoQl2QPMR+aJYRRQCc5/owIfJyY ClHg== X-Gm-Message-State: AC+VfDzGLX7+psPy8WCX01yyJXibzGZ/1MklJbj1TlGEf5GX0DM4FNWV vyHOKueF/tLTsg9DCOankqinoSGu4fTlEXg8Kdo= X-Google-Smtp-Source: ACHHUZ6Z1IporAEVTmntbzww2mlpou5nSlMKw864voVy8UcwTx7EkZjpX4C/Gxnrt4UFoN9aF+FP5Q== X-Received: by 2002:a19:ad02:0:b0:4f3:7b3c:2e16 with SMTP id t2-20020a19ad02000000b004f37b3c2e16mr4243599lfc.39.1684828008720; Tue, 23 May 2023 00:46:48 -0700 (PDT) Received: from [192.168.1.101] (abyk138.neoplus.adsl.tpnet.pl. [83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:46:48 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:13 +0200 Subject: [PATCH v5 02/12] dt-bindings: display/msm: dsi-controller-main: Add SM6375 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-2-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Rob Herring X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=1145; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1vb4mQXJIaOy+L2bFISsNkN0kUA69WSBSqQBJvQrOv8=; b=CBoqH84rn/pGKj9+tRprI5mq7KUtB5xc8n/iP2tnHJB7nuo3bD0S+ruz8fSKu0FIa/VAcT8yg /AEykRyGeNKCgjUs5bmGWxRpZkDJKXvjg9dSfvoyQFAbIoAeaTXT/oR X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the DSI host found on SM6375. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2= ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index 43f801a94d79..0cb1198eb3d0 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -27,6 +27,7 @@ properties: - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6350-dsi-ctrl + - qcom,sm6375-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl @@ -366,6 +367,7 @@ allOf: enum: - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6375-dsi-ctrl then: properties: clocks: --=20 2.40.1 From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4792DC7EE23 for ; Tue, 23 May 2023 08:33:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236020AbjEWIdT (ORCPT ); Tue, 23 May 2023 04:33:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232466AbjEWIcp (ORCPT ); Tue, 23 May 2023 04:32:45 -0400 Received: from mail-lj1-f174.google.com (mail-lj1-f174.google.com [209.85.208.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B0AB359B for ; Tue, 23 May 2023 01:28:48 -0700 (PDT) Received: by mail-lj1-f174.google.com with SMTP id 38308e7fff4ca-2af2451b3f1so53583041fa.2 for ; Tue, 23 May 2023 01:28:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684830435; x=1687422435; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NO5fRgfBpga7Z40GIKnv5Lmg/IglAEvXvStQNi4ygG0=; b=UEbFqDKUw+e3aBwwFoelRQkjFj0UVbG+Yl88T5I2KFjP5qEwbmwU0p0WuMgfSq08Tv g9ebd6QkwSx2GS2cKyR8w+fsnkQbU6GsCCJG4Ae26QpMde7rz8r0S0CzRf/GC0he36aW w5p772AIKG0AZ0nFt306k3BYLmmQU2ByxDNk8uJmaABTylIxHDcQmsV3eM1DRKd+qcRW D++HwDAGRrLlSzJjNynQnXiqyMBmtPs6dnKh89ek85+PWquG1o7qPghJMyVTLqQVCGAa JHeymehhWCvr5vNzh5NYtOgzJf61GR/vIqwjsl7PiTJlmyDPRq3XhGCxoQp72fIJCcTO kjrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684830435; x=1687422435; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NO5fRgfBpga7Z40GIKnv5Lmg/IglAEvXvStQNi4ygG0=; b=CztS7kyL4OvJHEQ0ndb8jRKqKS16Jka1oAQb5omJ2X8Udlgvr9idEvtPq5ioKYUrNP 49MPlUzprF6EJHhdzS1fyShUjMlIeFZAludoNt5tbncrO/A2lIB52ikzwA+X9pPralkD 9O51Kf695oDK9OHdPtKgRCn7bGaZaM4j2DXk6Ht/x04FkyxCeZYBoKrBMHMRWs1Pw5tB 6x2trJhEFmgVFMfOPm30qDzH5xduSVrTLQ5mIJV/FRHGta/LLT/e0yWx5n3jmzE4JCKd 0RucjVbtZfCXGliiGR7zZOW96i59m7fpfeREdhG/ESAoPzG1kqAlkGnXwE7QVjn05P3w na1A== X-Gm-Message-State: AC+VfDxyG3Hs83iTItIg4I3qmprj0zuQTWgaK1TBu01txkGVNjGjUiX8 nHEaRNOVI2IGRbkv9o97MIvqU1nGjcI5TZvOKb4= X-Google-Smtp-Source: ACHHUZ71JVmKh/tdS2RYAwVRVuFCKvLjiA3bfXy1Dgf8RKwZheiPzPj99AbW0bM/Es5vcP/qS5l2QQ== X-Received: by 2002:a19:ae1a:0:b0:4e9:cfd2:e2d with SMTP id f26-20020a19ae1a000000b004e9cfd20e2dmr4270367lfc.65.1684828010333; Tue, 23 May 2023 00:46:50 -0700 (PDT) Received: from [192.168.1.101] (abyk138.neoplus.adsl.tpnet.pl. [83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:46:49 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:14 +0200 Subject: [PATCH v5 03/12] dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-3-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=2117; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=0YTG0EAw+lDImyg5bB4Ke78N5DjTkdTQlY35rQdmXMI=; b=PHp0G4FhTqfvDuJ0a+D+2q6mMJa+Nwdr6F7LU3/mfGPFYlmLMf1YqUCyHEpLozcE6jCwyOP7y msjNM7JwYKCDFZGP5JteN8dX5wBsbcRqZuN/4W3O7Otz7m5nz44afFt X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SC7180, SM6350 and SM6375 use a rather similar hw setup for DPU, with the main exception being that the last one requires an additional throttle clock. It is not well understood yet, but failing to toggle it on makes the display hardware stall and not output any frames. Document SM6350 and SM6375 DPU. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../bindings/display/msm/qcom,sc7180-dpu.yaml | 23 ++++++++++++++++++= +++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml index 1fb8321d9ee8..630b11480496 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml @@ -13,7 +13,10 @@ $ref: /schemas/display/msm/dpu-common.yaml# =20 properties: compatible: - const: qcom,sc7180-dpu + enum: + - qcom,sc7180-dpu + - qcom,sm6350-dpu + - qcom,sm6375-dpu =20 reg: items: @@ -26,6 +29,7 @@ properties: - const: vbif =20 clocks: + minItems: 6 items: - description: Display hf axi clock - description: Display ahb clock @@ -33,8 +37,10 @@ properties: - description: Display lut clock - description: Display core clock - description: Display vsync clock + - description: Display core throttle clock =20 clock-names: + minItems: 6 items: - const: bus - const: iface @@ -42,6 +48,7 @@ properties: - const: lut - const: core - const: vsync + - const: throttle =20 required: - compatible @@ -52,6 +59,20 @@ required: =20 unevaluatedProperties: false =20 +allOf: + - if: + properties: + compatible: + const: qcom,sm6375-dpu + + then: + properties: + clocks: + minItems: 7 + + clock-names: + minItems: 7 + examples: - | #include --=20 2.40.1 From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1637C7EE23 for ; Tue, 23 May 2023 07:58:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235931AbjEWH6g (ORCPT ); Tue, 23 May 2023 03:58:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236034AbjEWH6O (ORCPT ); Tue, 23 May 2023 03:58:14 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84C3119A2 for ; Tue, 23 May 2023 00:56:33 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-510f3db1cd8so1023643a12.1 for ; Tue, 23 May 2023 00:56:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684828569; x=1687420569; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yjN/ffCdIbWuCww9f1G8lkgk4FzsnyMHqREJyrkcTto=; b=oH02Myg6OBzb8hdCgr3N4lxMEFLu+sLvSbZsjzu13xXxAnJ1LlSFWNJzQ+0swly5dW 8UitPMyZ9eQbfj5fUJ1fhc92x/WeOEA7q/TN4L8PBa8Kb24HVyr2jBGl7GtYofu7Pul0 OOvl818Ct9xQNr7G698lQDHZ/Zcho6pHPy4Da7hdRPi2S+j+sSbgbnIHj7fVBZe7AphO XIuuywNxmkl6UVV4CAa49sSPZ/QKA39Lmk15QgXmMEaUpU6i6yLsH+NtghFAPoiXct7L LEuf20EBG4IcYx/MLWzVIWABViB1XRPdggT48nS6CPdfPy8rHxhESg/MXYkkmGOH1Nl+ CSdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684828569; x=1687420569; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yjN/ffCdIbWuCww9f1G8lkgk4FzsnyMHqREJyrkcTto=; b=WB4MPVs2eU4SNeRl1V/MDlY3V1KeYEuBKxzVZURKAmQrz6mKmUnJm4aXJaXBt3KYlp ZyNRlKWjbgbrvTBiwt10JMpNelryvtGizOpjT3SHQtD/v2NSajWr/+ttKkqdgVAFfIOl H5+I1x6gSmxs/vCL3R8k3XogoP9DIoFB16EwVHxMOynUj8aTeXA16w23BOyzvQtsPX1D xWEZ+MlrEsizTdQlNZmK+kyGqHgsZvvN65XbAshJRHlSzxjxvU9dw2eaBBO8KAkWXZTo Co0aDIvsLTUDve0O5uiK0VMFYZz6UfHRf+S/c5jURdVl1g+bX8C5PzXU4cYnMWMSqJy/ psZg== X-Gm-Message-State: AC+VfDz+SHfU6uApjsK4lg/FSjJQdyM6whdc8iXPa2JJsPRtyowlqdBl DBnbAOUx1fB9yLpVsEpa/mvlkKXpn+kg9Pmgubw= X-Google-Smtp-Source: ACHHUZ49rm1/K7+1lTo1bvk/IjjsmNS6hlmKp4UhFsCuvas138RK2u3TIIENrzkIQU8U3U/mcFcNqQ== X-Received: by 2002:a05:6512:3912:b0:4f1:477c:f8a9 with SMTP id a18-20020a056512391200b004f1477cf8a9mr3306307lfu.65.1684828011962; Tue, 23 May 2023 00:46:51 -0700 (PDT) Received: from [192.168.1.101] (abyk138.neoplus.adsl.tpnet.pl. [83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:46:51 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:15 +0200 Subject: [PATCH v5 04/12] dt-bindings: display/msm: Add SM6350 MDSS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-4-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=7064; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ElBdVsUKD81P73zo0Ep2jls76a+QZxDiuf7z0YpIh/0=; b=ldgNP3J2Lx0gTf4vHq0jlxAi6qpO5ZtvRGMvLQH9iyadHFc3tw3WUuAI+HgsJVXgTk3uxpeFB Fz1xA8Dqz/DDbiLC1iuTXQu+xSKhn/xkc8dEWyhpQZB6hMhGJ23SnLX X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the SM6350 MDSS. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +++++++++++++++++= ++++ 1 file changed, 214 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml new file mode 100644 index 000000000000..6674040d2172 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 Display MDSS + +maintainers: + - Krishna Manikandan + +description: + SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6350-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6350-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm6350-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-10nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sm6350-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + power-domains =3D <&dispcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "bus", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x800 0x2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sm6350-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", "iface", "rot", "lut", "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + assigned-clock-rates =3D <300000000>, + <19200000>, + <19200000>, + <19200000>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM6350_CX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SM6350_MX>; + + phys =3D <&dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible =3D "qcom,dsi-phy-10nm"; + reg =3D <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_C= LK>; + clock-names =3D "iface", "ref"; + }; + }; +... --=20 2.40.1 From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6B82C77B75 for ; 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[83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:46:53 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:16 +0200 Subject: [PATCH v5 05/12] dt-bindings: display/msm: Add SM6375 MDSS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-5-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=7042; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ue7+w9cyuFPdfGbv/PRzJm40XzZEvHOKg8S5H0i+ojw=; b=3jNzrMwFnLFNRUsaFHmHuJWV7rcfLH0iyYSmv67jmeb8Jcx0ojkH2WdbzX3guA+98EYnfyeez zhIE83O8keQDtZo2cMkzf7IEjRdr7x8esa3GhnH4vo8GDOy31n5wjX3 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the SM6375 MDSS. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++= ++++ 1 file changed, 216 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml new file mode 100644 index 000000000000..3aa4f0470c95 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6375 Display MDSS + +maintainers: + - Konrad Dybcio + +description: + SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6375-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6375-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm6375-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6375-dsi-phy-7nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@5e00000 { + compatible =3D "qcom,sm6375-mdss"; + reg =3D <0x05e00000 0x1000>; + reg-names =3D "mdss"; + + power-domains =3D <&dispcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "ahb", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x820 0x2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@5e01000 { + compatible =3D "qcom,sm6375-dpu"; + reg =3D <0x05e01000 0x8e030>, + <0x05eb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>; + clock-names =3D "bus", + "iface", + "rot", + "lut", + "core", + "vsync", + "throttle"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmpd SM6375_VDDCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible =3D "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x05e94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy= 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmpd SM6375_VDDMX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@5e94400 { + compatible =3D "qcom,sm6375-dsi-phy-7nm"; + reg =3D <0x05e94400 0x200>, + <0x05e94600 0x280>, + <0x05e94900 0x264>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "ref"; + }; + }; +... --=20 2.40.1 From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60D4BC7EE23 for ; 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[83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.46.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:46:54 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:17 +0200 Subject: [PATCH v5 06/12] drm/msm/dpu: Add SM6350 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-6-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=9280; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ApJs8aGonS7EaDZ4Htc1NlHFmpfwm4QTWIiYwZIm7Jw=; b=mEbt1J8RUCDFXV/+MCqNepAMxLGaVRatAJDir2ySkvhAd61edvsLA817y3IBiIuIAhpQ0nVJL VOnXwMcL5YlAOHu2/9iUf8BMbHldzqI6DBsQusjriBYbdRmsCIKknY1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add SM6350 support to the DPU1 driver to enable display output. It's worth noting that one entry dpu_qos_lut_entry was trimmed off: {.fl =3D 0, .lut =3D 0x0011223344556677 }, due to the lack of support for selecting between portrait and landscape LUT settings (for danger and safe LUTs) and no full support for qseed/non-qseed usescases (for QoS LUT). Signed-off-by: Konrad Dybcio Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 173 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 180 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h new file mode 100644 index 000000000000..06eba23b0236 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_6_4_SM6350_H +#define _DPU_6_4_SM6350_H + +static const struct dpu_caps sm6350_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0x7, + .qseed_type =3D DPU_SSPP_SCALER_QSEED4, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg =3D { + .ubwc_version =3D DPU_HW_UBWC_VER_20, + .ubwc_swizzle =3D 6, + .highest_bank_bit =3D 1, +}; + +static const struct dpu_mdp_cfg sm6350_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0x0, .len =3D 0x494, + .features =3D 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] =3D { .reg_off =3D 0x2c4, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 2= 0 }, + }, +}; + +static const struct dpu_ctl_cfg sm6350_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x1600, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, +}; + +static const struct dpu_sspp_cfg sm6350_sspp[] =3D { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), +}; + +static const struct dpu_lm_cfg sm6350_lm[] =3D { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), +}; + +static const struct dpu_dspp_cfg sm6350_dspp[] =3D { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static struct dpu_pingpong_cfg sm6350_pp[] =3D { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + -1), +}; + +static const struct dpu_dsc_cfg sm6350_dsc[] =3D { + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), +}; + +static const struct dpu_intf_cfg sm6350_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 35, INTF_SC7180_MA= SK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_S= C7180_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), +}; + +static const struct dpu_perf_cfg sm6350_perf_data =3D { + .max_bw_low =3D 4200000, + .max_bw_high =3D 5100000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 35, + /* TODO: confirm danger_lut_tbl */ + .danger_lut_tbl =3D {0xffff, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xff00, 0xff00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +const struct dpu_mdss_cfg dpu_sm6350_cfg =3D { + .caps =3D &sm6350_dpu_caps, + .ubwc =3D &sm6350_ubwc_cfg, + .mdp_count =3D ARRAY_SIZE(sm6350_mdp), + .mdp =3D sm6350_mdp, + .ctl_count =3D ARRAY_SIZE(sm6350_ctl), + .ctl =3D sm6350_ctl, + .sspp_count =3D ARRAY_SIZE(sm6350_sspp), + .sspp =3D sm6350_sspp, + .mixer_count =3D ARRAY_SIZE(sm6350_lm), + .mixer =3D sm6350_lm, + .dspp_count =3D ARRAY_SIZE(sm6350_dspp), + .dspp =3D sm6350_dspp, + .dsc_count =3D ARRAY_SIZE(sm6350_dsc), + .dsc =3D sm6350_dsc, + .pingpong_count =3D ARRAY_SIZE(sm6350_pp), + .pingpong =3D sm6350_pp, + .intf_count =3D ARRAY_SIZE(sm6350_intf), + .intf =3D sm6350_intf, + .vbif_count =3D ARRAY_SIZE(sdm845_vbif), + .vbif =3D sdm845_vbif, + .perf =3D &sm6350_perf_data, + .mdss_irqs =3D BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF1_TEAR_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 1dee5ba2b312..6e338d569632 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -689,6 +689,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_linea= r[] =3D { {.fl =3D 0, .lut =3D 0x0011222222335777}, }; =20 +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] =3D { + {.fl =3D 0, .lut =3D 0x0011223445566777 }, +}; + static const struct dpu_qos_lut_entry sm8150_qos_linear[] =3D { {.fl =3D 0, .lut =3D 0x0011222222223357 }, }; @@ -744,6 +748,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_6_0_sm8250.h" #include "catalog/dpu_6_2_sc7180.h" #include "catalog/dpu_6_3_sm6115.h" +#include "catalog/dpu_6_4_sm6350.h" #include "catalog/dpu_6_5_qcm2290.h" =20 #include "catalog/dpu_7_0_sm8350.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 677048cc3b7d..ed4311f6aaf0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -834,6 +834,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; +extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 8ce057cc9374..d9925097626c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1328,6 +1328,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sc8180x-dpu", .data =3D &dpu_sc8180x_cfg, }, { .compatible =3D "qcom,sc8280xp-dpu", .data =3D &dpu_sc8280xp_cfg, }, { .compatible =3D "qcom,sm6115-dpu", .data =3D &dpu_sm6115_cfg, }, + { .compatible =3D "qcom,sm6350-dpu", .data =3D &dpu_sm6350_cfg, }, { .compatible =3D "qcom,sm8150-dpu", .data =3D &dpu_sm8150_cfg, }, { .compatible =3D "qcom,sm8250-dpu", .data =3D &dpu_sm8250_cfg, }, { .compatible =3D "qcom,sm8350-dpu", .data =3D &dpu_sm8350_cfg, }, --=20 2.40.1 From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E0A0C77B75 for ; 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[83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:46:56 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:18 +0200 Subject: [PATCH v5 07/12] drm/msm: mdss: Add SM6350 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-7-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=1447; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=0D7OZJvsI1VqBAldTbVtRFbwuC+jJW8mAUrMe9Ykcbs=; b=TAr1B/J8Fw4CbqlqV0fqrm0JKRVpsmTK2l29sM7+FcIchk7aAujxMonXnRCxaIbdOAlYDXrPe hiCF/x7Su9pAxMo2i4IgdPK5fVh9jtF1gNJwi/4saYxWY5K1xE5t3X/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for MDSS on SM6350. Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e8c93731aaa1..4e3a5f0c303c 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data =3D { .highest_bank_bit =3D 2, }; =20 +static const struct msm_mdss_data sm6350_data =3D { + .ubwc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D 6, + .ubwc_static =3D 0x1e, + .highest_bank_bit =3D 1, +}; + static const struct msm_mdss_data sm8150_data =3D { .ubwc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, @@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sc8180x-mdss", .data =3D &sc8180x_data }, { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &sc8280xp_data }, { .compatible =3D "qcom,sm6115-mdss", .data =3D &sm6115_data }, + { .compatible =3D "qcom,sm6350-mdss", .data =3D &sm6350_data }, { .compatible =3D "qcom,sm8150-mdss", .data =3D &sm8150_data }, { .compatible =3D "qcom,sm8250-mdss", .data =3D &sm8250_data }, { .compatible =3D "qcom,sm8350-mdss", .data =3D &sm8250_data }, --=20 2.40.1 From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CE0DC7EE23 for ; Tue, 23 May 2023 07:55:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235855AbjEWHzr (ORCPT ); Tue, 23 May 2023 03:55:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236105AbjEWHzX (ORCPT ); Tue, 23 May 2023 03:55:23 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B59A2E54 for ; Tue, 23 May 2023 00:55:00 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-96fe2a1db26so388752666b.0 for ; Tue, 23 May 2023 00:55:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684828480; x=1687420480; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Ut3ZAfO4y9fgOWEn1mcEXnszvvsFNUY31LRJIfA7nso=; b=VIpFlrY3l8/0mL8LARogr17xH10IRdY4vSrv19dnJTmXkrJkwxjN5WEPtotuT4T084 7v5c5CscWVVeEyXhzS5B1hqc8p/vHzSE/Mjj38TFyOzU+YKXNg70LzUUiPyMg0Hc7UYF H6jWqey1i2FMlSGlh1BSjwg8FV05CpL0aaaRQT7mPiRqGCVq18F2itX45W53n7hrdKFX WNAgkAuPV1kPKFpFDXcahL2KxZ3A/vzdGaajGtx8tf6aMLtJdqAvh503Coe+t1ztG/wG oll3Rt2A/XfO/X2BYXi4tdhMiXB/uH7QUCBjJj1jNSkqs5RULUTHYXRhzO80E9p71+Ip Ij5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684828480; x=1687420480; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ut3ZAfO4y9fgOWEn1mcEXnszvvsFNUY31LRJIfA7nso=; b=BemjVN+TfqwuOlbeeLIxe7w5GSZS6HmOIiPAe1IIHfx2AFtxOkP+2vUV4NMNCDH8F7 EcGrESqZ89im89+PMl+Ob2V9PbGfEmciWfTl5mtOjKW6r4vltCvzFEdDjflCqGaL4HiV g2+NWFbkKv8pzoNyiHNBRBvoaXcw8oD8G9LShWoakfDgby7LQUw1jASjBctFs6ticxY9 XEOXK9idHxwGLn+N/SHi/EOznlPHUUMPqkepIjPh8OlxkvN8ePFF7XzUT2EUYAPFvajO Z+x2+HTvrHGYeF2BwmRCOmztXs2V2WpZwE41c+HrE9UmunviR8wpg6AFjN3ZxixjnWf+ F7cw== X-Gm-Message-State: AC+VfDxLCbw2TaimZL3Bdh8YFCYHTsGiIFoW5fCPP2z8Nzorg/87l56t JTTo/6PBYSVn29+1zne9OEzVpKCUfzovnCru5mg= X-Google-Smtp-Source: ACHHUZ5qBjBfJpdlk/wfRS/VdZr5awac9peasVH7fvOilSBUjv8m6ILTqpIXNfHwYwAslfoUt5xtBw== X-Received: by 2002:ac2:5a07:0:b0:4f3:aa74:2faf with SMTP id q7-20020ac25a07000000b004f3aa742fafmr3918078lfn.6.1684828018979; Tue, 23 May 2023 00:46:58 -0700 (PDT) Received: from [192.168.1.101] (abyk138.neoplus.adsl.tpnet.pl. [83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:46:58 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:19 +0200 Subject: [PATCH v5 08/12] drm/msm/dpu: Add SM6375 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-8-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=7178; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=03CqBRCFBQ0jx252MqQ4uSySLYCalB9i6QiYngV+t0o=; b=KSJPPVCuQc8D/P703JrWZi4yv5jSeCKqpovSfj7xaSyu+gqli94Z3Jslq8jWcvQ6++0fB7Llg XXkH2Qkp+eHAJSZ3q5JB8z8c0KFIWmrjtX0MEZIwZZ8hRYvzAAjJ8ld X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add basic SM6375 support to the DPU1 driver to enable display output. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Reviewed-by: Marijn Suijten --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 139 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 142 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h new file mode 100644 index 000000000000..924f2526c06a --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_6_9_SM6375_H +#define _DPU_6_9_SM6375_H + +static const struct dpu_caps sm6375_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages =3D 0x4, + .qseed_type =3D DPU_SSPP_SCALER_QSEED4, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D 2160, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg =3D { + .ubwc_version =3D DPU_HW_UBWC_VER_20, + .ubwc_swizzle =3D 6, + .highest_bank_bit =3D 1, +}; + +static const struct dpu_mdp_cfg sm6375_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0x0, .len =3D 0x494, + .features =3D 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + }, +}; + +static const struct dpu_ctl_cfg sm6375_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, +}; + +static const struct dpu_sspp_cfg sm6375_sspp[] =3D { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), +}; + +static const struct dpu_lm_cfg sm6375_lm[] =3D { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, + &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), +}; + +static const struct dpu_dspp_cfg sm6375_dspp[] =3D { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sm6375_pp[] =3D { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), +}; + +static const struct dpu_dsc_cfg sm6375_dsc[] =3D { + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), +}; + +static const struct dpu_intf_cfg sm6375_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0), + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_S= C7280_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), +}; + +static const struct dpu_perf_cfg sm6375_perf_data =3D { + .max_bw_low =3D 5200000, + .max_bw_high =3D 6200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, /* No LLCC on this SoC */ + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 24, + /* TODO: confirm danger_lut_tbl */ + .danger_lut_tbl =3D {0xffff, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +const struct dpu_mdss_cfg dpu_sm6375_cfg =3D { + .caps =3D &sm6375_dpu_caps, + .ubwc =3D &sm6375_ubwc_cfg, + .mdp_count =3D ARRAY_SIZE(sm6375_mdp), + .mdp =3D sm6375_mdp, + .ctl_count =3D ARRAY_SIZE(sm6375_ctl), + .ctl =3D sm6375_ctl, + .sspp_count =3D ARRAY_SIZE(sm6375_sspp), + .sspp =3D sm6375_sspp, + .mixer_count =3D ARRAY_SIZE(sm6375_lm), + .mixer =3D sm6375_lm, + .dspp_count =3D ARRAY_SIZE(sm6375_dspp), + .dspp =3D sm6375_dspp, + .dsc_count =3D ARRAY_SIZE(sm6375_dsc), + .dsc =3D sm6375_dsc, + .pingpong_count =3D ARRAY_SIZE(sm6375_pp), + .pingpong =3D sm6375_pp, + .intf_count =3D ARRAY_SIZE(sm6375_intf), + .intf =3D sm6375_intf, + .vbif_count =3D ARRAY_SIZE(sdm845_vbif), + .vbif =3D sdm845_vbif, + .perf =3D &sm6375_perf_data, + .mdss_irqs =3D BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF1_TEAR_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 6e338d569632..7cfdcf7aa486 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -750,6 +750,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_6_3_sm6115.h" #include "catalog/dpu_6_4_sm6350.h" #include "catalog/dpu_6_5_qcm2290.h" +#include "catalog/dpu_6_9_sm6375.h" =20 #include "catalog/dpu_7_0_sm8350.h" #include "catalog/dpu_7_2_sc7280.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index ed4311f6aaf0..b84c14318449 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -836,6 +836,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; +extern const struct dpu_mdss_cfg dpu_sm6375_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index d9925097626c..d3ca8c3c808c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1329,6 +1329,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sc8280xp-dpu", .data =3D &dpu_sc8280xp_cfg, }, { .compatible =3D "qcom,sm6115-dpu", .data =3D &dpu_sm6115_cfg, }, { .compatible =3D "qcom,sm6350-dpu", .data =3D &dpu_sm6350_cfg, }, + { .compatible =3D "qcom,sm6375-dpu", .data =3D &dpu_sm6375_cfg, }, { .compatible =3D "qcom,sm8150-dpu", .data =3D &dpu_sm8150_cfg, }, { .compatible =3D "qcom,sm8250-dpu", .data =3D &dpu_sm8250_cfg, }, { .compatible =3D "qcom,sm8350-dpu", .data =3D &dpu_sm8350_cfg, }, --=20 2.40.1 From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93768C7EE23 for ; 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[83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.46.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:47:00 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:20 +0200 Subject: [PATCH v5 09/12] drm/msm: mdss: Add SM6375 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-9-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=1022; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Nh6zuYJI8gb14gxje6MmS/hbQSaIA3Eeoi75EfztoC0=; b=mwOMTHZtQczidymOKPTKW1hJ3k0Sfycwrop+S9790DYqps1onxdXRPHNXVFw+jMyTBbN68XRh O+ZzxbdzSd9AdFBeZSqcdaG2O5vRco+Dkni81Bj96yukCZc4ScXw/yr X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for MDSS on SM6375. Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 4e3a5f0c303c..05648c910c68 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -580,6 +580,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &sc8280xp_data }, { .compatible =3D "qcom,sm6115-mdss", .data =3D &sm6115_data }, { .compatible =3D "qcom,sm6350-mdss", .data =3D &sm6350_data }, + { .compatible =3D "qcom,sm6375-mdss", .data =3D &sm6350_data }, { .compatible =3D "qcom,sm8150-mdss", .data =3D &sm8150_data }, { .compatible =3D "qcom,sm8250-mdss", .data =3D &sm8250_data }, { .compatible =3D "qcom,sm8350-mdss", .data =3D &sm8250_data }, --=20 2.40.1 From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 146D8C7EE23 for ; Tue, 23 May 2023 08:20:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236067AbjEWIUm (ORCPT ); Tue, 23 May 2023 04:20:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231709AbjEWITp (ORCPT ); Tue, 23 May 2023 04:19:45 -0400 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2CED1BCA for ; Tue, 23 May 2023 01:17:57 -0700 (PDT) Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-4f4b256a0c9so1988902e87.2 for ; Tue, 23 May 2023 01:17:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684829816; x=1687421816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Uw6zfBHO0opEqODFwIHcb35ENxPJxB7I1/UM0FjZOR4=; b=rO/mlnMe0juAfrp+bwTQRotV7vZq/zI3lAtffatqC5TQNH/pvGh7BO8Zg1mwhSiLuP nAOhvxQbk+J024E+foGtlb3HGRApBNrZ3YNdyYKQh1r0nE42MpQsfUh618NLoNZtrYxM yiT0W1BLHFT59DBORdg2Pv26aem5o9RtDzX8zvHUa8KzqoxXPnScBGFjms9Ep9guXuib Cdx4T5N/mygHPGNzKWn8xdamnB90TPS/exKzlGPDkVzRbewB7PiiTqsy9cry7nF3CP+2 j7hZIlwgSW4CGtUuuA5pDsScTV2qe9WD9kOWGtvYTVvoNy8Ipe5VbeTYsaX3gJ8q5mzf GfCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684829816; x=1687421816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uw6zfBHO0opEqODFwIHcb35ENxPJxB7I1/UM0FjZOR4=; b=arLOV2ORi5LwuD2f9Nc2b90WZ4frbDImiaZerZj/VwB3+FH3HicRAOadQTJqJRrXaY HU1oLXy/Hzpuq+RZjUFgzjWr/Dsu29YCvrUg1TaXOwjd3IA8GXJlpTiSNII1Yz5S0UHj yzrKp9DoJ0CyTttqeZGEXop/KA76ohIHeKzJ51Xzc7NT1jAKgPX3z9yZvSZYbTn0ebpI n4YWwrYDEq0DI/7Cl1PfrOyn14b7nRu6c3h8FJm2pI3eH24i+NL29Z9pv7cGO9VcLaR9 stBJwX9zsggUwMin8sAr2MxtBZlADlZ9bOQ6hx4Y2Rz/l1g+oHyp+kAW4GXXimLj0FHX BUlg== X-Gm-Message-State: AC+VfDyR44h6Lx+araREERJJ81bYvjha+oHIrb5QPxRcITiQCLZ+nVHq 1erNBWLmeHwXcFxgtHQDd4mqKFHfQ8fczUmSIs0= X-Google-Smtp-Source: ACHHUZ5je+tCABEpT59rWVo/4tlBAhiBSx3eWKuptU/vYCax7CwZgnwKQkwyRKrX/EuvKpPExSEdGg== X-Received: by 2002:ac2:5d72:0:b0:4f3:bbfe:db4e with SMTP id h18-20020ac25d72000000b004f3bbfedb4emr2136125lft.56.1684828022062; Tue, 23 May 2023 00:47:02 -0700 (PDT) Received: from [192.168.1.101] (abyk138.neoplus.adsl.tpnet.pl. [83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.47.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:47:01 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:21 +0200 Subject: [PATCH v5 10/12] iommu/arm-smmu-qcom: Sort the compatible list alphabetically MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-10-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=1026; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Rc5Y2oI69X8xvGgWy74AqbUqZBcFJifSW/Zzw/OwQv0=; b=AxD88SslQYlSx+jDzVZY7fDCrbjY+DxcqY2OWDXBPIglsPSrTy+5sbTPXxbrAqbDZono0TRFx 8kqS2MfeoXfAzSUSXNSdhEehNfc1/lMYFLm6PLksmE0XSCcxYw8tQoV X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It got broken at some point, fix it up. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index c71afda79d64..3800ab478216 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -251,10 +251,10 @@ static const struct of_device_id qcom_smmu_client_of_= match[] __maybe_unused =3D { { .compatible =3D "qcom,sc7280-mss-pil" }, { .compatible =3D "qcom,sc8180x-mdss" }, { .compatible =3D "qcom,sc8280xp-mdss" }, - { .compatible =3D "qcom,sm8150-mdss" }, - { .compatible =3D "qcom,sm8250-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, + { .compatible =3D "qcom,sm8150-mdss" }, + { .compatible =3D "qcom,sm8250-mdss" }, { } }; =20 --=20 2.40.1 From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC3D9C7EE23 for ; Tue, 23 May 2023 07:55:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235858AbjEWHyr (ORCPT ); Tue, 23 May 2023 03:54:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235860AbjEWHy3 (ORCPT ); Tue, 23 May 2023 03:54:29 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15198E41 for ; Tue, 23 May 2023 00:54:14 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-96f7377c86aso798105266b.1 for ; Tue, 23 May 2023 00:54:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684828451; x=1687420451; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mfoMnvnUW9JxHFNrsE+j3PaFEyoaLfNhlabOCKS4wNc=; b=fIuNPWrT5fVpNPrBVxFz9i8Zyvr/jIzknAIqyI1J3StXMIRJh7UnlbO2g+EZ2Aow6O nUuPrfBWn62/AxK5q4hG65xtmXAhpYcMEx1eujLLcTLYtZ0P9QRid2SRdRPcVsES9p7V zNabMS1NwJdgBIuH6vh2WkK77LD33Lac1JlFQeEXJIUWf4Wc39samJRlQp8Z4s7C4qLU BKgI6rAGS9nb57XSYOmUAB5ku076mGtFla3nGzEt+COF1p27zeZlj0H37Q2yVBclcvXD s4z31VuGYl3yYV6L+zewNkIDfXimvN05c3W5mNchFslXtd8EVwDPeSeg+BZ2FxAH7XE+ O1Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684828451; x=1687420451; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mfoMnvnUW9JxHFNrsE+j3PaFEyoaLfNhlabOCKS4wNc=; b=F1/nBVyV5ngP6fnDyyKHEoliK5yBoVcCVb1VL6ZUtqCefaHDLYedprspb4BkezDOUx BI85AsIo5RR50z+NB3Wc6TxD49zXdmDIzbH21UmsHz0wuGcTAoMpY9t/HxUcvfCsJxeJ b/7JQ5StDfIHqQgdvgmNww0YGbUItOTk430TRqfaPBMEobsJINTSlXgdOcOLCOsBlW1g pAcmgymK3KPoArHKC2f1khaqBbo4sY4tsAN4kc6fZv8N7S6WihiD0xYrpxRkyhZv5nzp ZuEwWFhKOovGLQYEryLmoPRfxcGFGzAkRo35mhD83oMnavv4r4KD7j5oyYI/NOIYXKlk V9xA== X-Gm-Message-State: AC+VfDwWn8oLw9V5M0vrMv5nhP31ZsZ0RIrQ5NKBPTTKpWaPs+JUMrgJ dS/lmColVPEiZRm4fXZ9Dq66Y3+bWntaeHAxdLM= X-Google-Smtp-Source: ACHHUZ7vQpCMD8z+tXopWFPnkqXpWLOyK1g9oM8UkYcSzlJeaWh7JT+2ofWynI9x1gg11eZm6ERCiw== X-Received: by 2002:ac2:4e4c:0:b0:4f3:aa29:b663 with SMTP id f12-20020ac24e4c000000b004f3aa29b663mr4324951lfr.35.1684828023618; Tue, 23 May 2023 00:47:03 -0700 (PDT) Received: from [192.168.1.101] (abyk138.neoplus.adsl.tpnet.pl. [83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.47.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:47:03 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:22 +0200 Subject: [PATCH v5 11/12] iommu/arm-smmu-qcom: Add SM6375 DPU compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-11-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=919; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=U7GrazUMOESVisMUp1R2X/i2E38+ra43yVyDZTsdMko=; b=694+VJyXCZBUKckTCLQ5CsRJG+wJkbWuXCzZ6sGhBmhOWdEFH75k2SBgXqgbcBhvOwywQuLyK PilQQ3EaWw+A7wV3sA9YtDy/qbCmXblyVWuNqJmC+1aZwMqKT08ZrDA X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the SM6375 DPU compatible to clients compatible list, as it also needs the workarounds. Acked-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 3800ab478216..cc574928c707 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -253,6 +253,7 @@ static const struct of_device_id qcom_smmu_client_of_ma= tch[] __maybe_unused =3D { { .compatible =3D "qcom,sc8280xp-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, + { .compatible =3D "qcom,sm6375-mdss" }, { .compatible =3D "qcom,sm8150-mdss" }, { .compatible =3D "qcom,sm8250-mdss" }, { } --=20 2.40.1 From nobody Fri Dec 19 20:14:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E202C77B75 for ; Tue, 23 May 2023 07:58:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235963AbjEWH6y (ORCPT ); Tue, 23 May 2023 03:58:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236020AbjEWH6a (ORCPT ); Tue, 23 May 2023 03:58:30 -0400 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3706B19BD for ; Tue, 23 May 2023 00:57:01 -0700 (PDT) Received: by mail-lf1-f43.google.com with SMTP id 2adb3069b0e04-4f3a166f8e9so5591932e87.0 for ; Tue, 23 May 2023 00:57:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684828486; x=1687420486; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=71R2q19ZXsGZnOPocAOTBJ3+IZ1FZhz4Wl6PP95R9qE=; b=Vxc5lAHQMuXkx0ShhAwuwEBwuONqVTJGJ0X8IlpEdNTONHf9rn1dS+GSC09Ql3OHYc Wi9uSToFUf34ow5nkyQyhG0m/egv9OMAkjC4huA0JPDzw432XgvqEvioncHfGW5xEpwR QIAVKkJ7U0xcsaImike5rf9NVEuoYzXm3UGhFZ4bfKeOC9hxX7ZoDk+DJJJ9SaHZk2GP wDaMw6is8mcWda79nTJtUzxtZhVZInA+0DC0PBV+QCY48wQ4u4BQlYOL7OO5KD0cKlSU hbM/GHAOLzbt8D6nVVEF1KQQ3BSjQQDCt9OO2r5sI8kqJKShIknjDb9mU564lq9a7RjR zYjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684828486; x=1687420486; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=71R2q19ZXsGZnOPocAOTBJ3+IZ1FZhz4Wl6PP95R9qE=; b=AzLhqmBOXmh9Ixe689xLgncDMIM8gmjBsSrBD8bTSGtrqO8n0KCmQE32lcUi7gkeHN oENX8Mndgmuk+yWIVmtffYA7XPD4PlnshVkozlIZfXCWXYbf8qltU7gJnNh502ruWvEc zNdFtGOSirOdlpYuFD7oislzxvsvhmlR6blAasn88LZadQN6ySopwEN3ZDS6wx6BX56o XXTao7QZg5fbZxSULhQNftFSsUqk1StLEwhrnnKmZAvvTYXX/B1cU9Q9hwULLGiRttmz arieT322G2rmZDF6mvDShWebPtv8wYK4rHWa4nI3Nv7Z6eT3vz3gpuwhz1gez+JInWUS Ue0Q== X-Gm-Message-State: AC+VfDymkf/CbO42ls+R/XUYhTWbiDZiHF925Xh24Ni4JvFGyCIbh0+X pZeD4tCEwYkN3j7GTVb0bvzfXe3fiujzoA9Ivrc= X-Google-Smtp-Source: ACHHUZ5JTVpp/5NYzr6IYfEXUmBsbC2bmktnK/xToOViR87FZyWOzG7h4gTsSFl8nLwfgfTSrf+jJg== X-Received: by 2002:ac2:4847:0:b0:4f3:b242:aa98 with SMTP id 7-20020ac24847000000b004f3b242aa98mr4037954lfy.30.1684828025193; Tue, 23 May 2023 00:47:05 -0700 (PDT) Received: from [192.168.1.101] (abyk138.neoplus.adsl.tpnet.pl. [83.9.30.138]) by smtp.gmail.com with ESMTPSA id t9-20020ac25489000000b004eb0c51780bsm1257070lfk.29.2023.05.23.00.47.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 00:47:04 -0700 (PDT) From: Konrad Dybcio Date: Tue, 23 May 2023 09:46:23 +0200 Subject: [PATCH v5 12/12] iommu/arm-smmu-qcom: Add SM6350 DPU compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v5-12-998b4d2f7dd1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684828003; l=1014; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=CPO6pRkqp9OH9BXcQBO5PamnhFLC+q+SwQwF41wCtLY=; b=k7xKsuFLcWfaIkR5AoVwsP5oWEGrwWp29yM+FdNZiowj/uPcFBuemt4KcDaxucF97xazSftcP FeLxlwlnyYMCspg0xBeAlehmkXWyCgK+IbNjZK0m2G5efyzBkT9Mgm+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Konrad Dybcio Add the SM6350 DPU compatible to clients compatible list, as it also needs the workarounds. Signed-off-by: Konrad Dybcio Acked-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index cc574928c707..bdeb587552c0 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -253,6 +253,7 @@ static const struct of_device_id qcom_smmu_client_of_ma= tch[] __maybe_unused =3D { { .compatible =3D "qcom,sc8280xp-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, + { .compatible =3D "qcom,sm6350-mdss" }, { .compatible =3D "qcom,sm6375-mdss" }, { .compatible =3D "qcom,sm8150-mdss" }, { .compatible =3D "qcom,sm8250-mdss" }, --=20 2.40.1