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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:46 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:29 +0200 Subject: [PATCH v4 08/12] drm/msm/dpu: Add SM6375 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-8-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=7490; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=EHCd7rxYqWd4K8OPe4c07JXBY+0m2epxbCjM8CCGMoY=; b=n9BgwFD6kAjQ1kAJZhJd/Mi/ZmNCjOKjrADL1DnfhIgJyCNHX5IxkcbuWW2IVAxJFhZPhTIgG H7f0R8q0ZLTAfDN65F7kBHbYv5Jz1r3GBo7ToZpYOW/7p2dh+5HUv72 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add basic SM6375 support to the DPU1 driver to enable display output. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 153 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 156 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h new file mode 100644 index 000000000000..5085e7409ff6 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_6_9_SM6375_H +#define _DPU_6_9_SM6375_H + +static const struct dpu_caps sm6375_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages =3D 0x4, + .qseed_type =3D DPU_SSPP_SCALER_QSEED4, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D 2160, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg =3D { + .ubwc_version =3D DPU_HW_UBWC_VER_20, + .ubwc_swizzle =3D 6, + .highest_bank_bit =3D 1, +}; + +static const struct dpu_mdp_cfg sm6375_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0x0, .len =3D 0x494, + .features =3D 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + }, +}; + +static const struct dpu_ctl_cfg sm6375_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, +}; + +static const struct dpu_sspp_cfg sm6375_sspp[] =3D { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), +}; + +static const struct dpu_lm_cfg sm6375_lm[] =3D { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, + &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), +}; + +static const struct dpu_dspp_cfg sm6375_dspp[] =3D { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sm6375_pp[] =3D { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), +}; + +static const struct dpu_intf_cfg sm6375_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0), + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_S= C7280_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), +}; + +static const struct dpu_vbif_cfg sm6375_vbif[] =3D { + { + .name =3D "vbif_0", .id =3D VBIF_RT, + .base =3D 0, .len =3D 0x2008, + .features =3D BIT(DPU_VBIF_QOS_REMAP), + .xin_halt_timeout =3D 0x4000, + .qos_rp_remap_size =3D 0x40, + .qos_rt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_rt_pri_lvl), + .priority_lvl =3D sdm845_rt_pri_lvl, + }, + .qos_nrt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl =3D sdm845_nrt_pri_lvl, + }, + .memtype_count =3D 14, + .memtype =3D {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, + }, +}; + +static const struct dpu_perf_cfg sm6375_perf_data =3D { + .max_bw_low =3D 5200000, + .max_bw_high =3D 6200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, /* No LLCC on this SoC */ + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 24, + /* TODO: confirm danger_lut_tbl */ + .danger_lut_tbl =3D {0xffff, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +const struct dpu_mdss_cfg dpu_sm6375_cfg =3D { + .caps =3D &sm6375_dpu_caps, + .ubwc =3D &sm6375_ubwc_cfg, + .mdp_count =3D ARRAY_SIZE(sm6375_mdp), + .mdp =3D sm6375_mdp, + .ctl_count =3D ARRAY_SIZE(sm6375_ctl), + .ctl =3D sm6375_ctl, + .sspp_count =3D ARRAY_SIZE(sm6375_sspp), + .sspp =3D sm6375_sspp, + .mixer_count =3D ARRAY_SIZE(sm6375_lm), + .mixer =3D sm6375_lm, + .dspp_count =3D ARRAY_SIZE(sm6375_dspp), + .dspp =3D sm6375_dspp, + .pingpong_count =3D ARRAY_SIZE(sm6375_pp), + .pingpong =3D sm6375_pp, + .intf_count =3D ARRAY_SIZE(sm6375_intf), + .intf =3D sm6375_intf, + .vbif_count =3D ARRAY_SIZE(sm6375_vbif), + .vbif =3D sm6375_vbif, + .perf =3D &sm6375_perf_data, + .mdss_irqs =3D BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF1_TEAR_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 5ef1dffc27dc..7577572a5ef4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -809,6 +809,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_6_3_sm6115.h" #include "catalog/dpu_6_4_sm6350.h" #include "catalog/dpu_6_5_qcm2290.h" +#include "catalog/dpu_6_9_sm6375.h" =20 #include "catalog/dpu_7_0_sm8350.h" #include "catalog/dpu_7_2_sc7280.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 67ff78e7bc99..3d35fcfaf446 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -882,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; +extern const struct dpu_mdss_cfg dpu_sm6375_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 46be7ad8d615..980c3c8f8269 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sc8280xp-dpu", .data =3D &dpu_sc8280xp_cfg, }, { .compatible =3D "qcom,sm6115-dpu", .data =3D &dpu_sm6115_cfg, }, { .compatible =3D "qcom,sm6350-dpu", .data =3D &dpu_sm6350_cfg, }, + { .compatible =3D "qcom,sm6375-dpu", .data =3D &dpu_sm6375_cfg, }, { .compatible =3D "qcom,sm8150-dpu", .data =3D &dpu_sm8150_cfg, }, { .compatible =3D "qcom,sm8250-dpu", .data =3D &dpu_sm8250_cfg, }, { .compatible =3D "qcom,sm8350-dpu", .data =3D &dpu_sm8350_cfg, }, --=20 2.40.1