From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3479FC7EE2F for ; Fri, 19 May 2023 17:05:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231716AbjESRFH (ORCPT ); Fri, 19 May 2023 13:05:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230212AbjESRFD (ORCPT ); Fri, 19 May 2023 13:05:03 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4099C10FD for ; Fri, 19 May 2023 10:04:36 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4effb818c37so3982792e87.3 for ; Fri, 19 May 2023 10:04:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684515874; x=1687107874; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=H1+Xx964Do5+Dd75p0npXtM1tzzF2n1YUbY/5ffcryg=; b=thfkMJlDBO8wgthYMNMUetBmtETMvJPAsYrmS0DzsUWpmfaib4gkM6txQeuc6e4vvv GyytH2+nPXZg2cxeG4fm49g+VOthlvEgjSWV8yeBcWmv9ge/km0/ZRMyeWQzjSLHk4yj QPp+ecXf101QRtMFP39n9kSmcBcLXE3eM+tUHwQrPYdlWPpgccVRQTJO7E1fKQmdFXhz eQBZncbZPwGULUtgUf8FU6OKp3JaTMxGryRy+9d/lMXmuA6HT9u5f1EMfbT2UhGkR7K0 CKkxDT0Qam3x47K4ccxbeLbsyGDOr0MA52V6Ujd70UdmJIaCSiO/jKM6C33b1Cxl6J8Y yoxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684515874; x=1687107874; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H1+Xx964Do5+Dd75p0npXtM1tzzF2n1YUbY/5ffcryg=; b=XF74NClrBD1nzKGh33RH5HaVaoBd8/s/nQlY49NxPqm/Gv7EWz3c/ebIlLfnG9RSlM yyc28vV3lseIzknodZ2xIXtag/VyzhYScJcByL0OfRXQ24HrpH283XWyhlFyZd/b3fHa 8wWvuW5jHrJojfokabWRxpTXbYlAwhcZgF0TM1308dJStbr0R0eiWOzJPtTstP8ZdHHj vZCfv3bBA/Emcoy8Z+8iBZ4rHBrZWzr4eVcA9tPmNHjyArWKu48+fK0fCwI2fZv7qc5P GHS/BDkxl8LaVG28dZtRa7iwWZINDWHLRy8AcMnQTAHb+4FOHNC5IZskkO5Z2e5dO0Ld EiZA== X-Gm-Message-State: AC+VfDw0nFfPjgILaBoL4N50JagwhqewNXBhgYpiFfNW03xIV2jSktOh DWAAwYugYVEzJUbLBSFgrOrX1g== X-Google-Smtp-Source: ACHHUZ4mELS3YoypykXV8iWIlO0eUJnwCCZDBcvHgkxqQ8EOSkqseL8HgLFIlG4jNk1ozEpcxJvN/A== X-Received: by 2002:ac2:5298:0:b0:4ef:eb50:4d3d with SMTP id q24-20020ac25298000000b004efeb504d3dmr1036530lfm.18.1684515874534; Fri, 19 May 2023 10:04:34 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:34 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:22 +0200 Subject: [PATCH v4 01/12] dt-bindings: display/msm: dsi-controller-main: Add SM6350 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-1-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Rob Herring X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=1129; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=+O75/n498bCPQBt/QSpDKi1r6jFyvKeD8W9H7IyUIm4=; b=VMrSRiQHHy1IfOFNgIhJBuew4aa+bzoYEQiURFvzfuY35jhC8ZmvzP63uqDyObnTEPw1tPlJK NjlOaMqNxplC8il/61Rj/Lc3mhX2uSte/tj0u4ArOzMhKezg3GsCLCm X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the DSI host found on SM6350. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2= ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index e6c1ebfe8a32..6f367a1fabf8 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6350-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl @@ -285,6 +286,7 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl + - qcom,sm6350-dsi-ctrl then: properties: clocks: --=20 2.40.1 From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EBCBC7EE29 for ; Fri, 19 May 2023 17:05:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231749AbjESRFL (ORCPT ); Fri, 19 May 2023 13:05:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230517AbjESRFG (ORCPT ); Fri, 19 May 2023 13:05:06 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 102CCE73 for ; Fri, 19 May 2023 10:04:38 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-4f3b337e842so398161e87.3 for ; Fri, 19 May 2023 10:04:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684515876; x=1687107876; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Olp/PVXIJr8fEMjOP3fCHDkSYD0xJnBud5aoQtWwMD4=; b=P9a3mKGxCtfXzLKVP5SAo8qOjOSf2qX1HaGd/cu8Xc9t6oXlMn3jlr7AlPWcfXUcGc uUhl0unwQ+QMiJ6B95v/v6z2cKzszb/5BcyqYLd7UX6POBBNCYBgyiW9RxMBgaN6hejk e5D56a96OYOJrhs0upUZj0VDGFDjlBPbXLW5Zn8C16wqz0mPgyN8kUQ3fqDgk7Namlas HVeSscM5QregjAWpfKtNE+sc6VScflt0U/8InDCjzdAoRKFZyZmym1t93dB0RircufHa bGbO6VyI3Gi0Ao+Ofz035mXiB43bMiH19+BPZ+69ER1Vz9PioKXed9KGziR2h0GuwWKh kjzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684515876; x=1687107876; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Olp/PVXIJr8fEMjOP3fCHDkSYD0xJnBud5aoQtWwMD4=; b=LyLv5ezJwrupVWdZBg83JBwxjtlkeDHigxFu3YRBYs95E+OmCwB0rF/aQ3qKl68lJl vOuFsf4oCoauep1bbV2ugq82XURQDPsI6AMeVNQ3pG9K8vbffWeFykojAcNx4c5dmeVM mMMkICBNU20uhNsmw63/nzOC0o4nWwUs7RDSsr/nS9UbVP/oLIvS9o/jrxOKBnifvhx6 LZm4R4CO/uFy9e/KrkVCGLNvb2cud19Y1dMaeoZZgHwyZ1eDB3x0hsRLEqPHY/gnLr1R psbfEHE5/yCwN7gZFOy2sIIquIHkXGU8yrL8IS6bjGhmCQkj0hMX7Dk39yHbvipXHo23 ZPSA== X-Gm-Message-State: AC+VfDwv3iqLbLMzOoETqaKwStII9xYLTIjUjz64/zln2jEZglt3xCJg FPT8ZMzjuK7RSn2to83abayJiA== X-Google-Smtp-Source: ACHHUZ4IeHr3sqM5Wn5U1+TjNStYTlQDUVag+a9X5qZ3WvOtBOeS4Z5TH4sFCy3lI4XYAyk9EC+kwg== X-Received: by 2002:ac2:4c90:0:b0:4f1:95cf:11eb with SMTP id d16-20020ac24c90000000b004f195cf11ebmr972148lfl.6.1684515876323; Fri, 19 May 2023 10:04:36 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:35 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:23 +0200 Subject: [PATCH v4 02/12] dt-bindings: display/msm: dsi-controller-main: Add SM6375 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-2-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Rob Herring X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=1145; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=VsWoYP7GHCgHOv33piyXwEtJ6/KtKH5SJYQ2EDUVEdo=; b=QPzbrNxaTLE/p9WkBiuxekU0fx4pSTlLLWeihi35wm/6b4DUhAxEznO6YIPT1cqT9vE73a++B KIBa/uP4RVtC4cpGHCHGC0eyloeNuPrCeuqwfmpNxDSXB2Gr7rCN3Yh X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the DSI host found on SM6375. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2= ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index 6f367a1fabf8..f7dc05a65420 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -27,6 +27,7 @@ properties: - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6350-dsi-ctrl + - qcom,sm6375-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl @@ -354,6 +355,7 @@ allOf: enum: - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6375-dsi-ctrl then: properties: clocks: --=20 2.40.1 From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A8CAC77B7A for ; Fri, 19 May 2023 17:05:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231124AbjESRFf (ORCPT ); Fri, 19 May 2023 13:05:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231717AbjESRFH (ORCPT ); Fri, 19 May 2023 13:05:07 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE1C910D4 for ; Fri, 19 May 2023 10:04:39 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-4effb818c37so3982879e87.3 for ; Fri, 19 May 2023 10:04:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684515878; x=1687107878; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NO5fRgfBpga7Z40GIKnv5Lmg/IglAEvXvStQNi4ygG0=; b=Bbdb+1QThMlF638M4Pv9G/iJljUA7x+KqM8jdrVQsDF4imUidG7ALAqVodbIShi3UM 3BP6HsF/5MYh9RSn6zQ6wynq2wfhZjKLvvE36Ow7H2ll+yi2x6N5bS1CqoKd2YxtY/22 62ATGeNmNM6yVKg8r7JCQTN1JTMTc7kGs72gzf9PbJiccXDMtT3KnlhUz/Z212YJoNtf qgutCap1f3InoMPkzkPePQt4DA0nz8deZyxdalH8ACi2vSwmtwaFoINGIZLjnA6ZGZct 0lH16Dtre1Bq2uDq8w6uCTfEt27FE7iubGsTs1f20vFNlI+lDIoO2phnBqQoollyu5AJ SGxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684515878; x=1687107878; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NO5fRgfBpga7Z40GIKnv5Lmg/IglAEvXvStQNi4ygG0=; b=l/8ZkPU0d3KXOTHma+Z/xPXtusIAH7aS9RePhIHVlOhFftT4uA/XomJrAXVdhrJby7 5S2Oe2+gL4CKQQaqBBFhseiN8vn982tmdRCC8wnv/4Q68lw9q7OATXATNWxQFRNRD0DY foV8NysObtAu+WowVEc2hS4S/77HbtbYSddxmkNS9CF7/QwHcQiqWYECkVcW5/Nj6WoZ TprEEHpgvGQD7TBQ0EV6aI9OTyYrgLtSZefSX+YWPNFenPlPwt2vwbftApOtNCEtHxNy v2RYXvEFqhhWw2+pxyNKBeBvQgzb/eytzCI8V7drd08gAmlyQtQv2+OW69b/CN15X3Kd zv4g== X-Gm-Message-State: AC+VfDx0Fw4qUKH6iIgTrU54eYtsKkN4AXfU5NKWocYKnTGjpdT+PNQf NtAeVR7F1E7f/yE752oaCde4zw== X-Google-Smtp-Source: ACHHUZ6pbneutyD2zQncnD7WKo5DHNLnuaD2QVdYjB+RwAqZmitfAl2aZHnLP9npNSJQHFfDJsrcAQ== X-Received: by 2002:ac2:5973:0:b0:4f1:26f5:7814 with SMTP id h19-20020ac25973000000b004f126f57814mr970085lfp.20.1684515878014; Fri, 19 May 2023 10:04:38 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:37 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:24 +0200 Subject: [PATCH v4 03/12] dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-3-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=2117; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=0YTG0EAw+lDImyg5bB4Ke78N5DjTkdTQlY35rQdmXMI=; b=EcOimJs07IbYQ2waHhEPLsH7OslP142E9bndaFUYKcyL2n6tgLHuuW7brAv8TZhjdQaFnDZ3/ 9VabXvrY1UfByI35KRw5KZoGRHacXGXeCjrP4j+ZOfzWFDWDIRsUsZ5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SC7180, SM6350 and SM6375 use a rather similar hw setup for DPU, with the main exception being that the last one requires an additional throttle clock. It is not well understood yet, but failing to toggle it on makes the display hardware stall and not output any frames. Document SM6350 and SM6375 DPU. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sc7180-dpu.yaml | 23 ++++++++++++++++++= +++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml index 1fb8321d9ee8..630b11480496 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml @@ -13,7 +13,10 @@ $ref: /schemas/display/msm/dpu-common.yaml# =20 properties: compatible: - const: qcom,sc7180-dpu + enum: + - qcom,sc7180-dpu + - qcom,sm6350-dpu + - qcom,sm6375-dpu =20 reg: items: @@ -26,6 +29,7 @@ properties: - const: vbif =20 clocks: + minItems: 6 items: - description: Display hf axi clock - description: Display ahb clock @@ -33,8 +37,10 @@ properties: - description: Display lut clock - description: Display core clock - description: Display vsync clock + - description: Display core throttle clock =20 clock-names: + minItems: 6 items: - const: bus - const: iface @@ -42,6 +48,7 @@ properties: - const: lut - const: core - const: vsync + - const: throttle =20 required: - compatible @@ -52,6 +59,20 @@ required: =20 unevaluatedProperties: false =20 +allOf: + - if: + properties: + compatible: + const: qcom,sm6375-dpu + + then: + properties: + clocks: + minItems: 7 + + clock-names: + minItems: 7 + examples: - | #include --=20 2.40.1 From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D85BEC7EE29 for ; Fri, 19 May 2023 17:05:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229954AbjESRFj (ORCPT ); Fri, 19 May 2023 13:05:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231732AbjESRFI (ORCPT ); Fri, 19 May 2023 13:05:08 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9192C10D7 for ; Fri, 19 May 2023 10:04:41 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f122ff663eso3867644e87.2 for ; Fri, 19 May 2023 10:04:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684515880; x=1687107880; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yjN/ffCdIbWuCww9f1G8lkgk4FzsnyMHqREJyrkcTto=; b=KoYvEi6Uul05bf2KvMOgZNpoWvkAe6/aiKndEYfU7JfTkMz5xnqi029Og7MWbL7TZT TLprUNgGF/heeMXSgBJJKv4BWT+s+TTH5R+3gvECdNpqoQperOLbtEhE/U1/D0NdB9FS Y7KPiNo6IrOoW5PkKyh8mNEWkZQoCZzx7ziSOkfP6pcwOSTU34XfOuHxg13d8YGkujc+ NI10JXznkM6E5oOLOPhF/TVA7q2p6hxjEQOE5C6ipO+JIv30DNbOjSuOapXCQ1swVVx6 WO7pCvGm4ZUaD5XUOG/ImgkwZTL5tF8xfOx6n89QZtvuy6hecghVGFNPhhe3ZXxktr1K ERzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684515880; x=1687107880; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yjN/ffCdIbWuCww9f1G8lkgk4FzsnyMHqREJyrkcTto=; b=EUt1SGLbEM8ipwvxwpElfJYqcTVRzq+C4SVYgSUNoOjbTL1deAaLe3yF8oZXkLIXGF aVAnlHCT2W3WUATKsAlTiXSYXW4CPQYRKL+IpxvH+URQgW719n3cOmUfm6EfLvdzZ6Xo Rn9PDtg9Utei43CVcPDdU426vahX0Eu/yGownmZK1rOwnkfYDpF+FNHD3wLqAihLD78O MObpMz0DAi6L5ZVfwZ0paJYswNKn3O2s5PBqGIxJ1H9wTmUAD2HwyVdXtMr4aL3fN62U wc8JQo780gHBQj0KKKHlO4j8Y9EsXIasqRhNREBu+7lEv36vyvHz5Zdre00NPndqCJCv glOA== X-Gm-Message-State: AC+VfDxi+ZAom+Ny5OQn/5JgnYK/EcXTSjVnrqRV+hNOtGr6oCXk70Uh 1WHmk9wkkuDMU/9gxvn8Hjv8DQ== X-Google-Smtp-Source: ACHHUZ52vB/BXHHNJ3kXIEMhdoSlPdWn5w12SAY0Cz4n+quXz0bcxIKwkpll9yumhsNWxApkqe37FA== X-Received: by 2002:a19:7501:0:b0:4f2:5d61:a04d with SMTP id y1-20020a197501000000b004f25d61a04dmr900486lfe.63.1684515879681; Fri, 19 May 2023 10:04:39 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:39 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:25 +0200 Subject: [PATCH v4 04/12] dt-bindings: display/msm: Add SM6350 MDSS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-4-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=7064; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ElBdVsUKD81P73zo0Ep2jls76a+QZxDiuf7z0YpIh/0=; b=Z5v/60ydPUbcxgp1s5N9vJmCEkeeMe8MaTpOWdFvh7gJlF8Gkg4IMvvSN2sYIPbvQjAAgOuxz 1e8zr98M/u0COlFAJIT4GNx9d9Lda1v1OVSwYNWjYK//waL6nopZNle X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the SM6350 MDSS. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +++++++++++++++++= ++++ 1 file changed, 214 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml new file mode 100644 index 000000000000..6674040d2172 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 Display MDSS + +maintainers: + - Krishna Manikandan + +description: + SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6350-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6350-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm6350-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-10nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sm6350-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + power-domains =3D <&dispcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "bus", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x800 0x2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sm6350-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", "iface", "rot", "lut", "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + assigned-clock-rates =3D <300000000>, + <19200000>, + <19200000>, + <19200000>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM6350_CX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SM6350_MX>; + + phys =3D <&dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible =3D "qcom,dsi-phy-10nm"; + reg =3D <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_C= LK>; + clock-names =3D "iface", "ref"; + }; + }; +... --=20 2.40.1 From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4404C7EE37 for ; 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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:41 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:26 +0200 Subject: [PATCH v4 05/12] dt-bindings: display/msm: Add SM6375 MDSS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-5-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=7042; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=s+Spzk/2e7PqcBwMimTOdX5auMNouLwtiaEsT45qphY=; b=56kSBjxUSXN3fkiGrChengeR9znlYezBZ2vSTpLrXvJdUGeVcgs4IhyHJzNRQA+AqKbhprAfT pREWXHCxq10CIllLvxVimL8WzTZdaiy3SDFzXyY4lfYaKubXAGw+CB/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the SM6375 MDSS. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++= ++++ 1 file changed, 216 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml new file mode 100644 index 000000000000..fb56971ea2a1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6375 Display MDSS + +maintainers: + - Konrad Dybcio + +description: + SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6375-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6375-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm6375-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6375-dsi-phy-7nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@5e00000 { + compatible =3D "qcom,sm6375-mdss"; + reg =3D <0x05e00000 0x1000>; + reg-names =3D "mdss"; + + power-domains =3D <&dispcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "ahb", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x820 0x2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@5e01000 { + compatible =3D "qcom,sm6375-dpu"; + reg =3D <0x05e01000 0x8e030>, + <0x05eb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>; + clock-names =3D "iface", + "bus", + "core", + "lut", + "rot", + "vsync", + "throttle"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmpd SM6375_VDDCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible =3D "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x05e94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy= 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmpd SM6375_VDDMX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@5e94400 { + compatible =3D "qcom,sm6375-dsi-phy-7nm"; + reg =3D <0x05e94400 0x200>, + <0x05e94600 0x280>, + <0x05e94900 0x264>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "ref"; + }; + }; +... --=20 2.40.1 From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1810C77B7A for ; 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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:42 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:27 +0200 Subject: [PATCH v4 06/12] drm/msm/dpu: Add SM6350 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-6-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=9657; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=fbAGxdxarCqjbBbVVIDhv+0N+tBnIHACcWCl6GPKK6g=; b=KH0dHx9LJCp5H96JsOfoLUmCKfPiLlKKfq+P5V338RJcChii3qrW/VbMV1+WzRCazH0MBibBQ fYxE7TbSP5WBZWN+FHptv3i4E4shM9I8vyRKW6ejb5uK3YP+io46PEe X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add SM6350 support to the DPU1 driver to enable display output. It's worth noting that one entry dpu_qos_lut_entry was trimmed off: {.fl =3D 0, .lut =3D 0x0011223344556677 }, due to the fact that newer SoCs dropped the .fl (fill level)-based logic and don't provide real values, resulting in all entries but the last one being unused. Signed-off-by: Konrad Dybcio Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 188 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 195 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h new file mode 100644 index 000000000000..5d66a194155a --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_6_4_SM6350_H +#define _DPU_6_4_SM6350_H + +static const struct dpu_caps sm6350_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0x7, + .qseed_type =3D DPU_SSPP_SCALER_QSEED4, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg =3D { + .ubwc_version =3D DPU_HW_UBWC_VER_20, + .ubwc_swizzle =3D 6, + .highest_bank_bit =3D 1, +}; + +static const struct dpu_mdp_cfg sm6350_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0x0, .len =3D 0x494, + .features =3D 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] =3D { .reg_off =3D 0x2c4, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 2= 0 }, + }, +}; + +static const struct dpu_ctl_cfg sm6350_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x1600, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, +}; + +static const struct dpu_sspp_cfg sm6350_sspp[] =3D { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), +}; + +static const struct dpu_lm_cfg sm6350_lm[] =3D { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), +}; + +static const struct dpu_dspp_cfg sm6350_dspp[] =3D { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static struct dpu_pingpong_cfg sm6350_pp[] =3D { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + -1), +}; + +static const struct dpu_intf_cfg sm6350_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MA= SK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_S= C7180_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), +}; + +static const struct dpu_vbif_cfg sm6350_vbif[] =3D { + { + .name =3D "vbif_0", .id =3D VBIF_RT, + .base =3D 0, .len =3D 0x1044, + .features =3D BIT(DPU_VBIF_QOS_REMAP), + .xin_halt_timeout =3D 0x4000, + .qos_rt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_rt_pri_lvl), + .priority_lvl =3D sdm845_rt_pri_lvl, + }, + .qos_nrt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl =3D sdm845_nrt_pri_lvl, + }, + .memtype_count =3D 14, + .memtype =3D {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, + }, +}; + +static const struct dpu_perf_cfg sm6350_perf_data =3D { + .max_bw_low =3D 4200000, + .max_bw_high =3D 5100000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 35, + /* TODO: confirm danger_lut_tbl */ + .danger_lut_tbl =3D {0xffff, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xff00, 0xff00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +const struct dpu_mdss_cfg dpu_sm6350_cfg =3D { + .caps =3D &sm6350_dpu_caps, + .ubwc =3D &sm6350_ubwc_cfg, + .mdp_count =3D ARRAY_SIZE(sm6350_mdp), + .mdp =3D sm6350_mdp, + .ctl_count =3D ARRAY_SIZE(sm6350_ctl), + .ctl =3D sm6350_ctl, + .sspp_count =3D ARRAY_SIZE(sm6350_sspp), + .sspp =3D sm6350_sspp, + .mixer_count =3D ARRAY_SIZE(sm6350_lm), + .mixer =3D sm6350_lm, + .dspp_count =3D ARRAY_SIZE(sm6350_dspp), + .dspp =3D sm6350_dspp, + .pingpong_count =3D ARRAY_SIZE(sm6350_pp), + .pingpong =3D sm6350_pp, + .intf_count =3D ARRAY_SIZE(sm6350_intf), + .intf =3D sm6350_intf, + .vbif_count =3D ARRAY_SIZE(sm6350_vbif), + .vbif =3D sm6350_vbif, + .reg_dma_count =3D 1, + .dma_cfg =3D &sm8250_regdma, + .perf =3D &sm6350_perf_data, + .mdss_irqs =3D BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF1_TEAR_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 9daeaccc4f52..5ef1dffc27dc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -748,6 +748,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_linea= r[] =3D { {.fl =3D 0, .lut =3D 0x0011222222335777}, }; =20 +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] =3D { + {.fl =3D 0, .lut =3D 0x0011223445566777 }, +}; + static const struct dpu_qos_lut_entry sm8150_qos_linear[] =3D { {.fl =3D 0, .lut =3D 0x0011222222223357 }, }; @@ -803,6 +807,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_6_0_sm8250.h" #include "catalog/dpu_6_2_sc7180.h" #include "catalog/dpu_6_3_sm6115.h" +#include "catalog/dpu_6_4_sm6350.h" #include "catalog/dpu_6_5_qcm2290.h" =20 #include "catalog/dpu_7_0_sm8350.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index e9237321df77..67ff78e7bc99 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -880,6 +880,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; +extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 0e7a68714e9e..46be7ad8d615 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sc8180x-dpu", .data =3D &dpu_sc8180x_cfg, }, { .compatible =3D "qcom,sc8280xp-dpu", .data =3D &dpu_sc8280xp_cfg, }, { .compatible =3D "qcom,sm6115-dpu", .data =3D &dpu_sm6115_cfg, }, + { .compatible =3D "qcom,sm6350-dpu", .data =3D &dpu_sm6350_cfg, }, { .compatible =3D "qcom,sm8150-dpu", .data =3D &dpu_sm8150_cfg, }, { .compatible =3D "qcom,sm8250-dpu", .data =3D &dpu_sm8250_cfg, }, { .compatible =3D "qcom,sm8350-dpu", .data =3D &dpu_sm8350_cfg, }, --=20 2.40.1 From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 718F3C77B7A for ; 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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:44 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:28 +0200 Subject: [PATCH v4 07/12] drm/msm: mdss: Add SM6350 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-7-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=1447; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=0D7OZJvsI1VqBAldTbVtRFbwuC+jJW8mAUrMe9Ykcbs=; b=Edt5Xp7SRZ1iyE6ATl12eLjiI68MOV5UFLYk5uc9AM+XQhlc49NQrmgGc+pauw70ZN7LE9jmC sInJIunnVu4D75xYNDmff5gnzX1l3X69wNQARv0fp25ztkR8GTmD7Nt X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for MDSS on SM6350. Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e8c93731aaa1..4e3a5f0c303c 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data =3D { .highest_bank_bit =3D 2, }; =20 +static const struct msm_mdss_data sm6350_data =3D { + .ubwc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D 6, + .ubwc_static =3D 0x1e, + .highest_bank_bit =3D 1, +}; + static const struct msm_mdss_data sm8150_data =3D { .ubwc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, @@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sc8180x-mdss", .data =3D &sc8180x_data }, { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &sc8280xp_data }, { .compatible =3D "qcom,sm6115-mdss", .data =3D &sm6115_data }, + { .compatible =3D "qcom,sm6350-mdss", .data =3D &sm6350_data }, { .compatible =3D "qcom,sm8150-mdss", .data =3D &sm8150_data }, { .compatible =3D "qcom,sm8250-mdss", .data =3D &sm8250_data }, { .compatible =3D "qcom,sm8350-mdss", .data =3D &sm8250_data }, --=20 2.40.1 From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95C70C7EE26 for ; Fri, 19 May 2023 17:05:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231848AbjESRFw (ORCPT ); Fri, 19 May 2023 13:05:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231786AbjESRFR (ORCPT ); Fri, 19 May 2023 13:05:17 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AA3518C for ; Fri, 19 May 2023 10:04:48 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2ac770a99e2so39749501fa.3 for ; Fri, 19 May 2023 10:04:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684515886; x=1687107886; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tfW9/fi5SuuUPxdHMufs3cjpEy23njGDAJML0qW/4gw=; b=g9lXO31s73jB7KfuLGmTG+WenFgPB27fcUGACQVduUKdwWHyLdAwgt2KO/2i/shu5M zhwgJggVw3QU4tmz3xLgSMbUvtAq3ta7USYcUWSPu3FmoUrha7Yv8Ysfh27Wfezw1mHm kZTmGUJYZbq8KncDUTRd+QfRBBWwKGgTpopxCVmVE1aiMr47Awpe/j3XxkVzRntBcoou LrxVeinYqk1ldxOEWmEbPbUozy8zWPCAfYh+UTVKniivNMg1ka0nvWolT7YRD9duGEWJ jelyYjMeRs012hoKVkyE9BNFtdjOxqOZUCcwTETJssH7Dz/1zcqSrnlG362+LIk/Sg2R lRbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684515886; x=1687107886; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tfW9/fi5SuuUPxdHMufs3cjpEy23njGDAJML0qW/4gw=; b=PkFfyXgaiwzKdmOLF0S5ue+tVDXQTgKIX7ZVQuPmqLw3vzQZy2Eawq3LmD1+XtE8HL irwMs3oAZijrjc7jF20qVxXJed/gNRxi7W8iE7yU+fuYRfnxuwh3RPD3u6Z3aV/d52Pf KWXfXoLZVV46K22cSmmvlav/Z5+Mb0k7g22q/BQDwiMV/zSmTi7UsmavM3h8CLMy4w0N wuBjiFd2nucWeve8JlPfU47MvK2KcwozvxTw0cHWMpujilgKjYpx80jt7w+lCe6T5c3Y n/3V7bvw62oFOMVB4Legn3aEA5m6bt9K1xD90GWEPW8Yp6FGAKUC7HcqlOvSNUz68dt6 UF+w== X-Gm-Message-State: AC+VfDz+/QwnFTNJa+FaMgJMEJMefGzs2mv/JDNW3Y6jp7W2VZnq5g+A WAnd2r1SKMI9hQ+nyjSUtjmEZQ== X-Google-Smtp-Source: ACHHUZ5ufiivw7E7r2k2D3mv7AvA+TMAQZpnElA8lJTlXNqYvOZEbsI4TSzI/jQcM4ueq2X1clxfzg== X-Received: by 2002:ac2:4846:0:b0:4dc:8192:c5e6 with SMTP id 6-20020ac24846000000b004dc8192c5e6mr925066lfy.13.1684515886548; Fri, 19 May 2023 10:04:46 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:46 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:29 +0200 Subject: [PATCH v4 08/12] drm/msm/dpu: Add SM6375 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-8-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=7490; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=EHCd7rxYqWd4K8OPe4c07JXBY+0m2epxbCjM8CCGMoY=; b=n9BgwFD6kAjQ1kAJZhJd/Mi/ZmNCjOKjrADL1DnfhIgJyCNHX5IxkcbuWW2IVAxJFhZPhTIgG H7f0R8q0ZLTAfDN65F7kBHbYv5Jz1r3GBo7ToZpYOW/7p2dh+5HUv72 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add basic SM6375 support to the DPU1 driver to enable display output. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 153 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 156 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h new file mode 100644 index 000000000000..5085e7409ff6 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_6_9_SM6375_H +#define _DPU_6_9_SM6375_H + +static const struct dpu_caps sm6375_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages =3D 0x4, + .qseed_type =3D DPU_SSPP_SCALER_QSEED4, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D 2160, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg =3D { + .ubwc_version =3D DPU_HW_UBWC_VER_20, + .ubwc_swizzle =3D 6, + .highest_bank_bit =3D 1, +}; + +static const struct dpu_mdp_cfg sm6375_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0x0, .len =3D 0x494, + .features =3D 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + }, +}; + +static const struct dpu_ctl_cfg sm6375_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, +}; + +static const struct dpu_sspp_cfg sm6375_sspp[] =3D { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), +}; + +static const struct dpu_lm_cfg sm6375_lm[] =3D { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, + &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), +}; + +static const struct dpu_dspp_cfg sm6375_dspp[] =3D { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sm6375_pp[] =3D { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), +}; + +static const struct dpu_intf_cfg sm6375_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0), + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_S= C7280_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), +}; + +static const struct dpu_vbif_cfg sm6375_vbif[] =3D { + { + .name =3D "vbif_0", .id =3D VBIF_RT, + .base =3D 0, .len =3D 0x2008, + .features =3D BIT(DPU_VBIF_QOS_REMAP), + .xin_halt_timeout =3D 0x4000, + .qos_rp_remap_size =3D 0x40, + .qos_rt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_rt_pri_lvl), + .priority_lvl =3D sdm845_rt_pri_lvl, + }, + .qos_nrt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl =3D sdm845_nrt_pri_lvl, + }, + .memtype_count =3D 14, + .memtype =3D {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, + }, +}; + +static const struct dpu_perf_cfg sm6375_perf_data =3D { + .max_bw_low =3D 5200000, + .max_bw_high =3D 6200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, /* No LLCC on this SoC */ + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 24, + /* TODO: confirm danger_lut_tbl */ + .danger_lut_tbl =3D {0xffff, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +const struct dpu_mdss_cfg dpu_sm6375_cfg =3D { + .caps =3D &sm6375_dpu_caps, + .ubwc =3D &sm6375_ubwc_cfg, + .mdp_count =3D ARRAY_SIZE(sm6375_mdp), + .mdp =3D sm6375_mdp, + .ctl_count =3D ARRAY_SIZE(sm6375_ctl), + .ctl =3D sm6375_ctl, + .sspp_count =3D ARRAY_SIZE(sm6375_sspp), + .sspp =3D sm6375_sspp, + .mixer_count =3D ARRAY_SIZE(sm6375_lm), + .mixer =3D sm6375_lm, + .dspp_count =3D ARRAY_SIZE(sm6375_dspp), + .dspp =3D sm6375_dspp, + .pingpong_count =3D ARRAY_SIZE(sm6375_pp), + .pingpong =3D sm6375_pp, + .intf_count =3D ARRAY_SIZE(sm6375_intf), + .intf =3D sm6375_intf, + .vbif_count =3D ARRAY_SIZE(sm6375_vbif), + .vbif =3D sm6375_vbif, + .perf =3D &sm6375_perf_data, + .mdss_irqs =3D BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF1_TEAR_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 5ef1dffc27dc..7577572a5ef4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -809,6 +809,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_6_3_sm6115.h" #include "catalog/dpu_6_4_sm6350.h" #include "catalog/dpu_6_5_qcm2290.h" +#include "catalog/dpu_6_9_sm6375.h" =20 #include "catalog/dpu_7_0_sm8350.h" #include "catalog/dpu_7_2_sc7280.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 67ff78e7bc99..3d35fcfaf446 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -882,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; +extern const struct dpu_mdss_cfg dpu_sm6375_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 46be7ad8d615..980c3c8f8269 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sc8280xp-dpu", .data =3D &dpu_sc8280xp_cfg, }, { .compatible =3D "qcom,sm6115-dpu", .data =3D &dpu_sm6115_cfg, }, { .compatible =3D "qcom,sm6350-dpu", .data =3D &dpu_sm6350_cfg, }, + { .compatible =3D "qcom,sm6375-dpu", .data =3D &dpu_sm6375_cfg, }, { .compatible =3D "qcom,sm8150-dpu", .data =3D &dpu_sm8150_cfg, }, { .compatible =3D "qcom,sm8250-dpu", .data =3D &dpu_sm8250_cfg, }, { .compatible =3D "qcom,sm8350-dpu", .data =3D &dpu_sm8350_cfg, }, --=20 2.40.1 From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 578A3C7EE26 for ; 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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:47 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:30 +0200 Subject: [PATCH v4 09/12] drm/msm: mdss: Add SM6375 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-9-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=1022; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Nh6zuYJI8gb14gxje6MmS/hbQSaIA3Eeoi75EfztoC0=; b=/pMrarazssUBtmCWEJL265R5eOk52S2hT5NCFLEOgy3OcU68alhIDf6GZOKfsmwEYREtA9PnC 3lHdg+kJJDpD8+XJHXM3lAGm5+ON8x3yE8xQscNI3jK0RVLFnOZRWGl X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for MDSS on SM6375. Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 4e3a5f0c303c..05648c910c68 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -580,6 +580,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &sc8280xp_data }, { .compatible =3D "qcom,sm6115-mdss", .data =3D &sm6115_data }, { .compatible =3D "qcom,sm6350-mdss", .data =3D &sm6350_data }, + { .compatible =3D "qcom,sm6375-mdss", .data =3D &sm6350_data }, { .compatible =3D "qcom,sm8150-mdss", .data =3D &sm8150_data }, { .compatible =3D "qcom,sm8250-mdss", .data =3D &sm8250_data }, { .compatible =3D "qcom,sm8350-mdss", .data =3D &sm8250_data }, --=20 2.40.1 From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA126C77B7A for ; Fri, 19 May 2023 17:06:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231937AbjESRGD (ORCPT ); Fri, 19 May 2023 13:06:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231804AbjESRFS (ORCPT ); Fri, 19 May 2023 13:05:18 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC2A61A1 for ; Fri, 19 May 2023 10:04:51 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4f26f437b30so3998202e87.1 for ; Fri, 19 May 2023 10:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684515890; x=1687107890; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ppRfvpEzKntx7DzSp5zW1I4Fc3JFfOMmEmtjxYhv2RE=; b=yZnkjyb5A5MRZrT7msho2TdEwx8Dqmdl0B1+Qt4i0PJCAiv4bnobpVDzlvnIruQItB XoCu4xG7Nfjv6Z6peYj61vwsgk6ofiR9alcV2/ycEaRC7ad5mDya5hHfrppcyWByinZq Tdr8+/XFuoSzn9gqR9msSt/y4LV3NbvRxhkEvBMmBmVh0nxee1rmWW0A3KIXeJxHPwrI bw0Ekg4Kmpz+N51bdOzZ7fYK+WcSAU3TgkiZ9tYYOmRI373nTnzP9VTNRR3HD0e+ZIIC jj2phM+S8mpheHMTyL1u1iyLkmRmZrD45qSRacNHX0C3wVdiqRc8YlvGpvxf0i6TZFT1 DKEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684515890; x=1687107890; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ppRfvpEzKntx7DzSp5zW1I4Fc3JFfOMmEmtjxYhv2RE=; b=lPR1aCFXDF58JulSXKTE8/AqVuO7nvroOWTvFbALabiboy96HnoytDJLj8svGtDXwE 6qbPxQLYnihhuZECIjfv2tXjAMhOdRtf0w/KgitkNPFd/LopkoIPCTKW9y/EiE4GJ3b7 tziWDJP5yVQQlJ1aUdYuYm2A495Tc/O++QcqkyUar5DFispXgS6bsyCSlcjf6bOo+OF9 K7EcrjMTvtDb21mghwFZvF21y3DOHbzNQJkExL1LwN9zKv3lmgTI8iJHdKV4Wel69Tpf 4iAUpl5nVowTDz6DEvFYHXnOYLWLnuQJjWxEFcg9Lkqji3JremzQpFizD8o/5xNRadmF lV1A== X-Gm-Message-State: AC+VfDy/4uKSyO8ZQyiFiy7SP81sKBRr1+agi/f7FUqLNRUiqz0wDspe gvToG+NQiMcZBV/jnjRITWN1GQ== X-Google-Smtp-Source: ACHHUZ4SdkxsWCzkHrPg/XhlGeB08jcKZiy+JJ8XYc5WTrd/LY7hhcZRCk5LoKthWwvQR4nh+Dy3Ww== X-Received: by 2002:a19:f002:0:b0:4ea:fa07:1182 with SMTP id p2-20020a19f002000000b004eafa071182mr945077lfc.14.1684515889909; Fri, 19 May 2023 10:04:49 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:49 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:31 +0200 Subject: [PATCH v4 10/12] iommu/arm-smmu-qcom: Sort the compatible list alphabetically MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-10-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=965; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9/++xt/utIOxLufVN9PZF2yMVmu78Xo8NRamuKy95SI=; b=IFT0R7GXWdOBF7o2llf/YR7q+v6c4wSJLLLXlQkT78L1b6w2wlyTtawVoAyaEvOvNO+cpgEI2 iipx+WNKFSmADcnC6AgQgDR56IjlTcRn+t3vjytXV8Fupw7JEsRLp4i X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It got broken at some point, fix it up. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index ae09c627bc84..f945ae3d9d06 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -251,10 +251,10 @@ static const struct of_device_id qcom_smmu_client_of_= match[] __maybe_unused =3D { { .compatible =3D "qcom,sc7280-mss-pil" }, { .compatible =3D "qcom,sc8180x-mdss" }, { .compatible =3D "qcom,sc8280xp-mdss" }, - { .compatible =3D "qcom,sm8150-mdss" }, - { .compatible =3D "qcom,sm8250-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, + { .compatible =3D "qcom,sm8150-mdss" }, + { .compatible =3D "qcom,sm8250-mdss" }, { } }; =20 --=20 2.40.1 From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA9C7C7EE29 for ; Fri, 19 May 2023 17:06:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231892AbjESRF6 (ORCPT ); Fri, 19 May 2023 13:05:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231815AbjESRFT (ORCPT ); Fri, 19 May 2023 13:05:19 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 418641A7 for ; Fri, 19 May 2023 10:04:53 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-4f3b314b1d7so421700e87.1 for ; Fri, 19 May 2023 10:04:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684515891; x=1687107891; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6Cgx0VgjSWF36kTiyIdxe2LPUi4kT2lQKkyyJC5x69s=; b=IsY0da0u/JDDGZ3J9pfUfxvXvYtnLy1D+JtipBNPvBMtbtDtTz7HNBPcotwGkAmlfy PORzwnfF1eE1o74F4V53MF8I4B6xYtH+/1Qeh3ai0UEn3Jbg7koeCdcgjxciv4skpxKK Dd+OZTmBUhedVkMuG9TyM9xC6Tdma/4p8vFJNPL5zQJAICD7bqgmefISwx9CqL5EPLXd D4Nr8+FEO4bgOpv3+Xfx91X+dElds3dF083I77oRfdnjU5BfyOe6J+CN2+/rZxk+h23n Naxe+XT5eXF+9OG41/F/kawP49Vretx4AX4CFfC5mqxpFEdDmR9enO1+5bcPInK1F/k4 j2XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684515891; x=1687107891; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Cgx0VgjSWF36kTiyIdxe2LPUi4kT2lQKkyyJC5x69s=; b=FQyqpboXEifoa1MU1ZPSxDP7LSfgdaqWCmxFeo7RxmS30UZ7LLD3ttksHuYKiNYSDQ nBarlMRMM5efwjFWzjSy/80i/B/gViPVWyPDgELX0mNX8EtV2M8zXn5I278YH5ENUIVr hkmjW1DpMaG3viOv8/ezWTzmxy5p7gcX+X6g2t8jFAxRIfrWgDQzOGeCqY8BAxpKrHwn p+U6XRtZtZGvLu9n9aYetVZgmkTN9rG+5IGM0QehvAinFbQbi9rGDkI1GVK3QRMdHDCu fM+2zjJEvnDxR7gP6n71aspqkOIeC+bFX+SY3alY8yuhej68S5F7XCjs69Hg3yjMFEuc rjXw== X-Gm-Message-State: AC+VfDz1CcyutsR2p5EcQF4Z0N4de5QT+J1kmfxKJWhr5AB4RLyXIhYb 09jursX3glTdjJajEo5dnx99XA== X-Google-Smtp-Source: ACHHUZ7Ds1+/AWoTFgM3T6UfzCXKF2mivsVSYkyWxs5tAN5cNPFGwbnFQ0oWsighigcXlZcHgEYaQA== X-Received: by 2002:a19:f00a:0:b0:4eb:42b7:8c18 with SMTP id p10-20020a19f00a000000b004eb42b78c18mr963212lfc.53.1684515891515; Fri, 19 May 2023 10:04:51 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:51 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:32 +0200 Subject: [PATCH v4 11/12] iommu/arm-smmu-qcom: Add SM6375 DPU compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-11-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=919; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hMmDD+SgonZLP46KBM866xQojXqpPqEZ25ow2fxLp/E=; b=R5FoZY4Lqorac7OGiiU0hCgTpb7/pGRuboSGxvm7lhbIzQY6O4CtC/NrOwAerHytiT6x+EkhV M+R6OmHtCA7AQ3JrOawU6BYsdkdEV6mk6MgjQ/tb3RtgeGijwLddrRa X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the SM6375 DPU compatible to clients compatible list, as it also needs the workarounds. Acked-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index f945ae3d9d06..d7d5d1dbee17 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -253,6 +253,7 @@ static const struct of_device_id qcom_smmu_client_of_ma= tch[] __maybe_unused =3D { { .compatible =3D "qcom,sc8280xp-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, + { .compatible =3D "qcom,sm6375-mdss" }, { .compatible =3D "qcom,sm8150-mdss" }, { .compatible =3D "qcom,sm8250-mdss" }, { } --=20 2.40.1 From nobody Mon Feb 9 00:46:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA011C7EE2D for ; Fri, 19 May 2023 17:06:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230397AbjESRGG (ORCPT ); Fri, 19 May 2023 13:06:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231837AbjESRFT (ORCPT ); Fri, 19 May 2023 13:05:19 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F06C10F0 for ; Fri, 19 May 2023 10:04:55 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2af2b74d258so251521fa.3 for ; Fri, 19 May 2023 10:04:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684515893; x=1687107893; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KKTw5Zfw+dKxxnY8fd/tof/aQPft5PObVsbIBwm4nOE=; b=z3yvfQ4KllCaIiBPBzGr9FG7c5sdwTiPqU6aglyOS4rJihClrvueBLtwUcEXnJTQhE KlBTPqEwHR5um1+ryteThNBiq3Kv3LgHLa8HPLErzzMrUm+2kKOBMLyqJNnVrN+8dKEY 3m3pTPxnqWLSpGlNWegJTsWft6XfG0P1wCxfXxjqXzgqd0catmm3Ku0GmWczouxrKs/y 2LH8VuuUaOSrNDmFbiHZ6rp3jxyNtSRD97xY2lflSuVPUdm166+HMvBXLEgxL1ia4/Bw UFDEIicCYwh0FLE1ePZv5oMLb9U5k/hMD6Es+M4rCtTnjsJh9iRUzJ/mLPMtf4nZBmJk rtWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684515893; x=1687107893; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KKTw5Zfw+dKxxnY8fd/tof/aQPft5PObVsbIBwm4nOE=; b=Klrh4stnXLp4m1fAnMLgjUZ4EKNAqaNlWZQuXtfC/6f9HYW+HoP1ogvLQbdgB3HrwL 5DPx066oq1BERM3rZ1V/P6SvySFqJYEprqd3hHZNPn6KbbDhuBGD+coHUqEzwOK8MfiD piyBsrcCOwSOgSJCNO78HS+DeQYnZuZFkoJyvndP4fNtekMyJyRkH/sHzuUNJA5Lk+0W 7brNnNSZ28kAanjzmzxqX9BRZSxYXIfFWmGwTuganjWq5IFFq/tQQGAJnWwWDbMuXLxu LxBXBLpFgdh68GY0mtcN9pTO/8nBplipGnc9DFIq4fIi+I0mqUQ5FvlUZpLCKVsx83Z1 jpow== X-Gm-Message-State: AC+VfDzyrikFRWpfemdUlWq3T9A94EWtbjQFgP6chQENornqvBFCQeDW c53CxY7d70XSPPBQY5kZGP1VLQ== X-Google-Smtp-Source: ACHHUZ6hb+9tW9dZymi1gZLakhlpllRE71/FgqhEmtf6uNPbPo+mBDJ1VJEFHKSoSos09di8OsIesQ== X-Received: by 2002:a2e:3213:0:b0:2af:1eee:84af with SMTP id y19-20020a2e3213000000b002af1eee84afmr1168912ljy.26.1684515893318; Fri, 19 May 2023 10:04:53 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id a6-20020a19f806000000b004f38260f196sm654478lff.218.2023.05.19.10.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 10:04:52 -0700 (PDT) From: Konrad Dybcio Date: Fri, 19 May 2023 19:04:33 +0200 Subject: [PATCH v4 12/12] iommu/arm-smmu-qcom: Add SM6350 DPU compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v4-12-68e7e25d70e1@linaro.org> References: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v4-0-68e7e25d70e1@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684515870; l=1014; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=d3S3xhOuliIdaa9KoHmUn1yxgnvenr1zId8Sw3Pr4Gg=; b=ihwHwr0j8S4l2zwqo/DbkiQez0VWcdnrFgJZGS+0sED5bEZluFPe94qSoPP/csG4/zAKv0PiV fDngCeGT1ZID8bR3q1gXI/bL59YYGxIww0TnxuHMyLWg2Di1qBia5nL X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Konrad Dybcio Add the SM6350 DPU compatible to clients compatible list, as it also needs the workarounds. Signed-off-by: Konrad Dybcio Acked-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index d7d5d1dbee17..e64c737724c4 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -253,6 +253,7 @@ static const struct of_device_id qcom_smmu_client_of_ma= tch[] __maybe_unused =3D { { .compatible =3D "qcom,sc8280xp-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, + { .compatible =3D "qcom,sm6350-mdss" }, { .compatible =3D "qcom,sm6375-mdss" }, { .compatible =3D "qcom,sm8150-mdss" }, { .compatible =3D "qcom,sm8250-mdss" }, --=20 2.40.1