From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3C43C77B7F for ; Fri, 5 May 2023 21:41:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233634AbjEEVlm (ORCPT ); Fri, 5 May 2023 17:41:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233626AbjEEVlh (ORCPT ); Fri, 5 May 2023 17:41:37 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF23159DD for ; Fri, 5 May 2023 14:40:44 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2ac8c0fbb16so10641921fa.2 for ; Fri, 05 May 2023 14:40:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683322843; x=1685914843; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=H1+Xx964Do5+Dd75p0npXtM1tzzF2n1YUbY/5ffcryg=; b=mGExL8SrQ5XCe3yqvDTrnGVkTIhBUhG8YPsyQ1/e/44Q3cEhZJ1/08XjzeuiRUyQD6 M7LB6Ez57o3AzvLFjeyAWMJALzYXdNP5M+2jminPeixrUPikkepbM+Bm56WqlLmrBYfw xKPWLHO6S0mh/OQ30sBadObt6s1ZrWJldEJ5AiUbHKsECbbpI1IdFDU+3k8vdctN9mBE SG9OPTHzZjUZY+VcadBG3WVZvfW0b26y9XZhml/nM1KrjY7pd5EcHbn90zlgmvZQEHKY QnGsUU3nMC72ua2pgZZ2l2gEKdrQfbjYoR+3X7r9uojNgEerTz0gxTkVc2hX0l8wKsfl Sd6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683322843; x=1685914843; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H1+Xx964Do5+Dd75p0npXtM1tzzF2n1YUbY/5ffcryg=; b=fs4h0FLx41+7PlggjYN0dD1GlW98MLDU6lIc09W2uyrQjniG5+a5OFpAzxw3j2KWWF dJd1/1bxakZJhXCLXORtWqQrmZi2NHtyKUU/F1dF1u3z16Zcd7uJUKnORmyg+YbHiEPk gwmCLWA1bCTedtNQV40t8IG2c5YXjhMMlLUb5IWD1MlpUAA5E9pB1JJ1u1aHMRTHD0dL 4BmdEGmqqbSMf4wFyNWlQiuu6xiEVDML0+lhI7aCz6hSDh8M02XboLudAhgWjOLweVJT Sc15qxpe1bTKeaklQNK2+w0rOR7V/ybxiCBOVKf0B8rfTr3wP3HEoe1pxlLL0AlDGz8c lIWw== X-Gm-Message-State: AC+VfDwEtYCO+4QQLOCSTed+aZkXcDigHFT/59r5ozX2IrWc5QsUtf53 kv54Lo7sEyP2K/KQ6+ZB8JQAUw== X-Google-Smtp-Source: ACHHUZ7dbutd62hVffBmQka6SJs8tp9PNCSqis8xhLAT3IIrAmJco8X7JFwSYcMQzrd1Segejocbug== X-Received: by 2002:a2e:9202:0:b0:2ac:7a77:1d4e with SMTP id k2-20020a2e9202000000b002ac7a771d4emr790219ljg.24.1683322843242; Fri, 05 May 2023 14:40:43 -0700 (PDT) Received: from [192.168.1.101] (abyl248.neoplus.adsl.tpnet.pl. [83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:40:42 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:27 +0200 Subject: [PATCH v3 01/12] dt-bindings: display/msm: dsi-controller-main: Add SM6350 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-1-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Rob Herring X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=1129; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=+O75/n498bCPQBt/QSpDKi1r6jFyvKeD8W9H7IyUIm4=; b=H5Kkgj24gPlGZUMzlH7o48hrPaPJDKbNQlfIh6lS7Er20KgpF2LUCpCvwkInzjXJDZ0bDJ9aS 6QteD0gUYBmCf9xOsDUgvrXBc64n/3AF6qfnUgjhKnmSXHBb+EfyOrm X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the DSI host found on SM6350. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2= ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index e6c1ebfe8a32..6f367a1fabf8 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6350-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl @@ -285,6 +286,7 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl + - qcom,sm6350-dsi-ctrl then: properties: clocks: --=20 2.40.1 From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44A1AC77B7F for ; Fri, 5 May 2023 21:41:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233671AbjEEVlq (ORCPT ); Fri, 5 May 2023 17:41:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233629AbjEEVlh (ORCPT ); Fri, 5 May 2023 17:41:37 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C499459ED for ; Fri, 5 May 2023 14:40:46 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2ac770a99e2so25626681fa.3 for ; Fri, 05 May 2023 14:40:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683322845; x=1685914845; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Olp/PVXIJr8fEMjOP3fCHDkSYD0xJnBud5aoQtWwMD4=; b=bcyb7PU+mB0xuZcC98A3z4xrQTA4cCO9fBd6WOSZ4BXU+qSJ1uguBXdCQkKkfa1qOG tz29LlHe+jDhfBGEkFjUPX0kG/zMnGQdZaUbfQGKVC24x4niiJcGNPPWgl7i8TZEGNgy zKaTUKwGCrCIiCDNEutlCwoHmLJVBCSeUhO+emE5U24E0omFmV1YfVxmBKvL5bsPsNb/ CvU5JYSMOwJrZmG3cpVKwpR/DwiFu6t/cGXEaeJzn/dSt0Glh6iKohWshJo9Q21rz8DN vmzfXNbcmz8axbxYCWdVpFDXPsbEUSf3l2CUlGgX6r3WJ1n0PqpnxZs7iJ2vu3RlcxlH j+5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683322845; x=1685914845; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Olp/PVXIJr8fEMjOP3fCHDkSYD0xJnBud5aoQtWwMD4=; b=YfYT3ey++ikKX5xjobexXr3s4/3zfAqx7MZi2vES1UaTe0oKUwFVK5VK10dZ5Cr1ab F8w7qZE3iVd/4nNpUTAFV2rfKHJQrjfRigRNo1CHc61AHQVwUUv9WgxWv9AEngL2rXx0 5k1z+BxSBT4xfPyfBVXXt/KMVHdkUekoZTdUIkuCHU8w2v15rYtwzouLB+vckDK9AIwN K7S0XCnbE9S7oNOClsnI8ijv4fP/IPNhO8m4cDiauY+1oNBFMti4AMeT5/ssslxZODPX qHjYo5o3I1e1ObWzQB+/EbvEhPTxfGhSLsLVSsEkJdGWet83XUNfM1wZVYTILUj0lL1J oHaQ== X-Gm-Message-State: AC+VfDyFCcEO45KDzdJzxKSse+1knGqKZ/BTg8TWWnKeWFEuZAkqLgyP /BrQErf3APG9KV0QqBNjwYCagg== X-Google-Smtp-Source: ACHHUZ4gXaB+RYZgmcooayAAK8tmsa/H8nYRTCwojYzNiGeovBEiytzLG1KPmci+aNtG4Z3ZdQlYPQ== X-Received: by 2002:a2e:8815:0:b0:2a8:bf35:3b7 with SMTP id x21-20020a2e8815000000b002a8bf3503b7mr821445ljh.32.1683322845019; Fri, 05 May 2023 14:40:45 -0700 (PDT) Received: from [192.168.1.101] (abyl248.neoplus.adsl.tpnet.pl. [83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:40:44 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:28 +0200 Subject: [PATCH v3 02/12] dt-bindings: display/msm: dsi-controller-main: Add SM6375 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-2-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Rob Herring X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=1145; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=VsWoYP7GHCgHOv33piyXwEtJ6/KtKH5SJYQ2EDUVEdo=; b=+3R0ILIrXzT82PWwbsl52w/wP4I53hpnomknSN5Kg5vAI7isrjcQm4SRnGPHieDAD+1Jm6gke 4m7bCcjT25dAP6HBg9UzJaX/QBj7wkbo8MX8s82R3DQp7aHegBP1CeB X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the DSI host found on SM6375. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2= ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index 6f367a1fabf8..f7dc05a65420 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -27,6 +27,7 @@ properties: - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6350-dsi-ctrl + - qcom,sm6375-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl @@ -354,6 +355,7 @@ allOf: enum: - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6375-dsi-ctrl then: properties: clocks: --=20 2.40.1 From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 025C7C77B7C for ; Fri, 5 May 2023 21:41:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233679AbjEEVlw (ORCPT ); Fri, 5 May 2023 17:41:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233631AbjEEVlh (ORCPT ); Fri, 5 May 2023 17:41:37 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E5FC5B89 for ; Fri, 5 May 2023 14:40:48 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2ac7462d9f1so26312371fa.2 for ; Fri, 05 May 2023 14:40:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683322847; x=1685914847; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NO5fRgfBpga7Z40GIKnv5Lmg/IglAEvXvStQNi4ygG0=; b=rsLrKdrhy2a2Rdz5SOu60AlU7/txqFbmO0OQH8+ltM/lW7FX9rbeTouQ6vJyl0+RiU p1HId9R0wqX8PyhheHxe6biuExlNfHhvZ8CMrCNOBbszxA5K9rCKzn4xoSOkDxhG2Kox 2Uh5EiLbpL0ZGmx4MkXpriy0J83Hq6im4kmOzEMn/+mkfjorCpGTiJJ+JvizLOhmJUQB KMjdQv+81CtZJRmo4scmg0KiajwCfaY/1LD84lkq348SripmPGITWsY48s4Gr3B+1no0 jElDpJzebopdjfEuTKiUlorIhOOhyUqQ1d1NNWxXQ35SLSMh//ekq//SfxdMb+VGUr8Y iXiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683322847; x=1685914847; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NO5fRgfBpga7Z40GIKnv5Lmg/IglAEvXvStQNi4ygG0=; b=bRzJrjxqnehDd/b9KyN4dDKSbahV5Aov/to34+NODucI/3gRn6PA6T9tthaz8M425n 8u0+qsbTbfkxN0Y1li7YqLAl9VbelhVNuVlSVPyZYu7I5yy6ZVSwq3ijo3LYsdIRJpRC 7YS0hKSteW76RYePouOmUWdIcGgIu6bH7/WauU3sc4H76aCILUuzUz8ADH8ZXXqFmn3c Axu6dws39ZkLSQTEsnVlx5vAqZFlnXhGhsDqcezdTHfvi9eOSQ2Cko4JvpCVjysUI9yY /71JwVxKb5NErwxmEJHM2lMoW3+KVtFWZJuDydrQ6RlxDBMojAutL9/xpLtJJ4B/vfOm tlbA== X-Gm-Message-State: AC+VfDxM2kXxn4e2FymbJ5qWCE2Ec6n1GYJc1yoqg4CIAkOIEvLi9cAv UNG1le/v7O9yYokDVkBDiiVU8A== X-Google-Smtp-Source: ACHHUZ4gXeCJE4zlDMMHxTrHrsNhicdcqhAMyXIpqTGgh3AleIuYXLThx3eNJjWiq9OkwNC2MIBVIA== X-Received: by 2002:a2e:c52:0:b0:2a8:c374:c0f2 with SMTP id o18-20020a2e0c52000000b002a8c374c0f2mr914494ljd.42.1683322846941; Fri, 05 May 2023 14:40:46 -0700 (PDT) Received: from [192.168.1.101] (abyl248.neoplus.adsl.tpnet.pl. [83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:40:46 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:29 +0200 Subject: [PATCH v3 03/12] dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-3-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=2117; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=0YTG0EAw+lDImyg5bB4Ke78N5DjTkdTQlY35rQdmXMI=; b=klLfGuhE6s72yhtk0LTrI5AIStLgGemG4Bbu3dYCHWIq3DabAQyTXOmCql9t0a70N13bG4Qk8 2aXq/aWxoCqBMDTNWXPK0q3mCrWZdN+WYlos93WAVJtJZRjvr17jIOl X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SC7180, SM6350 and SM6375 use a rather similar hw setup for DPU, with the main exception being that the last one requires an additional throttle clock. It is not well understood yet, but failing to toggle it on makes the display hardware stall and not output any frames. Document SM6350 and SM6375 DPU. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sc7180-dpu.yaml | 23 ++++++++++++++++++= +++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml index 1fb8321d9ee8..630b11480496 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml @@ -13,7 +13,10 @@ $ref: /schemas/display/msm/dpu-common.yaml# =20 properties: compatible: - const: qcom,sc7180-dpu + enum: + - qcom,sc7180-dpu + - qcom,sm6350-dpu + - qcom,sm6375-dpu =20 reg: items: @@ -26,6 +29,7 @@ properties: - const: vbif =20 clocks: + minItems: 6 items: - description: Display hf axi clock - description: Display ahb clock @@ -33,8 +37,10 @@ properties: - description: Display lut clock - description: Display core clock - description: Display vsync clock + - description: Display core throttle clock =20 clock-names: + minItems: 6 items: - const: bus - const: iface @@ -42,6 +48,7 @@ properties: - const: lut - const: core - const: vsync + - const: throttle =20 required: - compatible @@ -52,6 +59,20 @@ required: =20 unevaluatedProperties: false =20 +allOf: + - if: + properties: + compatible: + const: qcom,sm6375-dpu + + then: + properties: + clocks: + minItems: 7 + + clock-names: + minItems: 7 + examples: - | #include --=20 2.40.1 From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36E71C77B7C for ; Fri, 5 May 2023 21:41:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233681AbjEEVl4 (ORCPT ); Fri, 5 May 2023 17:41:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233435AbjEEVli (ORCPT ); Fri, 5 May 2023 17:41:38 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58A905B95 for ; Fri, 5 May 2023 14:40:50 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2ac733b813fso25613361fa.1 for ; Fri, 05 May 2023 14:40:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683322848; x=1685914848; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yjN/ffCdIbWuCww9f1G8lkgk4FzsnyMHqREJyrkcTto=; b=o3bmL0A/XXD6ZM+q+PQjSyG6FcbmWE9R1XVMmmKM4NukACHyRpMYdFzZFo541m+QRe u2colS2SXaXQmXwuNBJPSE+1hA6D971Z2gW1bFZ8PX8wqyXhJ6v/WxgX3Scf5hJDLF16 KBNP7a74Nq916PzaF0eotz8hfIB+UZuzjDtcjdqFTSvIOl9yN0a2dR+DCTJWNbI4/PC8 Syluh51Fll/ezPQsHevBpqgcPJG6qGzPG4u1nNXti0qfmv8/qzEoDJ+4QmKa0jbCa9nT SGXM0UR6FQN7vbxYpPcJtduwIy1onqj4XnrAXxCruUoEDY5Ob/0S1jNUOB79mQ4aLhEZ l7ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683322848; x=1685914848; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yjN/ffCdIbWuCww9f1G8lkgk4FzsnyMHqREJyrkcTto=; b=Y81Tbt4oG909PtV7+WER3YwAo8Y0qHNXyERBZyd6FzNYVVeQeTetqGQOB8rcoH5t/J j9YYBk0GxT1jThHmXipoiAJTywfrZzlRKXGlrf0qr76d9OgUZDqipKGu+xroPakl3CR3 JCRdJasqCld50NaK/TIZeyrQNQqBc5my7HtSVMLHnaYkpEMptEultZLUquRPJp1HYzHM EB1BakDfwZNiJo7o6KWsOEp+SmMHGo/tMNxNWlBkgLtKDVOBKSxbOBOnfXjkaIe9ar09 IYVT0n+opwBaiC1u5B3ZyoEEID5fHNsnXVxMzuBruXUOkgWDEcuT8Tb21jVCpY4gpC3J NJKw== X-Gm-Message-State: AC+VfDxdLXcN18zg/SGbtAyVwZo8/kFquSlKbGI6uQBszjgO2D34Zo06 AcdmV4p+peeuqJc2VPaoUIbWxg== X-Google-Smtp-Source: ACHHUZ5Y5bclf4/JmsomEgRjXU3ZEA0DXfCSMEb82R5vv9h9Cc37nFKOnod2O4zNMd69UeR2GI5NLA== X-Received: by 2002:a05:651c:112:b0:2a8:c8d8:80fe with SMTP id a18-20020a05651c011200b002a8c8d880femr708697ljb.23.1683322848739; Fri, 05 May 2023 14:40:48 -0700 (PDT) Received: from [192.168.1.101] (abyl248.neoplus.adsl.tpnet.pl. [83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.40.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:40:48 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:30 +0200 Subject: [PATCH v3 04/12] dt-bindings: display/msm: Add SM6350 MDSS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-4-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=7064; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ElBdVsUKD81P73zo0Ep2jls76a+QZxDiuf7z0YpIh/0=; b=HVJfWdcHy2HkxLalDlUNL7LXqEuluVltURECCD6VAUeJg9ArwMaL2xEgj43hVpKoVx4FTvRPD ykIMX9QlV16DANGWwtXwhmtvafe7BuVDtgW5yfFQjxlDeuxoMixexrN X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the SM6350 MDSS. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +++++++++++++++++= ++++ 1 file changed, 214 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml new file mode 100644 index 000000000000..6674040d2172 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 Display MDSS + +maintainers: + - Krishna Manikandan + +description: + SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6350-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6350-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm6350-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-10nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sm6350-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + power-domains =3D <&dispcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "bus", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x800 0x2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sm6350-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", "iface", "rot", "lut", "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + assigned-clock-rates =3D <300000000>, + <19200000>, + <19200000>, + <19200000>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM6350_CX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SM6350_MX>; + + phys =3D <&dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible =3D "qcom,dsi-phy-10nm"; + reg =3D <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_C= LK>; + clock-names =3D "iface", "ref"; + }; + }; +... --=20 2.40.1 From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 863CDC7EE24 for ; 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[83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:40:50 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:31 +0200 Subject: [PATCH v3 05/12] dt-bindings: display/msm: Add SM6375 MDSS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-5-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=7042; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=s+Spzk/2e7PqcBwMimTOdX5auMNouLwtiaEsT45qphY=; b=1ZErMk/IbniHBNqiXmkWyDGCxVV4v4pZYwteGR2aIfHqMzGcb/EjmrsGoi3UYXSaxH2xim8gk MBZ7Z3tfZVpB0fBPub6QFakSjtzA9v+xPdX07DYOfcQow5fpVFh0ky7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the SM6375 MDSS. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++= ++++ 1 file changed, 216 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml new file mode 100644 index 000000000000..fb56971ea2a1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6375 Display MDSS + +maintainers: + - Konrad Dybcio + +description: + SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6375-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6375-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm6375-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6375-dsi-phy-7nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@5e00000 { + compatible =3D "qcom,sm6375-mdss"; + reg =3D <0x05e00000 0x1000>; + reg-names =3D "mdss"; + + power-domains =3D <&dispcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "ahb", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x820 0x2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@5e01000 { + compatible =3D "qcom,sm6375-dpu"; + reg =3D <0x05e01000 0x8e030>, + <0x05eb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>; + clock-names =3D "iface", + "bus", + "core", + "lut", + "rot", + "vsync", + "throttle"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmpd SM6375_VDDCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible =3D "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x05e94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy= 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmpd SM6375_VDDMX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@5e94400 { + compatible =3D "qcom,sm6375-dsi-phy-7nm"; + reg =3D <0x05e94400 0x200>, + <0x05e94600 0x280>, + <0x05e94900 0x264>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "ref"; + }; + }; +... --=20 2.40.1 From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62488C77B7C for ; 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[83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.40.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:40:52 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:32 +0200 Subject: [PATCH v3 06/12] drm/msm/dpu: Add SM6350 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-6-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=9856; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=sbutAjGXYybmHlEoZi0r3Ql5YzoMwZ3Z92hc8pJF2Oc=; b=K+EUaJaTrnMvZm4ZJ0jykRGrK+RvEMg3CXxZLvxI6J9UkFDytH7WU+gWo4j72GlwZRtgKRtzv bEa/SNgdJcjAbkMJYQ4li39gjI+PKWcM7EKOASB0GNSjMKGRS8HCDmR X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add SM6350 support to the DPU1 driver to enable display output. It's worth noting that one entry dpu_qos_lut_entry was trimmed off: {.fl =3D 0, .lut =3D 0x0011223344556677 }, due to the fact that newer SoCs dropped the .fl (fill level)-based logic and don't provide real values, resulting in all entries but the last one being unused. Signed-off-by: Konrad Dybcio Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 187 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 196 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h new file mode 100644 index 000000000000..e8bfbd468e0a --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_6_4_SM6350_H +#define _DPU_6_4_SM6350_H + +static const struct dpu_caps sm6350_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0x7, + .qseed_type =3D DPU_SSPP_SCALER_QSEED4, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg =3D { + .ubwc_version =3D DPU_HW_UBWC_VER_20, + .ubwc_swizzle =3D 6, + .highest_bank_bit =3D 1, +}; + +static const struct dpu_mdp_cfg sm6350_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0x0, .len =3D 0x494, + .features =3D 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] =3D { .reg_off =3D 0x2c4, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 2= 0 }, + }, +}; + +static const struct dpu_ctl_cfg sm6350_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x1600, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, +}; + +static const struct dpu_sspp_cfg sm6350_sspp[] =3D { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), +}; + +static const struct dpu_lm_cfg sm6350_lm[] =3D { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), +}; + +static const struct dpu_dspp_cfg sm6350_dspp[] =3D { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static struct dpu_pingpong_cfg sm6350_pp[] =3D { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + -1), +}; + +static const struct dpu_intf_cfg sm6350_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MA= SK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_S= C7180_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), +}; + +static const struct dpu_vbif_cfg sm6350_vbif[] =3D { + { + .name =3D "vbif_0", .id =3D VBIF_RT, + .base =3D 0, .len =3D 0x1044, + .features =3D BIT(DPU_VBIF_QOS_REMAP), + .xin_halt_timeout =3D 0x4000, + .qos_rt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_rt_pri_lvl), + .priority_lvl =3D sdm845_rt_pri_lvl, + }, + .qos_nrt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl =3D sdm845_nrt_pri_lvl, + }, + .memtype_count =3D 14, + .memtype =3D {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, + }, +}; + +static const struct dpu_perf_cfg sm6350_perf_data =3D { + .max_bw_low =3D 4200000, + .max_bw_high =3D 5100000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 35, + /* TODO: confirm danger_lut_tbl */ + .danger_lut_tbl =3D {0xffff, 0xffff, 0x0, 0x0, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +const struct dpu_mdss_cfg dpu_sm6350_cfg =3D { + .caps =3D &sm6350_dpu_caps, + .ubwc =3D &sm6350_ubwc_cfg, + .mdp_count =3D ARRAY_SIZE(sm6350_mdp), + .mdp =3D sm6350_mdp, + .ctl_count =3D ARRAY_SIZE(sm6350_ctl), + .ctl =3D sm6350_ctl, + .sspp_count =3D ARRAY_SIZE(sm6350_sspp), + .sspp =3D sm6350_sspp, + .mixer_count =3D ARRAY_SIZE(sm6350_lm), + .mixer =3D sm6350_lm, + .dspp_count =3D ARRAY_SIZE(sm6350_dspp), + .dspp =3D sm6350_dspp, + .pingpong_count =3D ARRAY_SIZE(sm6350_pp), + .pingpong =3D sm6350_pp, + .intf_count =3D ARRAY_SIZE(sm6350_intf), + .intf =3D sm6350_intf, + .vbif_count =3D ARRAY_SIZE(sm6350_vbif), + .vbif =3D sm6350_vbif, + .reg_dma_count =3D 1, + .dma_cfg =3D &sm8250_regdma, + .perf =3D &sm6350_perf_data, + .mdss_irqs =3D BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF1_TEAR_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 9daeaccc4f52..5ef1dffc27dc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -748,6 +748,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_linea= r[] =3D { {.fl =3D 0, .lut =3D 0x0011222222335777}, }; =20 +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] =3D { + {.fl =3D 0, .lut =3D 0x0011223445566777 }, +}; + static const struct dpu_qos_lut_entry sm8150_qos_linear[] =3D { {.fl =3D 0, .lut =3D 0x0011222222223357 }, }; @@ -803,6 +807,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_6_0_sm8250.h" #include "catalog/dpu_6_2_sc7180.h" #include "catalog/dpu_6_3_sm6115.h" +#include "catalog/dpu_6_4_sm6350.h" #include "catalog/dpu_6_5_qcm2290.h" =20 #include "catalog/dpu_7_0_sm8350.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index e9237321df77..56af77353b1e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage { DPU_QOS_LUT_USAGE_LINEAR, DPU_QOS_LUT_USAGE_MACROTILE, DPU_QOS_LUT_USAGE_NRT, + DPU_QOS_LUT_USAGE_CWB, + DPU_QOS_LUT_USAGE_MACROTILE_QSEED, DPU_QOS_LUT_USAGE_MAX, }; =20 @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; +extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 0e7a68714e9e..46be7ad8d615 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sc8180x-dpu", .data =3D &dpu_sc8180x_cfg, }, { .compatible =3D "qcom,sc8280xp-dpu", .data =3D &dpu_sc8280xp_cfg, }, { .compatible =3D "qcom,sm6115-dpu", .data =3D &dpu_sm6115_cfg, }, + { .compatible =3D "qcom,sm6350-dpu", .data =3D &dpu_sm6350_cfg, }, { .compatible =3D "qcom,sm8150-dpu", .data =3D &dpu_sm8150_cfg, }, { .compatible =3D "qcom,sm8250-dpu", .data =3D &dpu_sm8250_cfg, }, { .compatible =3D "qcom,sm8350-dpu", .data =3D &dpu_sm8350_cfg, }, --=20 2.40.1 From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1017C77B75 for ; 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[83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.40.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:40:54 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:33 +0200 Subject: [PATCH v3 07/12] drm/msm: mdss: Add SM6350 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-7-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=1447; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=0D7OZJvsI1VqBAldTbVtRFbwuC+jJW8mAUrMe9Ykcbs=; b=tJk+hp42JEbVFdnnUZXF6Ww9u3ITN3Ny597c6lPUsEhtqF5AmZGzbMxXnXmKA+XitE4rGDxrE jwtK6aBm5J9CLs9cD8i/4dS0CLFRzKzJ+bKuJZvxO64kE4i46eeWmGk X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for MDSS on SM6350. Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e8c93731aaa1..4e3a5f0c303c 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data =3D { .highest_bank_bit =3D 2, }; =20 +static const struct msm_mdss_data sm6350_data =3D { + .ubwc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D 6, + .ubwc_static =3D 0x1e, + .highest_bank_bit =3D 1, +}; + static const struct msm_mdss_data sm8150_data =3D { .ubwc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, @@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sc8180x-mdss", .data =3D &sc8180x_data }, { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &sc8280xp_data }, { .compatible =3D "qcom,sm6115-mdss", .data =3D &sm6115_data }, + { .compatible =3D "qcom,sm6350-mdss", .data =3D &sm6350_data }, { .compatible =3D "qcom,sm8150-mdss", .data =3D &sm8150_data }, { .compatible =3D "qcom,sm8250-mdss", .data =3D &sm8250_data }, { .compatible =3D "qcom,sm8350-mdss", .data =3D &sm8250_data }, --=20 2.40.1 From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 975CCC77B75 for ; Fri, 5 May 2023 21:42:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233239AbjEEVm0 (ORCPT ); Fri, 5 May 2023 17:42:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233653AbjEEVlk (ORCPT ); Fri, 5 May 2023 17:41:40 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 191A355BF for ; Fri, 5 May 2023 14:40:58 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2ac836f4447so19077681fa.2 for ; Fri, 05 May 2023 14:40:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683322856; x=1685914856; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5hiwjibX88i5/MafZ3aoPA1DYLMeczKJpUvHeJK49/0=; b=bu9R+u4u9h6DoTsLtxgUY1CjRCq0yWxqPL8TepI6f2+JaeEvrvs02rNtlK3imhskYK mQrxsKe7qedY8NFtiw7FD+MwaAreT+EDRjMEtt4h++4jYubvSj5Ogb/DG9lTz3aM8oC3 JcbcYLipEu/DN9SsJFB3dHn+XjL3R5C2xBthHFm+a17ECtuBvQx7xEnTNueL4Da+9ztA 3tyXrsKzWJJmRuM5l8fHxDO2i2sqe+QbtkueZ8jR5kP0i91s5MWuRN/uhu1yXZ2qtOMl ZHC1A8tsIM/isWWpa04e8SftLoWelcxrdmjg4YXi6uRX8m+noNZF85Uby9lftO8XTSwe YBOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683322856; x=1685914856; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5hiwjibX88i5/MafZ3aoPA1DYLMeczKJpUvHeJK49/0=; b=UhJRsiPF9Rxk81KJqlvZ0/FFB6EDbfQI5fTW87Sqp06jqiszt9CXwk7Uhup1rMh4a2 tIsvFynpYcjb08E/N6xKik2RH8bFGWOt9zXoyDImcNNxURnGB1tHL9Z24SE8hX53S80t vrqihXd+x6DaMBcoiihwVrpdf1DCdNCsRWZVJiSov4YDkw2hE10dQ4hIu696lyUlR/yx WQS1yxtCIgUmG6N5h6G5mGDjOQLjZhtNp68ceNepD/ThpGo4XOgz5+cth1WzwSkp8aBI mceUXcgtZ7gTMbabu7kUyI1E2SIIJnmfBgJrr7yqEiWKYjWe3pejDlCdWumU/vEUX/ss GvWg== X-Gm-Message-State: AC+VfDxP9RnzMcPbcpCS7plrd2+1qgX6drXqi7lOwUpKnUVVrpA0GG+E jUdcC50KsbSZ6JXK7VIHRJOaRA== X-Google-Smtp-Source: ACHHUZ48LuAUd+7u6aTPDcw4LbdMc3w8Q98hNrHUMnJ0h0JX/4LSGGuiINtDJYdZcxkTP2qMNWkBAQ== X-Received: by 2002:a2e:9858:0:b0:2a8:ea1e:bdf4 with SMTP id e24-20020a2e9858000000b002a8ea1ebdf4mr830653ljj.52.1683322856452; Fri, 05 May 2023 14:40:56 -0700 (PDT) Received: from [192.168.1.101] (abyl248.neoplus.adsl.tpnet.pl. [83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.40.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:40:56 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:34 +0200 Subject: [PATCH v3 08/12] drm/msm/dpu: Add SM6375 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-8-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=7458; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ONx8/343ZY2EmcqJXGJ1u91Yg+XevcIpofVrogQW5Ms=; b=hvh+q049vRb9KY9QAkE6++hZSfHrNxAEKn/f5jB46BX+Fw62SXO5SrpvCAxYHLy9jiclnDa9A vuY0YiRxaZWADyO2yIJIH+/Xsh2KfRpfFkyayvrzsztzBsGwI98a33J X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add basic SM6375 support to the DPU1 driver to enable display output. Signed-off-by: Konrad Dybcio --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 155 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h new file mode 100644 index 000000000000..c7f303b0557e --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_6_9_SM6375_H +#define _DPU_6_9_SM6375_H + +static const struct dpu_caps sm6375_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages =3D 0x4, + .qseed_type =3D DPU_SSPP_SCALER_QSEED4, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D 2160, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg =3D { + .ubwc_version =3D DPU_HW_UBWC_VER_20, + .ubwc_swizzle =3D 6, + .highest_bank_bit =3D 1, +}; + +static const struct dpu_mdp_cfg sm6375_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0x0, .len =3D 0x494, + .features =3D 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + }, +}; + +static const struct dpu_ctl_cfg sm6375_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, +}; + +static const struct dpu_sspp_cfg sm6375_sspp[] =3D { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), +}; + +static const struct dpu_lm_cfg sm6375_lm[] =3D { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, + &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), +}; + +static const struct dpu_dspp_cfg sm6375_dspp[] =3D { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sm6375_pp[] =3D { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), +}; + +static const struct dpu_intf_cfg sm6375_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0), + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_S= C7280_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), +}; + +static const struct dpu_vbif_cfg sm6375_vbif[] =3D { + { + .name =3D "vbif_0", .id =3D VBIF_RT, + .base =3D 0, .len =3D 0x2008, + .features =3D BIT(DPU_VBIF_QOS_REMAP), + .xin_halt_timeout =3D 0x4000, + .qos_rp_remap_size =3D 0x40, + .qos_rt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_rt_pri_lvl), + .priority_lvl =3D sdm845_rt_pri_lvl, + }, + .qos_nrt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl =3D sdm845_nrt_pri_lvl, + }, + .memtype_count =3D 14, + .memtype =3D {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, + }, +}; + +static const struct dpu_perf_cfg sm6375_perf_data =3D { + .max_bw_low =3D 5200000, + .max_bw_high =3D 6200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, /* No LLCC on this SoC */ + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 24, + /* TODO: confirm danger_lut_tbl */ + .danger_lut_tbl =3D {0xffff, 0xffff, 0x0, 0x0, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +const struct dpu_mdss_cfg dpu_sm6375_cfg =3D { + .caps =3D &sm6375_dpu_caps, + .ubwc =3D &sm6375_ubwc_cfg, + .mdp_count =3D ARRAY_SIZE(sm6375_mdp), + .mdp =3D sm6375_mdp, + .ctl_count =3D ARRAY_SIZE(sm6375_ctl), + .ctl =3D sm6375_ctl, + .sspp_count =3D ARRAY_SIZE(sm6375_sspp), + .sspp =3D sm6375_sspp, + .mixer_count =3D ARRAY_SIZE(sm6375_lm), + .mixer =3D sm6375_lm, + .dspp_count =3D ARRAY_SIZE(sm6375_dspp), + .dspp =3D sm6375_dspp, + .pingpong_count =3D ARRAY_SIZE(sm6375_pp), + .pingpong =3D sm6375_pp, + .intf_count =3D ARRAY_SIZE(sm6375_intf), + .intf =3D sm6375_intf, + .vbif_count =3D ARRAY_SIZE(sm6375_vbif), + .vbif =3D sm6375_vbif, + .perf =3D &sm6375_perf_data, + .mdss_irqs =3D BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF1_TEAR_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 5ef1dffc27dc..7577572a5ef4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -809,6 +809,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_6_3_sm6115.h" #include "catalog/dpu_6_4_sm6350.h" #include "catalog/dpu_6_5_qcm2290.h" +#include "catalog/dpu_6_9_sm6375.h" =20 #include "catalog/dpu_7_0_sm8350.h" #include "catalog/dpu_7_2_sc7280.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 56af77353b1e..96a8ec02b5b8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; +extern const struct dpu_mdss_cfg dpu_sm6375_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 46be7ad8d615..980c3c8f8269 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sc8280xp-dpu", .data =3D &dpu_sc8280xp_cfg, }, { .compatible =3D "qcom,sm6115-dpu", .data =3D &dpu_sm6115_cfg, }, { .compatible =3D "qcom,sm6350-dpu", .data =3D &dpu_sm6350_cfg, }, + { .compatible =3D "qcom,sm6375-dpu", .data =3D &dpu_sm6375_cfg, }, { .compatible =3D "qcom,sm8150-dpu", .data =3D &dpu_sm8150_cfg, }, { .compatible =3D "qcom,sm8250-dpu", .data =3D &dpu_sm8250_cfg, }, { .compatible =3D "qcom,sm8350-dpu", .data =3D &dpu_sm8350_cfg, }, --=20 2.40.1 From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A65AAC77B7C for ; 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[83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.40.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:40:57 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:35 +0200 Subject: [PATCH v3 09/12] drm/msm: mdss: Add SM6375 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-9-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=1022; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Nh6zuYJI8gb14gxje6MmS/hbQSaIA3Eeoi75EfztoC0=; b=O0R9IBwQx83wZaZ+iCkksyDGMEr66jfhQEuaLMyd93w2BZzeP2bgaTdASpHY1oirCrmn/JcOn 3G+pjZFuHTiCBujAXjqW5hc8QDl1jLHFkxGYeQ8CzvHk3Ju4aJllTVX X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for MDSS on SM6375. Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 4e3a5f0c303c..05648c910c68 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -580,6 +580,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &sc8280xp_data }, { .compatible =3D "qcom,sm6115-mdss", .data =3D &sm6115_data }, { .compatible =3D "qcom,sm6350-mdss", .data =3D &sm6350_data }, + { .compatible =3D "qcom,sm6375-mdss", .data =3D &sm6350_data }, { .compatible =3D "qcom,sm8150-mdss", .data =3D &sm8150_data }, { .compatible =3D "qcom,sm8250-mdss", .data =3D &sm8250_data }, { .compatible =3D "qcom,sm8350-mdss", .data =3D &sm8250_data }, --=20 2.40.1 From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEAE3C77B75 for ; Fri, 5 May 2023 21:42:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231735AbjEEVmn (ORCPT ); Fri, 5 May 2023 17:42:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233665AbjEEVll (ORCPT ); Fri, 5 May 2023 17:41:41 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B6775BB5 for ; Fri, 5 May 2023 14:41:01 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2ac7707e34fso26880331fa.1 for ; Fri, 05 May 2023 14:41:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683322860; x=1685914860; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ppRfvpEzKntx7DzSp5zW1I4Fc3JFfOMmEmtjxYhv2RE=; b=R3nz/yc4RKI+HKc8qf/CgP4sa5/occ8xEvTKS/qhoYNoPxZW7k/tEOgBf9Il8un/yP iRxO9fomYjGWCfknkCXi8KznES714HRBdJPqrBElSXfSlCCTrtdrYqPFsE2vKFYoTOJg t5DiIqJZgA3nCCL7Biv3PIRZKWmM+EwCx/lAMbZyxw9oS8Yu2MpC79CIHgKx4j+68qGX uI96O9JZKvl8uYUOczRzmWy/yBvpBi1s1RAvpBMvypuESFlE5w/AWQVZe4lqgT1i//5V 3YSJhnPyZGfKrBBfc+0ErO1wkWkCWCDr6i/lEnz4XK5KXRZ7PGZMkNW6SDIivzqPzroq o0ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683322860; x=1685914860; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ppRfvpEzKntx7DzSp5zW1I4Fc3JFfOMmEmtjxYhv2RE=; b=lcH/jzwCp6TF62ea7BSjhfMcdcfyzFSKmEgWNw6opvMXL1kD7lpCIs8f6ngpP+nZ7i dAElhNQebvRSo7fjZ19wgZEx8FF0gio4/EmfvmuZH1T8Z04IdGrb8tUxh7e4XrIWpqQy LpnggrQdFjli5+HLOT+VoeUWIOidIzQ95l6AOQ6Xqhho/en1zgQQsJXb2ACUUCO5fqjx wklQu5jqt8UN1z7G/GNouqYUgse07aR2XkZ6sqaw//6+/uF/Qof2iG5BF/AJPhRDzQFC 5tRtIiufttxLbzzahEzOce6tOTDTr5FRKoM6tGsy+VYRhNyshByG1Qdbh9d9d2Ogckbd 93JQ== X-Gm-Message-State: AC+VfDwxLvBXnGqW1sXvQl01CxMAMHnIBqynOFiot1LBmGW7g12sWWJP bYQHHRL4RqO4BtQ8OILavrvPMg== X-Google-Smtp-Source: ACHHUZ5TWav1X9X/ALxvs/0XM5r7mThgrubkXZrzJkCS8NbL4zVainf3e/1qHa6k3/M1q30PkS1m2A== X-Received: by 2002:a2e:9211:0:b0:299:bb73:fcd4 with SMTP id k17-20020a2e9211000000b00299bb73fcd4mr806540ljg.7.1683322859940; Fri, 05 May 2023 14:40:59 -0700 (PDT) Received: from [192.168.1.101] (abyl248.neoplus.adsl.tpnet.pl. [83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.40.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:40:59 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:36 +0200 Subject: [PATCH v3 10/12] iommu/arm-smmu-qcom: Sort the compatible list alphabetically MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-10-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=965; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9/++xt/utIOxLufVN9PZF2yMVmu78Xo8NRamuKy95SI=; b=W4vng8UwOpFtLvkhYgHEBma6qHU974GMhSHhkYHxlHjBzkNdxo9TfDuc1S6Rp7aMdSC9LKIwn HplM/nY9V4gDWs9MiUk4EMJk6SU/76Otxvj2rOjLu76AsmwlZtfkUpn X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It got broken at some point, fix it up. Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index ae09c627bc84..f945ae3d9d06 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -251,10 +251,10 @@ static const struct of_device_id qcom_smmu_client_of_= match[] __maybe_unused =3D { { .compatible =3D "qcom,sc7280-mss-pil" }, { .compatible =3D "qcom,sc8180x-mdss" }, { .compatible =3D "qcom,sc8280xp-mdss" }, - { .compatible =3D "qcom,sm8150-mdss" }, - { .compatible =3D "qcom,sm8250-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, + { .compatible =3D "qcom,sm8150-mdss" }, + { .compatible =3D "qcom,sm8250-mdss" }, { } }; =20 --=20 2.40.1 From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49DB7C77B75 for ; Fri, 5 May 2023 21:42:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233660AbjEEVme (ORCPT ); Fri, 5 May 2023 17:42:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233673AbjEEVlu (ORCPT ); Fri, 5 May 2023 17:41:50 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8E685BBF for ; Fri, 5 May 2023 14:41:03 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2ac8d9399d5so7756441fa.1 for ; Fri, 05 May 2023 14:41:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683322862; x=1685914862; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6Cgx0VgjSWF36kTiyIdxe2LPUi4kT2lQKkyyJC5x69s=; b=Gccfie7GMOugjyiUVru/AmbzWeTgn3lIDnsiRORE1BLhhAhDo2q5OeGjUTPqdrkPBV 42ByFze8DoBI5q1FCMCT3Iqs+bmFU9i+JGnGLiFcDLLR+U6BR/AlJJoHqfO5asrH7mPH tUCk2VtfCESPRGvyE+inqnMfl0UcEkoyWEGYVTdWp4vxAJonCDVB+us6Iw92/tmXMKch lHBlg/1zA/bh25rGZ61FMJcGz6CSwAPlGrSppo1mdMsb5EsYAZ3p1Ep7bEJedfnQfzJW ihCWZ0yivoUcwJphIuwej6UOCSM9grvNt6HRpYB4LNcg3PISN324cVw3HYfU0OzB2t6h AIzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683322862; x=1685914862; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Cgx0VgjSWF36kTiyIdxe2LPUi4kT2lQKkyyJC5x69s=; b=DLb52MUk2GnMqzbC1ri+y7d8QkA0CcAQZiOaHX7Rm0cdL1bUAVZlLda2cQnhH3LML4 y/pFaWIyrNmUhxSsFTRv3oX8TNiZNaOTX57CVmG0ttLgC7ow7QLstlrEvAYjJ8w+s79+ rNGr/i7kkGMmvQGs01iclR8/pvwYua8xFR78e6Y0i2QDhD2TaJ9DNijEH1o43BJ7wCf6 lKxVHQK3s3Wke3EWGDltbE/hvqiBrMBKfW6X3nCVDZLq7L2E2x6WCvsgHAYBW6fTwVjK V8tsNTwcdKyteiw7MopJOidFJVByEIgD2Pau+sUAIJjzZexnYHMDVZC2S2+u0DZerUGL 4bmQ== X-Gm-Message-State: AC+VfDxg1ORsN35jymvsPf5n+cWZS6ePLib1PT/hhjgaMnpDau1beVFH g3PVzQOVIroA69t7G7nhA+r1hQ== X-Google-Smtp-Source: ACHHUZ4+K+GhXhvLSXj3jdIBiVBVY1fOjuTIzZpxArJ+LOicJ5uIxrApQrg8YtPi+bMU1mnhxFICzg== X-Received: by 2002:a2e:9056:0:b0:2a7:9a7a:f864 with SMTP id n22-20020a2e9056000000b002a79a7af864mr953234ljg.5.1683322861925; Fri, 05 May 2023 14:41:01 -0700 (PDT) Received: from [192.168.1.101] (abyl248.neoplus.adsl.tpnet.pl. [83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.41.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:41:01 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:37 +0200 Subject: [PATCH v3 11/12] iommu/arm-smmu-qcom: Add SM6375 DPU compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-11-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=919; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hMmDD+SgonZLP46KBM866xQojXqpPqEZ25ow2fxLp/E=; b=zckkfPprq0LAaufGJdyd08HwqQ+DvDuj3pjCVufSbw/R95EDd1/WxZUQAiuD3r3x7v5RBq0Ea rvoL+U9hlerCFPzxbe1MTtGhJLaUTYkcG44IEB3EaL4dsVNizhDuuO+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the SM6375 DPU compatible to clients compatible list, as it also needs the workarounds. Acked-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index f945ae3d9d06..d7d5d1dbee17 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -253,6 +253,7 @@ static const struct of_device_id qcom_smmu_client_of_ma= tch[] __maybe_unused =3D { { .compatible =3D "qcom,sc8280xp-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, + { .compatible =3D "qcom,sm6375-mdss" }, { .compatible =3D "qcom,sm8150-mdss" }, { .compatible =3D "qcom,sm8250-mdss" }, { } --=20 2.40.1 From nobody Wed Feb 11 16:31:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5567FC77B75 for ; Fri, 5 May 2023 21:42:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233753AbjEEVmj (ORCPT ); Fri, 5 May 2023 17:42:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233629AbjEEVlu (ORCPT ); Fri, 5 May 2023 17:41:50 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 774EF59E7 for ; Fri, 5 May 2023 14:41:05 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-4f139de8cefso17557518e87.0 for ; Fri, 05 May 2023 14:41:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683322864; x=1685914864; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KKTw5Zfw+dKxxnY8fd/tof/aQPft5PObVsbIBwm4nOE=; b=ukT0/Gbl014hMNt6POWBZru46jjtyO67bCDOzbZQZOMZh/Xs1H+L8K6mDJGk6hCggf hP8OvDws58qepr8kd9WeIEaA83Rd6PluO+iUO5+29SlGxYywQWhIQE8qIa4GBG418mt8 c5l3uHkpi/5r7sB13IdmqPFrrHzj/BxFMY0JaZPSq0RF8ukN/qvrdcvLllwn9NNL5paG xQMSTWDqos2eRlNGrdkBtaReQd/VjqO7SYfT15338L6qPFxVkRTh6Q6AfSncogyQyH45 fZbyB/xTGzrtQcYxtMwV24Pyo+2bBYQzas5NnRA2v+FQniqofEXyRf8f/6JQ4+lNTg6F 2clg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683322864; x=1685914864; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KKTw5Zfw+dKxxnY8fd/tof/aQPft5PObVsbIBwm4nOE=; b=ENXM+sXk/8cv1HWV3EPsegEgz+tCjUX2CQBUH2SHxlGgyIJ3Csa3i2WqXDPAD9ag62 wKwQ4RJDr0/DKgE2MAKmsGepOE1rswwlzWDkI2PWjD9bAZD29J32zQSYZh+yZ904Bpj1 /x+Tupw76yeG8iLDtYHel7vekwTpKPCcE+yCnk+ndgqbkVHk05rLf16xx1M8nSFOVCUr 9AGkk1fsHTqbK/Accd2eBH6o40JIOAiu5r8tNl055Dj/wzXTke33djaLg1njP7VQvcBz 9Fi6mniYJjNA5UQX4HNdZWMXlixucBEcqrsWKn81dAJKkyMawk4I+BobxGwGO0W/LXUz cYOQ== X-Gm-Message-State: AC+VfDyb/+LHuGlUE2F6oFlR4GHfM5mWCnoC7F6zMz5Tei8YDbrzG1eG 8WeaSDY+LIObZOHQUiXwCAXPNA== X-Google-Smtp-Source: ACHHUZ6ZtEMdLb5DxiTNnLAorcEKFTUditPxbDFGZDHqLOLxFtWNDnrraKKGdt84CJWoao5/f5ySSg== X-Received: by 2002:a2e:994c:0:b0:295:d7a8:559b with SMTP id r12-20020a2e994c000000b00295d7a8559bmr880720ljj.10.1683322863863; Fri, 05 May 2023 14:41:03 -0700 (PDT) Received: from [192.168.1.101] (abyl248.neoplus.adsl.tpnet.pl. [83.9.31.248]) by smtp.gmail.com with ESMTPSA id n12-20020a2e720c000000b002a776dbc277sm126453ljc.124.2023.05.05.14.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:41:03 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 May 2023 23:40:38 +0200 Subject: [PATCH v3 12/12] iommu/arm-smmu-qcom: Add SM6350 DPU compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v3-12-9837d6b3516d@linaro.org> References: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v3-0-9837d6b3516d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683322839; l=1014; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=d3S3xhOuliIdaa9KoHmUn1yxgnvenr1zId8Sw3Pr4Gg=; b=u3I52rgeZRIPJW2hyj/d+O+JrD0lLVAtextnz9mrc5yCQjY92j+5ZQdr3tADqPYJVA4RutRv3 92CfHxICo1ADBe7zjWqCKUtgraxwFrHDFKvLO1TZbLhn+tvZjWcQpLU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Konrad Dybcio Add the SM6350 DPU compatible to clients compatible list, as it also needs the workarounds. Signed-off-by: Konrad Dybcio Acked-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index d7d5d1dbee17..e64c737724c4 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -253,6 +253,7 @@ static const struct of_device_id qcom_smmu_client_of_ma= tch[] __maybe_unused =3D { { .compatible =3D "qcom,sc8280xp-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, + { .compatible =3D "qcom,sm6350-mdss" }, { .compatible =3D "qcom,sm6375-mdss" }, { .compatible =3D "qcom,sm8150-mdss" }, { .compatible =3D "qcom,sm8250-mdss" }, --=20 2.40.1