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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:22 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:10 +0200 Subject: [PATCH v2 01/13] dt-bindings: display/msm: dsi-controller-main: Add SM6350 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-1-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Rob Herring X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=1129; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1EZeD/7Id9o6cBL4ylQ4GNUTK1f0wLzgpRCWpr/xxlY=; b=wcPs44uEQqo7xru1sJ+NnetyZuOSV0ot3K+yGfD6q7BPkHkYw3QFtH5LXw7Tm1g/nLRcx7x2ZTpV PmFalNyZAsKNw3ajQaTN5bG899GZ4jB9ffY6uOvQVN4xLUyZfp7t X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the DSI host found on SM6350. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2= ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index e6c1ebfe8a32..6f367a1fabf8 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6350-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl @@ -285,6 +286,7 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl + - qcom,sm6350-dsi-ctrl then: properties: clocks: --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CFE8C77B7C for ; Thu, 20 Apr 2023 22:31:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231739AbjDTWbg (ORCPT ); Thu, 20 Apr 2023 18:31:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232050AbjDTWb2 (ORCPT ); Thu, 20 Apr 2023 18:31:28 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C97533C1B for ; Thu, 20 Apr 2023 15:31:26 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2a7b02615f1so9608081fa.0 for ; Thu, 20 Apr 2023 15:31:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682029885; x=1684621885; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mgy1m01DsGQkO8m6umm6ha07ksFZFFo7FoVlVrv2pCk=; b=WleTIZCSyGhCiRH+O5xPdhKxDlRPx3jxmlS6I8zc9dTtPQpUulWszVYU/24DRXIWrx TyTAz2cSZSp77irfa2s+QuxXhWNuP98IAuNQitxIvEp38mNY9XkD35p01x86OBA+LoAc i5MIcTrh2faAd5zAh5V/TxUvUHDNNWldY5gwehCxA+JRZX4VqZBd4cK1ugV9It7/CJvv pOliZeCZjaF7GFwqPEzKbTIiwzzVMx2pbijbXlBRI6K97dU6vig21HP9b6E9NJwfDbXh cxWaja6+AcHhUqGiu498Q4U9M+zFrg/YvsKPH4LhYV3vTKl2TKKaAmBcsOqweKIYOAON 1iuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682029885; x=1684621885; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mgy1m01DsGQkO8m6umm6ha07ksFZFFo7FoVlVrv2pCk=; b=J9yix/CGkI3g5+WcxN9OUxl03P+uq88K6rbETIto7Ak90RBg4e383fu8sOjS1q78kI cfEw8qBiCsTY1YkNmLO+DorgK8MravD+Lp4IsJTk2Q+95NDOG2C88qu5dpmTd05n8ENF gTUd8C1Sc2z0vJYDcCiTWeyD9bJrHkOXtsJwG/ZWFZbiyOWb17ZJG0HUYda08FcguT+e C/TZw3rcPPSJzFEoY+XgxWZqHOIii1D7vb5sv6/g2DuKov/1alTm8+NTv5az13iFtT/t HctQ+7gO4Ue5CJGbVpLR1AZPRHuoXc2dJH8KCzJkDbXcPg2GZq4MUNG86mOrHwSYciE0 ZFRw== X-Gm-Message-State: AAQBX9dkYTad5DXgjR39CXLdqhpftMHtr5BwEdH3CSgbM7XwvuqpMtk1 Hqtl31MBDv2hXLB5XCX8WCnxig== X-Google-Smtp-Source: AKy350ZAf10TswzpeU0L8mqlrgrQZIW7aM7IXW4Y6tz+en9CcheCpNxhhVoVesxB41VU6Bo+G6fZGQ== X-Received: by 2002:a2e:98d8:0:b0:2a8:ee05:ca1e with SMTP id s24-20020a2e98d8000000b002a8ee05ca1emr95726ljj.13.1682029884877; Thu, 20 Apr 2023 15:31:24 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:24 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:11 +0200 Subject: [PATCH v2 02/13] dt-bindings: display/msm: dsi-controller-main: Add SM6375 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-2-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Rob Herring X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=1145; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=QlPpd+ksZO3I03gNbWxED0xzwfnGvYwQQWVE28vN1qo=; b=Tg+MM4R6Hq9ZR30v4XBrUBNZ1ekzX3I5GoPUGc3SFwD2ubk3y9GVml3+HBbWLW3rLJL2w+YLpVEq V8PlvA1pCze0dvkmYouDUIxE2ZfSWhXFOvvibcPr3IyU+rxq9Qyw X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the DSI host found on SM6375. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2= ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index 6f367a1fabf8..f7dc05a65420 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -27,6 +27,7 @@ properties: - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6350-dsi-ctrl + - qcom,sm6375-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl @@ -354,6 +355,7 @@ allOf: enum: - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6375-dsi-ctrl then: properties: clocks: --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 922D4C77B7E for ; Thu, 20 Apr 2023 22:31:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232951AbjDTWbk (ORCPT ); Thu, 20 Apr 2023 18:31:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232099AbjDTWbb (ORCPT ); Thu, 20 Apr 2023 18:31:31 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B8624233 for ; Thu, 20 Apr 2023 15:31:28 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4ec86aeeb5cso949932e87.3 for ; Thu, 20 Apr 2023 15:31:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682029886; x=1684621886; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VJj4iUa0gP8dE+G0RSh+D7ANM6WUiBcMefoNYHpmjLo=; b=iLhtUyLEI5h9707Bz0eSJLkguwBa6XOJGzh37I0z2vb9Ca/QoEpeiMWcjQJqrI9Vkt QnD8TaJtg9wiBBv5Srk1pmhII07sprdy7KxQI1qs4W4zdqJ/6ZouOobyFrI2nQS04vNA tRbJv412j/22VhX2xsSLTn/9fdFvmpnt26wBHM2IS7/DqMvksvO2WZWJvV3/ckVNX4GO LkHNGyI0KN70paicigpYlelseajoNfziasQnGi1kOOSO4MWXJQu1sOMblsnIn7r6CaS7 +EbUAuC1hKqrbSc75Rj2Fk5oOiEE3VyxvvWpoKJHM4dBoULM/p80aYwzah/Bc9+0eZNl +9Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682029886; x=1684621886; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VJj4iUa0gP8dE+G0RSh+D7ANM6WUiBcMefoNYHpmjLo=; b=GZGr5r/RdxBIj5VV1po7VfEwL+R1RcLy99lhm3sg+UkTIKeRXAoWR0ukktdUpCIBe+ iVmyinnUG1xetUDtJ9Su4POq/8VHwWXL+BBUJZTwRtnXbL0JyD7z8DSTE+p5U7VmcHfx Q2Pgc3GyERDIIA3imYjA361bjlE5jYoew3WevPLafTFYyCJ+DPSWnGI7a/0CSg7PBRRP hIoWrG8u8iwk43XuA9Y4SwWbnbTweD1sYhnZ6F74u2lsiwvdtpdFZvAHPEiEDRLCE9wq v+l3y6EGYGPXS7ySJc8v3BR+0zxiJzL19aFoV5axcg3XMkHGb0n1W/SLa7yl4v5Oc6kE MzjQ== X-Gm-Message-State: AAQBX9dj6KmS11SbhxvFbG4Z2W2W7+aj1bBs1DxReQpfeheclLoqcEDs DRPM6NsYRGH+bvtG2H+v7QcVpw== X-Google-Smtp-Source: AKy350ZaZKdhevb+I6R02zGNmsqx/pDBw3ojmDsIhknsvSc29GRoNLxYD149FtIJnIMVKdZ7Ve5p7A== X-Received: by 2002:ac2:44db:0:b0:4db:3847:12f0 with SMTP id d27-20020ac244db000000b004db384712f0mr740802lfm.50.1682029886498; Thu, 20 Apr 2023 15:31:26 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:26 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:12 +0200 Subject: [PATCH v2 03/13] dt-bindings: display/msm: Add SM6350 DPU MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-3-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=3116; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Jn7UUu6GoDaa1TPUPCp5gGqhPJdOjKwB/r9DEtFoZ/8=; b=hT4Kv6Rl8AlI+YMEYKy2x199yWG2QcMaUez6pKcGxf95PxJ9gt3z6p728s1HkV514Q/8P2XvMAM1 /Y9sppidCF+LVbqRnM8i2sidRJyhpuat81PIaTk/VypHfDVN6QLI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the SM6350 DPU. Signed-off-by: Konrad Dybcio Reviewed-by: Rob Herring --- .../bindings/display/msm/qcom,sm6350-dpu.yaml | 94 ++++++++++++++++++= ++++ 1 file changed, 94 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml new file mode 100644 index 000000000000..979fcf81afc9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-dpu.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SM6350 target + +maintainers: + - Konrad Dybcio + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6350-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display axi clock + - description: Display ahb clock + - description: Display rot clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: iface + - const: rot + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + display-controller@ae01000 { + compatible =3D "qcom,sm6350-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", "iface", "rot", "lut", "core", + "vsync"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + power-domains =3D <&rpmhpd SM6350_CX>; + operating-points-v2 =3D <&mdp_opp_table>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + }; +... --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF945C77B73 for ; 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:27 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:13 +0200 Subject: [PATCH v2 04/13] dt-bindings: display/msm: Add SM6350 MDSS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-4-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=7064; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=+VotB7/AfQN9UJePv7WDKzhmnxGZ+CBYX8ro9N8OQ0o=; b=5jpT7r88RA/9BmjqBmcAEryzssmvgJGy08J1zFiDbDtlAdKrHcjd6K/wfyjeQ3cAU88MdK3/bsz1 /YvmN4C+B/4at0926ONlK0A+8Pk0P5Weze1MV6K+ZBqINSXp93mU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the SM6350 MDSS. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +++++++++++++++++= ++++ 1 file changed, 214 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml new file mode 100644 index 000000000000..6674040d2172 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 Display MDSS + +maintainers: + - Krishna Manikandan + +description: + SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6350-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6350-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm6350-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-10nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sm6350-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + power-domains =3D <&dispcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "bus", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x800 0x2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sm6350-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", "iface", "rot", "lut", "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + assigned-clock-rates =3D <300000000>, + <19200000>, + <19200000>, + <19200000>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM6350_CX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SM6350_MX>; + + phys =3D <&dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible =3D "qcom,dsi-phy-10nm"; + reg =3D <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_C= LK>; + clock-names =3D "iface", "ref"; + }; + }; +... --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55C06C77B7C for ; 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:29 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:14 +0200 Subject: [PATCH v2 05/13] dt-bindings: display/msm: Add SM6375 DPU MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-5-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=3492; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=vZzhA97oxdwZ/IPQF/OKwzeLk8iG5rTuB8ZFpx6DRZ0=; b=LHP9urgYRNjLl/5VSCLQUISqeihQSxNIUZy+XvNKkOEL9JqpSWQ2vdVfistdyy8B/5eY1mn0oqT/ KKMShazuBkrzUMnshYU5IHSJ7DAkhujaMV7IaAqS4nX6dB6v7NvC X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document SM6375 DPU. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6375-dpu.yaml | 106 +++++++++++++++++= ++++ 1 file changed, 106 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml new file mode 100644 index 000000000000..76dc5a7efebf --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-dpu.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SM6375 target + +maintainers: + - Konrad Dybcio + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6375-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display iface clock + - description: Display bus clock + - description: Display core clock + - description: Display lut clock + - description: Display rot clock + - description: Display vsync clock + - description: Display throttle clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: lut + - const: rot + - const: vsync + - const: throttle + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + display-controller@ae01000 { + compatible =3D "qcom,sm6375-dpu"; + reg =3D <0x05e01000 0x8e030>, + <0x05eb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>; + clock-names =3D "iface", + "bus", + "core", + "lut", + "rot", + "vsync", + "throttle"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmpd SM6375_VDDCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + }; +... --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F140AC77B7E for ; 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:31 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:15 +0200 Subject: [PATCH v2 06/13] dt-bindings: display/msm: Add SM6375 MDSS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-6-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=7042; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=NAfwHg47hKCKFK0+NQIcVu2PABcoM/KsJDZyi6LXodQ=; b=ztmVWXu2NN/CiemOQIkHaxNFh4zd6/8/49TptQ4i4ZtEPsJ7YjcNh0g9ioQdx2RS03p11T4AwfZ0 S+oJv0FYB3KDMPVBSGj3lIZAEyQQYIuUtB2x/cFJdK6ZMqJMJJMP X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the SM6375 MDSS. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++= ++++ 1 file changed, 216 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml new file mode 100644 index 000000000000..fb56971ea2a1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6375 Display MDSS + +maintainers: + - Konrad Dybcio + +description: + SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6375-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6375-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm6375-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6375-dsi-phy-7nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@5e00000 { + compatible =3D "qcom,sm6375-mdss"; + reg =3D <0x05e00000 0x1000>; + reg-names =3D "mdss"; + + power-domains =3D <&dispcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "ahb", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x820 0x2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@5e01000 { + compatible =3D "qcom,sm6375-dpu"; + reg =3D <0x05e01000 0x8e030>, + <0x05eb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>; + clock-names =3D "iface", + "bus", + "core", + "lut", + "rot", + "vsync", + "throttle"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmpd SM6375_VDDCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible =3D "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x05e94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy= 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmpd SM6375_VDDMX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@5e94400 { + compatible =3D "qcom,sm6375-dsi-phy-7nm"; + reg =3D <0x05e94400 0x200>, + <0x05e94600 0x280>, + <0x05e94900 0x264>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", "ref"; + }; + }; +... --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A57EC77B7C for ; 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:32 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:16 +0200 Subject: [PATCH v2 07/13] drm/msm/dpu: Add SM6350 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-7-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=9316; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=gT9L4u1VuFTOmRCaxRkDtWh/c76LBas//ACGhlx1A/I=; b=QI3PSCwscxeEAcVw6rnNKDerDN2L6/iHAuZLCciK+BLr0MdnWONP5CgvjUdR24nONcn1dCRf+m5d vHxLHvypBecZqEFObnNHN9dTIyTji31FqG/3WiInbC/b0iWYCkA7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add SM6350 support to the DPU1 driver to enable display output. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Reviewed-by: Marijn Suijten --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 191 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 196 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h new file mode 100644 index 000000000000..687a508cbaa6 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_6_4_SM6350_H +#define _DPU_6_4_SM6350_H + +static const struct dpu_caps sm6350_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0x7, + .qseed_type =3D DPU_SSPP_SCALER_QSEED4, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6350_ubwc_cfg =3D { + .ubwc_version =3D DPU_HW_UBWC_VER_20, + .ubwc_swizzle =3D 6, + .highest_bank_bit =3D 1, +}; + +static const struct dpu_mdp_cfg sm6350_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0x0, .len =3D 0x494, + .features =3D 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] =3D { .reg_off =3D 0x2c4, .bit_off =3D 8 }, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 2= 0 }, + }, +}; + +static const struct dpu_ctl_cfg sm6350_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x1600, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, +}; + +static const struct dpu_sspp_cfg sm6350_sspp[] =3D { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), +}; + +static const struct dpu_lm_cfg sm6350_lm[] =3D { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), +}; + +static const struct dpu_dspp_cfg sm6350_dspp[] =3D { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static struct dpu_pingpong_cfg sm6350_pp[] =3D { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + -1), +}; + +static const struct dpu_intf_cfg sm6350_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2c0, INTF_DP, 0, 35, INTF_SC7180_MA= SK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_S= C7180_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), +}; + +static const struct dpu_vbif_cfg sm6350_vbif[] =3D { + { + .name =3D "vbif_0", .id =3D VBIF_RT, + .base =3D 0, .len =3D 0x1044, + .features =3D BIT(DPU_VBIF_QOS_REMAP), + .xin_halt_timeout =3D 0x4000, + .qos_rt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_rt_pri_lvl), + .priority_lvl =3D sdm845_rt_pri_lvl, + }, + .qos_nrt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl =3D sdm845_nrt_pri_lvl, + }, + .memtype_count =3D 14, + .memtype =3D {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, + }, +}; + +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] =3D { + {.fl =3D 0, .lut =3D 0x0011223344556677 }, + {.fl =3D 0, .lut =3D 0x0011223445566777 }, +}; + +static const struct dpu_perf_cfg sm6350_perf_data =3D { + .max_bw_low =3D 4200000, + .max_bw_high =3D 5100000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 35, + /* TODO: confirm danger_lut_tbl */ + .danger_lut_tbl =3D {0xffff, 0xffff, 0x0, 0x0, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +const struct dpu_mdss_cfg dpu_sm6350_cfg =3D { + .caps =3D &sm6350_dpu_caps, + .ubwc =3D &sm6350_ubwc_cfg, + .mdp_count =3D ARRAY_SIZE(sm6350_mdp), + .mdp =3D sm6350_mdp, + .ctl_count =3D ARRAY_SIZE(sm6350_ctl), + .ctl =3D sm6350_ctl, + .sspp_count =3D ARRAY_SIZE(sm6350_sspp), + .sspp =3D sm6350_sspp, + .mixer_count =3D ARRAY_SIZE(sm6350_lm), + .mixer =3D sm6350_lm, + .dspp_count =3D ARRAY_SIZE(sm6350_dspp), + .dspp =3D sm6350_dspp, + .pingpong_count =3D ARRAY_SIZE(sm6350_pp), + .pingpong =3D sm6350_pp, + .intf_count =3D ARRAY_SIZE(sm6350_intf), + .intf =3D sm6350_intf, + .vbif_count =3D ARRAY_SIZE(sm6350_vbif), + .vbif =3D sm6350_vbif, + .reg_dma_count =3D 1, + .dma_cfg =3D &sm8250_regdma, + .perf =3D &sm6350_perf_data, + .mdss_irqs =3D BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index db558a9ae36e..52750b592b36 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -806,6 +806,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_6_0_sm8250.h" #include "catalog/dpu_6_2_sc7180.h" #include "catalog/dpu_6_3_sm6115.h" +#include "catalog/dpu_6_4_sm6350.h" #include "catalog/dpu_6_5_qcm2290.h" =20 #include "catalog/dpu_7_0_sm8350.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 756bff1d2185..f9611bd75e02 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -320,6 +320,8 @@ enum dpu_qos_lut_usage { DPU_QOS_LUT_USAGE_LINEAR, DPU_QOS_LUT_USAGE_MACROTILE, DPU_QOS_LUT_USAGE_NRT, + DPU_QOS_LUT_USAGE_CWB, + DPU_QOS_LUT_USAGE_MACROTILE_QSEED, DPU_QOS_LUT_USAGE_MAX, }; =20 @@ -880,6 +882,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; +extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 0e7a68714e9e..46be7ad8d615 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1286,6 +1286,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sc8180x-dpu", .data =3D &dpu_sc8180x_cfg, }, { .compatible =3D "qcom,sc8280xp-dpu", .data =3D &dpu_sc8280xp_cfg, }, { .compatible =3D "qcom,sm6115-dpu", .data =3D &dpu_sm6115_cfg, }, + { .compatible =3D "qcom,sm6350-dpu", .data =3D &dpu_sm6350_cfg, }, { .compatible =3D "qcom,sm8150-dpu", .data =3D &dpu_sm8150_cfg, }, { .compatible =3D "qcom,sm8250-dpu", .data =3D &dpu_sm8250_cfg, }, { .compatible =3D "qcom,sm8350-dpu", .data =3D &dpu_sm8350_cfg, }, --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 659EEC77B73 for ; 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:34 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:17 +0200 Subject: [PATCH v2 08/13] drm/msm: mdss: Add SM6350 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-8-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=1325; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=YJnhuotbycPo0Lxuk2IRtdOzqse8Z1bIU0CErB+UTrw=; b=d5k6WYZUd1XbcPs5nVQlXqkJtEycVrXqJI6R1+zGm9QHV1JuWYVoLyI0UBWtYcyZeJB+Ge8Enm6E pWe8cxtkBAoI/eYMad7nfABBlIGkHpu+c6+M/fst+9zWU45spktu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for MDSS on SM6350. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e8c93731aaa1..4e3a5f0c303c 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data =3D { .highest_bank_bit =3D 2, }; =20 +static const struct msm_mdss_data sm6350_data =3D { + .ubwc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D 6, + .ubwc_static =3D 0x1e, + .highest_bank_bit =3D 1, +}; + static const struct msm_mdss_data sm8150_data =3D { .ubwc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, @@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sc8180x-mdss", .data =3D &sc8180x_data }, { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &sc8280xp_data }, { .compatible =3D "qcom,sm6115-mdss", .data =3D &sm6115_data }, + { .compatible =3D "qcom,sm6350-mdss", .data =3D &sm6350_data }, { .compatible =3D "qcom,sm8150-mdss", .data =3D &sm8150_data }, { .compatible =3D "qcom,sm8250-mdss", .data =3D &sm8250_data }, { .compatible =3D "qcom,sm8350-mdss", .data =3D &sm8250_data }, --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9A01C77B7E for ; Thu, 20 Apr 2023 22:32:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233226AbjDTWcV (ORCPT ); Thu, 20 Apr 2023 18:32:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232987AbjDTWbx (ORCPT ); Thu, 20 Apr 2023 18:31:53 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7788F6E97 for ; Thu, 20 Apr 2023 15:31:39 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2a8a5f6771fso9013431fa.3 for ; Thu, 20 Apr 2023 15:31:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682029897; x=1684621897; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4dxb6oAKpk/izyLUqwvlAuj2ZVQP3uibHpiE+szXdbE=; b=DAuz47bFZN+8HBZqxZK1xj7vzFzuO5b/1oE9TuSvW0GiNsasQcVrsGm053yAVeTTWk 2eN2fLzuJUom7JY4uk8VzYM5t+Vt90VQSFHOImPOPGH5d2aBs/ma1TV1EsB3hmrVNL+5 ahOSabOREEjvp8WdlOY370jq6G9AHZlEybYDvCFtf26OGrWAc4KINxo2JanYmCFSYtmr GGVWfZgHiEssIb4MPY2W0LHkXupzdMfsfKizgaqOfgkRTwfrvTUANnon/p66kUXi0BvB j0vf5jiHsd9MNstYqNSnQNL+6BUzYIX00gEgCymaDJQz6ouRQh062a72SrYm+Wof0Itf 24YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682029897; x=1684621897; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4dxb6oAKpk/izyLUqwvlAuj2ZVQP3uibHpiE+szXdbE=; b=Fnt2GtheInj/XBkFMK91oQIi/v+xe0CqnvmQPlX9GZWUHzIVE7D5EL3Jf7lwUn8RUe bf66p2+xpHqlwXPyuBsQfuZPxL1TA2KPMHzZhjSG/Wq6FpA01z+k8HTQp9JeytelHMPt PrrHTOWpgF1IVU3cr9N0j/WDlpQY/r6LZwO892ZVe8suTnkKWCyrVE4laybS5Tb9xhOe WyA04K1s6U/1Gu6B41Iw77BTKAiXQpKJp9H3sP0Ve8tpEmsCpGeYy8uNVdpJQY8UC0vu ZQO2DXeQ8Pd0sO/TJernBClOXCoMEbc9F8RL7Q9mkN+n06z+6v+ZjKD4jGVjGc0zF7k/ 8bEg== X-Gm-Message-State: AAQBX9cgk/hTLsU3au9Zk3fMnicjw+iaLjToGp3bHfULvcEMPzJma+g+ o5GGomcGjme201WKH/8GiDhITQ== X-Google-Smtp-Source: AKy350Z1Bt4w+Q8dsaEpaq74hi/eXznKY4JqZVcjq9ZvaaLcRchaTXMaiCYfstpq5UqMMZYjcpMfkw== X-Received: by 2002:ac2:55ba:0:b0:4db:2ab7:43e6 with SMTP id y26-20020ac255ba000000b004db2ab743e6mr789579lfg.44.1682029896888; Thu, 20 Apr 2023 15:31:36 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:36 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:18 +0200 Subject: [PATCH v2 09/13] drm/msm/dpu: Add SM6375 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-9-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=8991; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=OM9y6PPtTxs3PCRleFOoCKfkmbVbBCFmJ4Gx6zoTa1k=; b=AD47pEiIgc6SBG55l/F4tvWLbCWuIV84cWo3vheN3jMPT4OBsk1AjKv3SdyxLhIAvDun6mV0m5F1 VHKQaDx4Ddis/q/gmMx5BLUc5iO0DsOdbO7OuckIaqya8surkD6Y X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add basic SM6375 support to the DPU1 driver to enable display output. Signed-off-by: Konrad Dybcio --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 5 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 152 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 5 files changed, 168 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 687a508cbaa6..d46b43964be6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -126,11 +126,6 @@ static const struct dpu_vbif_cfg sm6350_vbif[] =3D { }, }; =20 -static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] =3D { - {.fl =3D 0, .lut =3D 0x0011223344556677 }, - {.fl =3D 0, .lut =3D 0x0011223445566777 }, -}; - static const struct dpu_perf_cfg sm6350_perf_data =3D { .max_bw_low =3D 4200000, .max_bw_high =3D 5100000, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h new file mode 100644 index 000000000000..19ca0051e072 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_6_9_SM6375_H +#define _DPU_6_9_SM6375_H + +static const struct dpu_caps sm6375_dpu_caps =3D { + .max_mixer_width =3D 2048, + .max_mixer_blendstages =3D 0x4, + .qseed_type =3D DPU_SSPP_SCALER_QSEED4, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D 2160, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6375_ubwc_cfg =3D { + .ubwc_version =3D DPU_HW_UBWC_VER_20, + .ubwc_swizzle =3D 6, + .highest_bank_bit =3D 1, +}; + +static const struct dpu_mdp_cfg sm6375_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0x0, .len =3D 0x494, + .features =3D 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + }, +}; + +static const struct dpu_ctl_cfg sm6375_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1dc, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, +}; + +static const struct dpu_sspp_cfg sm6375_sspp[] =3D { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), +}; + +static const struct dpu_lm_cfg sm6375_lm[] =3D { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, + &sm6375_lm_sblk, PINGPONG_0, 0, DSPP_0), +}; + +static const struct dpu_dspp_cfg sm6375_dspp[] =3D { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sm6375_pp[] =3D { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845= _pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), +}; + +static const struct dpu_intf_cfg sm6375_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x00000, 0x2c0, INTF_NONE, 0, 0, 0, 0, 0), + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_S= C7280_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), +}; + +static const struct dpu_vbif_cfg sm6375_vbif[] =3D { + { + .name =3D "vbif_0", .id =3D VBIF_RT, + .base =3D 0, .len =3D 0x2008, + .features =3D BIT(DPU_VBIF_QOS_REMAP), + .xin_halt_timeout =3D 0x4000, + .qos_rp_remap_size =3D 0x40, + .qos_rt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_rt_pri_lvl), + .priority_lvl =3D sdm845_rt_pri_lvl, + }, + .qos_nrt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl =3D sdm845_nrt_pri_lvl, + }, + .memtype_count =3D 14, + .memtype =3D {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, + }, +}; + +static const struct dpu_perf_cfg sm6375_perf_data =3D { + .max_bw_low =3D 5200000, + .max_bw_high =3D 6200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, /* No LLCC on this SoC */ + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 24, + /* TODO: confirm danger_lut_tbl */ + .danger_lut_tbl =3D {0xffff, 0xffff, 0x0, 0x0, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +const struct dpu_mdss_cfg dpu_sm6375_cfg =3D { + .caps =3D &sm6375_dpu_caps, + .ubwc =3D &sm6375_ubwc_cfg, + .mdp_count =3D ARRAY_SIZE(sm6375_mdp), + .mdp =3D sm6375_mdp, + .ctl_count =3D ARRAY_SIZE(sm6375_ctl), + .ctl =3D sm6375_ctl, + .sspp_count =3D ARRAY_SIZE(sm6375_sspp), + .sspp =3D sm6375_sspp, + .mixer_count =3D ARRAY_SIZE(sm6375_lm), + .mixer =3D sm6375_lm, + .dspp_count =3D ARRAY_SIZE(sm6375_dspp), + .dspp =3D sm6375_dspp, + .pingpong_count =3D ARRAY_SIZE(sm6375_pp), + .pingpong =3D sm6375_pp, + .intf_count =3D ARRAY_SIZE(sm6375_intf), + .intf =3D sm6375_intf, + .vbif_count =3D ARRAY_SIZE(sm6375_vbif), + .vbif =3D sm6375_vbif, + .perf =3D &sm6375_perf_data, + .mdss_irqs =3D BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 52750b592b36..29516273dd6b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -440,6 +440,14 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk =3D= { }, }; =20 +static const struct dpu_lm_sub_blks sm6375_lm_sblk =3D { + .maxwidth =3D 2048, + .maxblendstages =3D 4, /* excluding base layer */ + .blendstage_base =3D { /* offsets relative to mixer base */ + 0x20, 0x38, 0x50, 0x68 + }, +}; + /* QCM2290 */ =20 static const struct dpu_lm_sub_blks qcm2290_lm_sblk =3D { @@ -751,6 +759,11 @@ static const struct dpu_qos_lut_entry sc7180_qos_linea= r[] =3D { {.fl =3D 0, .lut =3D 0x0011222222335777}, }; =20 +static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] =3D { + {.fl =3D 0, .lut =3D 0x0011223344556677 }, + {.fl =3D 0, .lut =3D 0x0011223445566777 }, +}; + static const struct dpu_qos_lut_entry sm8150_qos_linear[] =3D { {.fl =3D 0, .lut =3D 0x0011222222223357 }, }; @@ -808,6 +821,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_6_3_sm6115.h" #include "catalog/dpu_6_4_sm6350.h" #include "catalog/dpu_6_5_qcm2290.h" +#include "catalog/dpu_6_9_sm6375.h" =20 #include "catalog/dpu_7_0_sm8350.h" #include "catalog/dpu_7_2_sc7280.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index f9611bd75e02..b4f193037869 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -884,6 +884,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; +extern const struct dpu_mdss_cfg dpu_sm6375_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 46be7ad8d615..980c3c8f8269 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1287,6 +1287,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sc8280xp-dpu", .data =3D &dpu_sc8280xp_cfg, }, { .compatible =3D "qcom,sm6115-dpu", .data =3D &dpu_sm6115_cfg, }, { .compatible =3D "qcom,sm6350-dpu", .data =3D &dpu_sm6350_cfg, }, + { .compatible =3D "qcom,sm6375-dpu", .data =3D &dpu_sm6375_cfg, }, { .compatible =3D "qcom,sm8150-dpu", .data =3D &dpu_sm8150_cfg, }, { .compatible =3D "qcom,sm8250-dpu", .data =3D &dpu_sm8250_cfg, }, { .compatible =3D "qcom,sm8350-dpu", .data =3D &dpu_sm8350_cfg, }, --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC5BEC77B73 for ; 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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:38 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:19 +0200 Subject: [PATCH v2 10/13] drm/msm: mdss: Add SM6375 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-10-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=1357; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=IZraHC2rKjwAxvGejhLYdH/8ZPnRD2vaDl4IpBKvSDs=; b=FP2ipxs5Nr8YDG41US/6zI6ekAMslR4vE0K4u7LOeT1EivuPnX1w5tKQTXEck12W9qVTOEtDivz3 WuRS5/DZDjHC58OaEhn697/T/kdfsd1bZWmPg7vS1HYlJv1GAHpk X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for MDSS on SM6375. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/msm_mdss.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 4e3a5f0c303c..f2470ce699f7 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -546,6 +546,15 @@ static const struct msm_mdss_data sm6350_data =3D { .highest_bank_bit =3D 1, }; =20 +static const struct msm_mdss_data sm6375_data =3D { + .ubwc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D 6, + .ubwc_static =3D 0x1e, + /* Possibly 0 for LPDDR3 */ + .highest_bank_bit =3D 1, +}; + static const struct msm_mdss_data sm8150_data =3D { .ubwc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, @@ -580,6 +589,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &sc8280xp_data }, { .compatible =3D "qcom,sm6115-mdss", .data =3D &sm6115_data }, { .compatible =3D "qcom,sm6350-mdss", .data =3D &sm6350_data }, + { .compatible =3D "qcom,sm6375-mdss", .data =3D &sm6375_data }, { .compatible =3D "qcom,sm8150-mdss", .data =3D &sm8150_data }, { .compatible =3D "qcom,sm8250-mdss", .data =3D &sm8250_data }, { .compatible =3D "qcom,sm8350-mdss", .data =3D &sm8250_data }, --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25F17C7618E for ; Thu, 20 Apr 2023 22:32:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233173AbjDTWce (ORCPT ); Thu, 20 Apr 2023 18:32:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233058AbjDTWcL (ORCPT ); Thu, 20 Apr 2023 18:32:11 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87C1D5FE0 for ; Thu, 20 Apr 2023 15:31:41 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4ec88c67b2eso939653e87.1 for ; Thu, 20 Apr 2023 15:31:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682029900; x=1684621900; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=z7U+MQQRn266X/fu48wXlntxvnDdxvseAqEyvV5bnYU=; b=tMlxGgaR6TjY9h0TBPC//jlkuKqvmqB/3gCELO4fQHzbhqM1pN8tWw5LvbFYIMEFAx 2W7OizUDJ7IuE4yeBSwaonNURn0iha2+UHhiZRq+ZPzmsZ6oJJ6udJxD2ptavJ5iWxgb LhBoIarkiSGbTzPKLaNsjYWrh1W2ySxsIHaSfTwYeuQt2axkX9zm5bsuf+tAuvXDAGPF RybMNWmjB7IpiOJFEvXvk/QJsAbSrcIpGKZR20E/1ICfsQdRqG6X1+v0r/Qv8t49I0s0 y0JlgurZs8Nmwa9ZuqONoww3D7GdNClHsi2aGUU5viYJviBhqcpwXnerXS58bixKFHIQ yWjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682029900; x=1684621900; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z7U+MQQRn266X/fu48wXlntxvnDdxvseAqEyvV5bnYU=; b=iFP93HAPpdYAprQjbf+53Q47MpP162pI9kToNHlqi6bGkdkqYQgkV5e6oYok26CJCZ LvvapRIZPSebfSWZu42rm8znTuSdBJXjHknzuZuz0CnjZL3Zjy5Z9PAqysIKVe67y2QZ kR2RV1+WrICWU3OJZ9GyaOTszznGoreUUyLjMHSsymYoHug97vzAWy5mfmb5kkFYUsBt tfKb2a6Go8GMhy4lz8wUwOv61jR98cQ9Hrd1To9dXNSvdeLC2DVFwlOFxk/IrrOGw4ya RAA10eGZTbHBUzO4dloVzu3zwANdP+QgoPRUxTapxPAkp+HsCpb1qaCZ3vezn7biIPe2 g4qQ== X-Gm-Message-State: AAQBX9cQQ36g1Gm5dFhP3mgLgWbQywSJhQWjohSOhks+Wof3sCLWR/Mc J/Yidjv2ysFmKOBMKx8Ak5cNgg== X-Google-Smtp-Source: AKy350ZHaiUf6dhHxtQIv5/1RWQP/D8HT6ayzW/hPzmDLaYG8EmD3Kj8tDGo9DQ1XAOeCfV2w5oZjQ== X-Received: by 2002:a19:c503:0:b0:4db:513b:6ef4 with SMTP id w3-20020a19c503000000b004db513b6ef4mr861359lfe.11.1682029900156; Thu, 20 Apr 2023 15:31:40 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:39 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:20 +0200 Subject: [PATCH v2 11/13] iommu/arm-smmu-qcom: Add SM6375 DPU compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-11-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=785; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=/9HUTFzDlWhvA+x0Ieoh1uk/GJ56evseSi3zEZVI4y0=; b=ROJxpQig3kurlmL1S3QtRtECNCPVtfMcinbv+K27HQnjedkIX8uJX5aG6iQpvL9I7p/oUOGv9hbW FCr4DwNFAO+ezsbjZfziED0S7dhYav6nqfEfdzaeIBUDDYNQX+Nk X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the SM6375 DPU compatible to clients compatible list, as it also needs the workarounds. Signed-off-by: Konrad Dybcio Acked-by: Dmitry Baryshkov --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index ae09c627bc84..995ab5172883 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -255,6 +255,7 @@ static const struct of_device_id qcom_smmu_client_of_ma= tch[] __maybe_unused =3D { { .compatible =3D "qcom,sm8250-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, + { .compatible =3D "qcom,sm6375-mdss" }, { } }; =20 --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C600FC7618E for ; Thu, 20 Apr 2023 22:32:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233199AbjDTWci (ORCPT ); Thu, 20 Apr 2023 18:32:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233176AbjDTWcM (ORCPT ); Thu, 20 Apr 2023 18:32:12 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFAC67AA0 for ; Thu, 20 Apr 2023 15:31:43 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4ec816c9b62so949340e87.2 for ; Thu, 20 Apr 2023 15:31:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682029902; x=1684621902; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=UpOebqvOPbIqBzmR7NG/8rdRhqAcRj4FETPLZVvYR+0=; b=V0h1ZJjp6OhY4YDWAT7BDJ5ttf7U6iPjAi9Rcptq5HYQkQvwRLcYlr9TSkPIl+3ixf chauhhFx1ZN8Dfx0Xoq+3rCgOozjOiJ5wN+gqH/jJGiEYilnTuF87qQjPnr45ExRdyaT MbuNpZ3Or0OgZqfkZdOMgiGnx3OGnrLUVx8RI+O20k5lrzZ9pqeCd0sYU7wGItp31rO5 UM17D2dm3AmUkxEe6xbXTxQufjSkOI7oNM7mdQtuwOnTWrPhwSEr3MxOskjLi1qhvWVK gyL7IK1KLNdkklcmVQsrymJiAE9BCiwyr08xJ8xhRwjQHGbTY68hcw1AJN/Quol7kj2O WXsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682029902; x=1684621902; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UpOebqvOPbIqBzmR7NG/8rdRhqAcRj4FETPLZVvYR+0=; b=CJbeRSJ/Isg3nLisZk9BIr8Ea7JMnYWlfz72UDi12MDgGtkfmHwzqQ53sPHpyysgkN eVXR+KxA4M4PCOaVn0/x69cH5jJ+bhIFeYlZBKGUY285Ga9MUiVeLMjYa5KhKCFn5wu0 R2e6iLOONHZmq4u+DvDCHXJ9qXRLTlN5eolgqhmD3xnWUkL0ZNHd9y+o5t/ECayd9Qed 7cklMTCkr7uliCS/X+wXG8mmT2v/CXCZodQg8OhBmkJRR9PwmHB6UXdptB9i8jbcQw5O NdJWuJbXFlKzpR9DP2rdgL+NJw9uPL3GqQfUyjADkca/VEVuMHk23LT2Ie7KuBSvH8zl HLJg== X-Gm-Message-State: AAQBX9ebKhswEdRm1aU415wpL/IEbuSJIWp+4VWYRQkCFiz6l41ZTLcJ bMys70BGtPOIoG72JhnbrvKkFQ== X-Google-Smtp-Source: AKy350ax7WiiZ7sdUoOrCa6zqvzc4la3MYIVSoMYrIr6DOVfjS5Y91sf5cpvtfvB3sHU712yldza8Q== X-Received: by 2002:ac2:5204:0:b0:4dc:807a:d144 with SMTP id a4-20020ac25204000000b004dc807ad144mr905144lfl.39.1682029901820; Thu, 20 Apr 2023 15:31:41 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:41 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:21 +0200 Subject: [PATCH v2 12/13] iommu/arm-smmu-qcom: Add SM6350 DPU compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-12-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=884; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=evqQGLlTFOqHDOuiOF22m7xaO9yZbbtIXtz5YEiBVu0=; b=fwJivKHapHtCQymUF6p9dE6yEgcAcMF20Cmrb7Mbb0/7cBIbuYECeiyai+qF+fsnSn/sBz3WaMRJ hzP05E9EDpr2STBp7wbUGqCGO5QmuBw56ySUAbFzHTnr6Xh3ffb8 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Konrad Dybcio Add the SM6350 DPU compatible to clients compatible list, as it also needs the workarounds. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Acked-by: Dmitry Baryshkov --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 995ab5172883..2daaa600ac75 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -255,6 +255,7 @@ static const struct of_device_id qcom_smmu_client_of_ma= tch[] __maybe_unused =3D { { .compatible =3D "qcom,sm8250-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, + { .compatible =3D "qcom,sm6350-mdss" }, { .compatible =3D "qcom,sm6375-mdss" }, { } }; --=20 2.40.0 From nobody Wed Dec 17 10:04:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C7A2C77B7C for ; Thu, 20 Apr 2023 22:32:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233293AbjDTWco (ORCPT ); Thu, 20 Apr 2023 18:32:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233080AbjDTWcN (ORCPT ); Thu, 20 Apr 2023 18:32:13 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C33756A7C for ; Thu, 20 Apr 2023 15:31:45 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4eca19c3430so961732e87.1 for ; Thu, 20 Apr 2023 15:31:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682029903; x=1684621903; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=J8QyMbXoOHe4maJ/141Gl2opRXdF3vmPM4GP90Suqw8=; b=I0RuJim/ZifvTMm7CVHkzXSjJOF2vA532KiwtNLFVTQXWBbhF+e+ARmTjaDBf18orf qiKADkH5X0erT010RrJfLz4JiZfUTBQc7LnyAcaj+kXCPtP8M26HKUaUBYcmqV3JSio1 S0JmaO1Ubte8l9JRUmFkjhmj+gL5Fn27RRXMiCrkZacFiX+oNJ02ZpYQOPXkrT3fXswV upgGN5hgqC37TjWrUtT2TsWS1Di/+9IZzoWAl+LZj3XIq+61sTWVq8yl+sNFV5pUb4uM o7ddN/EfAW+F3mxpGcj2YWLcuCrMLKrcdKbyxgLN8tur0LLLWV/O9et6c8Hbry4HJtC3 v9ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682029903; x=1684621903; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J8QyMbXoOHe4maJ/141Gl2opRXdF3vmPM4GP90Suqw8=; b=aB0WUGx8x9aXfeaDbkwO89lhj5RH7NBkkb2QB6MdROHT56pqy/jMjqvwLk0Ro7WQan QYNZeoN+k+tHWoD/vtU8bfk6AEve3trF85gIwe+0wCENxIDEQ5DMf34sbAaHoEMeA5Mt Q5VZbQBjEoWhBqNn2PeTzpFzpG7XvJpyTBbT9J4q+sqkLeOWnpDz1cLsWgwrm+wUKfst Jc5TL+9uDxunYMterqO9e2owxgweyy00jvLnxNaS5fkXW0zW8KPM8gxsDtqCijugCCey VybuOsRverDLKtCZQb/hVt/gcN88Jsh2ExCQBpXp7bFCzMvZe3jVB0oD3KHwaqj7hvsI 6Lsw== X-Gm-Message-State: AAQBX9c0MCreMDGbu0e24Bc0Ti9nQZhhcbhvXzj/LUVRwCcMQmJUx96z dFVx4f/9xEPE7ikBg3vklw0mUw== X-Google-Smtp-Source: AKy350a1EqNhSqyvroEQFXEC3oNWZWKJ59j7Y7boNYcM6me6/l6zelpIdJE5bpeODyX5Mgx2NKVt3A== X-Received: by 2002:a05:6512:388e:b0:4eb:104b:bf61 with SMTP id n14-20020a056512388e00b004eb104bbf61mr801740lft.58.1682029903471; Thu, 20 Apr 2023 15:31:43 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:43 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:22 +0200 Subject: [PATCH v2 13/13] iommu/arm-smmu-qcom: Sort the compatible list alphabetically MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230411-topic-straitlagoon_mdss-v2-13-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=1047; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=4qlkXIpajO/screcnHozmWYEhsqRxqVWMGV9cb8adn0=; b=ku9MGWJ3g/n4SA+sMB5iIoSn/fJTWnS8wuxtVJXhCx8ML1znDgY0ILA0SMGsj+MXNuuj71iXZ8bD ZTVT1H7eBDFOQ12L6qLMqL1bRuGLZ14HOqrXVKTsCzbIlw32UOfb X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It got broken at some point, fix it up. Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 2daaa600ac75..e64c737724c4 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -251,12 +251,12 @@ static const struct of_device_id qcom_smmu_client_of_= match[] __maybe_unused =3D { { .compatible =3D "qcom,sc7280-mss-pil" }, { .compatible =3D "qcom,sc8180x-mdss" }, { .compatible =3D "qcom,sc8280xp-mdss" }, - { .compatible =3D "qcom,sm8150-mdss" }, - { .compatible =3D "qcom,sm8250-mdss" }, { .compatible =3D "qcom,sdm845-mdss" }, { .compatible =3D "qcom,sdm845-mss-pil" }, { .compatible =3D "qcom,sm6350-mdss" }, { .compatible =3D "qcom,sm6375-mdss" }, + { .compatible =3D "qcom,sm8150-mdss" }, + { .compatible =3D "qcom,sm8250-mdss" }, { } }; =20 --=20 2.40.0