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Mon, 10 Apr 2023 08:57:25 -0700 From: Shanker Donthineni To: Thomas Gleixner , Marc Zyngier CC: Sebastian Andrzej Siewior , Michael Walle , Shanker Donthineni , , Vikram Sethi Subject: [PATCH v3 3/3] genirq: Use the maple tree for IRQ descriptors management Date: Mon, 10 Apr 2023 10:57:21 -0500 Message-ID: <20230410155721.3720991-4-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230410155721.3720991-1-sdonthineni@nvidia.com> References: <20230410155721.3720991-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT056:EE_|DS7PR12MB6141:EE_ X-MS-Office365-Filtering-Correlation-Id: 722891f6-bc38-4e20-4e46-08db39dc4a82 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3EMqBGKM1l041qQ1mdAZzYD4vGJQ5jA+nJzZVky5s7RWdBfMGJDAutkd/w3TVvLAJGayK0t5TZbsP5dEQqeabmTtLfWv/HccK0dDFx2+TxhDh/JCmxAmY3C8hsxf3jymnXbx8mWwa5u7Eehjt9fOYknmFSj7ojmYcnzlUtrkItDC/UCNT9ykLKG8YYBhSLwD/g90hBHq7F5FNVn4DjKCZ4beL4eK9yZM8F/YOXkc4+6wTRvB6VFVoXNK123EU7pP4hqrpb+rgWaF69AcSaK6WnRk5d0WUxTKbskPC2ZHeUb82G2kYq/7hD7U1IWmEnIAOPW6zqh9I/FmW2vBl7eBz9dtyLYFBJktCyhKKEo0s0EBStVsQb4XnqjFPgCUBWMjtDDa4wYUqNxlZqkpiuuMyJKrPQPCyWVp41TdeGRM4Vs6+LL/BclxnHKtHS1JDrGJjNBe4vXsitx36O2MMUfiDKp4N5fFwCXjF11bSxOQ03WxZROyv7i84SENODVtLfDorB6Ua4H40tCIeHas4vuRA0gnPwItVSf6O+K7W0sSJDovQ6xB378ihURCM+8d2f2ZSbJS/cPwpmEKoKIRH8Y8V+COmzTCUiDrZkzmYeVIeMN7fvviyOoTsVwL4WCjg+cs8OdstyiMMU9cEBVUZnx/gnN/6GzYkMCnKLSdzPTOmiV6Lc7B25hSOaBjUnB/3xMaLMsCMUV41f1unPHo9pzr6AFqiM9vevtvXBN1shXfJg10/2C4IFknB8x+j7O1rPmz X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(136003)(346002)(396003)(376002)(451199021)(36840700001)(40470700004)(46966006)(66899021)(7696005)(478600001)(86362001)(40480700001)(47076005)(83380400001)(40460700003)(36756003)(82740400003)(7636003)(356005)(2616005)(36860700001)(336012)(426003)(6666004)(107886003)(2906002)(54906003)(110136005)(316002)(186003)(26005)(1076003)(5660300002)(41300700001)(8936002)(82310400005)(8676002)(70586007)(70206006)(4326008);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 15:57:30.7293 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 722891f6-bc38-4e20-4e46-08db39dc4a82 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6141 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The current implementation uses a static bitmap and a radix tree to manage IRQ allocation and irq_desc pointer store respectively. However, the size of the bitmap is constrained by the build time macro MAX_SPARSE_IRQS, which may not be sufficient to support the high-end servers, particularly those with GICv4.1 hardware, which require a large interrupt space to cover LPIs and vSGIs. The maple tree is a highly efficient data structure for storing non-overlapping ranges and can handle a large number of entries, up to ULONG_MAX. It can be utilized for both storing interrupt descriptors and identifying available free spaces. The interrupt descriptors management can be simplified by switching to a maple tree data structure, which offers greater flexibility and scalability. To support modern servers, the maximum number of IRQs has been increased to INT_MAX, which provides a more adequate value than the previous limit of NR_IRQS+8192. Signed-off-by: Shanker Donthineni --- kernel/irq/internals.h | 2 +- kernel/irq/irqdesc.c | 54 +++++++++++++++++++++++------------------- 2 files changed, 31 insertions(+), 25 deletions(-) diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index f3f2090dd2de..7bdb7507efb0 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -12,7 +12,7 @@ #include =20 #ifdef CONFIG_SPARSE_IRQ -# define MAX_SPARSE_IRQS (NR_IRQS + 8196) +# define MAX_SPARSE_IRQS INT_MAX #else # define MAX_SPARSE_IRQS NR_IRQS #endif diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index 9a71fc6f2c5f..d6d8120ffd56 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -12,8 +12,7 @@ #include #include #include -#include -#include +#include #include #include =20 @@ -131,17 +130,38 @@ int nr_irqs =3D NR_IRQS; EXPORT_SYMBOL_GPL(nr_irqs); =20 static DEFINE_MUTEX(sparse_irq_lock); -static DECLARE_BITMAP(allocated_irqs, MAX_SPARSE_IRQS); +static struct maple_tree sparse_irqs =3D MTREE_INIT_EXT(sparse_irqs, + MT_FLAGS_ALLOC_RANGE | + MT_FLAGS_LOCK_EXTERN | + MT_FLAGS_USE_RCU, + sparse_irq_lock); =20 static int irq_find_free_area(unsigned int from, unsigned int cnt) { - return bitmap_find_next_zero_area(allocated_irqs, MAX_SPARSE_IRQS, - from, cnt, 0); + MA_STATE(mas, &sparse_irqs, 0, 0); + + if (mas_empty_area(&mas, from, MAX_SPARSE_IRQS, cnt)) + return -ENOSPC; + return mas.index; } =20 static unsigned int irq_find_next_irq(unsigned int offset) { - return find_next_bit(allocated_irqs, nr_irqs, offset); + struct irq_desc *desc =3D mt_next(&sparse_irqs, offset, nr_irqs); + + return desc ? irq_desc_get_irq(desc) : nr_irqs; +} + +static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) +{ + MA_STATE(mas, &sparse_irqs, irq, irq); + WARN_ON(mas_store_gfp(&mas, desc, GFP_KERNEL) !=3D 0); +} + +static void delete_irq_desc(unsigned int irq) +{ + MA_STATE(mas, &sparse_irqs, irq, irq); + mas_erase(&mas); } =20 #ifdef CONFIG_SPARSE_IRQ @@ -355,26 +375,14 @@ static void irq_sysfs_del(struct irq_desc *desc) {} =20 #endif /* CONFIG_SYSFS */ =20 -static RADIX_TREE(irq_desc_tree, GFP_KERNEL); - -static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) -{ - radix_tree_insert(&irq_desc_tree, irq, desc); -} - struct irq_desc *irq_to_desc(unsigned int irq) { - return radix_tree_lookup(&irq_desc_tree, irq); + return mtree_load(&sparse_irqs, irq); } #ifdef CONFIG_KVM_BOOK3S_64_HV_MODULE EXPORT_SYMBOL_GPL(irq_to_desc); #endif =20 -static void delete_irq_desc(unsigned int irq) -{ - radix_tree_delete(&irq_desc_tree, irq); -} - #ifdef CONFIG_SMP static void free_masks(struct irq_desc *desc) { @@ -517,7 +525,6 @@ static int alloc_descs(unsigned int start, unsigned int= cnt, int node, irq_sysfs_add(start + i, desc); irq_add_debugfs_entry(start + i, desc); } - bitmap_set(allocated_irqs, start, cnt); return start; =20 err: @@ -557,7 +564,6 @@ int __init early_irq_init(void) =20 for (i =3D 0; i < initcnt; i++) { desc =3D alloc_desc(i, node, 0, NULL, NULL); - set_bit(i, allocated_irqs); irq_insert_desc(i, desc); } return arch_early_irq_init(); @@ -612,6 +618,7 @@ static void free_desc(unsigned int irq) raw_spin_lock_irqsave(&desc->lock, flags); desc_set_defaults(irq, desc, irq_desc_get_node(desc), NULL, NULL); raw_spin_unlock_irqrestore(&desc->lock, flags); + delete_irq_desc(irq); } =20 static inline int alloc_descs(unsigned int start, unsigned int cnt, int no= de, @@ -624,8 +631,8 @@ static inline int alloc_descs(unsigned int start, unsig= ned int cnt, int node, struct irq_desc *desc =3D irq_to_desc(start + i); =20 desc->owner =3D owner; + irq_insert_desc(start + i, desc); } - bitmap_set(allocated_irqs, start, cnt); return start; } =20 @@ -637,7 +644,7 @@ static int irq_expand_nr_irqs(unsigned int nr) void irq_mark_irq(unsigned int irq) { mutex_lock(&sparse_irq_lock); - bitmap_set(allocated_irqs, irq, 1); + irq_insert_desc(irq, irq_desc + irq); mutex_unlock(&sparse_irq_lock); } =20 @@ -781,7 +788,6 @@ void irq_free_descs(unsigned int from, unsigned int cnt) for (i =3D 0; i < cnt; i++) free_desc(from + i); =20 - bitmap_clear(allocated_irqs, from, cnt); mutex_unlock(&sparse_irq_lock); } EXPORT_SYMBOL_GPL(irq_free_descs); --=20 2.25.1