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Mon, 10 Apr 2023 14:00:42 GMT Received: from devipriy-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Mon, 10 Apr 2023 07:00:32 -0700 From: Devi Priya To: , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V12 3/4] arm64: dts: qcom: Add support for ipq9574 SoC and RDP433 variant Date: Mon, 10 Apr 2023 19:29:47 +0530 Message-ID: <20230410135948.11970-4-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230410135948.11970-1-quic_devipriy@quicinc.com> References: <20230410135948.11970-1-quic_devipriy@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: B1uQVkc9PrixcLHQQeT0zXTaqsliSlD- X-Proofpoint-ORIG-GUID: B1uQVkc9PrixcLHQQeT0zXTaqsliSlD- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-10_10,2023-04-06_03,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 mlxscore=0 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 adultscore=0 bulkscore=0 mlxlogscore=999 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304100118 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add initial device tree support for Qualcomm IPQ9574 SoC and Reference Design Platform(RDP) 433 which is based on IPQ9574 family of SoCs Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Co-developed-by: Poovendhan Selvaraj Signed-off-by: Poovendhan Selvaraj Signed-off-by: Devi Priya Reviewed-by: Konrad Dybcio --- Changes in V12: - Updated the size of GICC and GICV region to 8kB - Added target CPU encoding arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 84 +++++++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 263 ++++++++++++++++++++ 3 files changed, 348 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index f6ff4024a60e..3e48393dd9d4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq8074-hk10-c2.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-asus-z00l.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/= dts/qcom/ipq9574-rdp433.dts new file mode 100644 index 000000000000..2ce8e09e7565 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP433 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; + compatible =3D "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; + + aliases { + serial0 =3D &blsp1_uart2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&blsp1_uart2 { + pinctrl-0 =3D <&uart2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&sdhc_1 { + pinctrl-0 =3D <&sdc_default_state>; + pinctrl-names =3D "default"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency =3D <384000000>; + bus-width =3D <8>; + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins =3D "gpio5"; + function =3D "sdc_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio4"; + function =3D "sdc_cmd"; + drive-strength =3D <8>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", + "gpio3", "gpio6", "gpio7", + "gpio8", "gpio9"; + function =3D "sdc_data"; + drive-strength =3D <8>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "gpio10"; + function =3D "sdc_rclk"; + drive-strength =3D <8>; + bias-pull-down; + }; + }; +}; + +&xo_board_clk { + clock-frequency =3D <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi new file mode 100644 index 000000000000..f1f959b43180 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 SoC device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a73"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + CPU1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a73"; + reg =3D <0x1>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + CPU2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a73"; + reg =3D <0x2>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + CPU3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a73"; + reg =3D <0x3>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + L2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + }; + }; + + memory@40000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x40000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,cortex-a73-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + tz_region: tz@4a600000 { + reg =3D <0x0 0x4a600000 0x0 0x400000>; + no-map; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0 0xffffffff>; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,ipq9574-tlmm"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 65>; + interrupt-controller; + #interrupt-cells =3D <2>; + + uart2_pins: uart2-state { + pins =3D "gpio34", "gpio35"; + function =3D "blsp2_uart"; + drive-strength =3D <8>; + bias-disable; + }; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,ipq9574-gcc"; + reg =3D <0x01800000 0x80000>; + clocks =3D <&xo_board_clk>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + sdhc_1: mmc@7804000 { + compatible =3D "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x07804000 0x1000>, <0x07805000 0x1000>; + reg-names =3D "hc", "cqhci"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board_clk>; + clock-names =3D "iface", "core", "xo"; + non-removable; + status =3D "disabled"; + }; + + blsp1_uart2: serial@78b1000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078b1000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART3_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + status =3D "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + reg =3D <0x0b000000 0x1000>, /* GICD */ + <0x0b002000 0x2000>, /* GICC */ + <0x0b001000 0x1000>, /* GICH */ + <0x0b004000 0x2000>; /* GICV */ + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-controller; + #interrupt-cells =3D <3>; + interrupts =3D ; + ranges =3D <0 0x0b00c000 0x3000>; + + v2m0: v2m@0 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x00000000 0xffd>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x00001000 0xffd>; + msi-controller; + }; + + v2m2: v2m@2000 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x00002000 0xffd>; + msi-controller; + }; + }; + + timer@b120000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0b120000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + frame@b120000 { + reg =3D <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@b123000 { + reg =3D <0x0b123000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b124000 { + reg =3D <0x0b124000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b125000 { + reg =3D <0x0b125000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b126000 { + reg =3D <0x0b126000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b127000 { + reg =3D <0x0b127000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b128000 { + reg =3D <0x0b128000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.17.1