From nobody Wed Feb 11 18:26:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C4AAC77B61 for ; Mon, 10 Apr 2023 11:09:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229821AbjDJLJr (ORCPT ); Mon, 10 Apr 2023 07:09:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229660AbjDJLJo (ORCPT ); Mon, 10 Apr 2023 07:09:44 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EBAB5BB5; Mon, 10 Apr 2023 04:09:17 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id h24so4525542plr.1; Mon, 10 Apr 2023 04:09:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mWJIHJN97kYoJ38RctmRsN2DU2i8m+C9aLZTSJfRMII=; b=VHrNTTn9O0v4eIr0DKLvDoXcuFbN4T2kdw8XCIZgNmiWxqggFSG5V9P8B2olsSRcN7 f8qHSZa+K4+dLPujdOiOd/PFZfL5SLOEHHjgMa9MriyOI7N/DrC4YuSegwgdyV+oedkr WIZ/QGfDiAJes5+/SvM00Ho7edEbIZ0qm8Xk/yV7z+d3g+zQq6Pn5Z9u0q0C19ZMa6fc zLVicXxfQ0/xnM+al9MT3CP522vL/9n0Q8dXouJDCKHSnc0y4e/YcNGs3/b1Vtj/Ds5h W4KWRVrV4Uzjo7Ilz7PiIywN9z0OffelklZvBX6NDnovfvi6fFGsVOhkn3NNZ+praw0+ ArZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mWJIHJN97kYoJ38RctmRsN2DU2i8m+C9aLZTSJfRMII=; b=2MCbgplYRS8ipCCl+L8NaOzVwxYF285dAnYgrE1t5LXBwUXaOHpxD/gY5LUZVCLw9o I4EHGlv6ybkJY/lj2GxRkQyWcVDmSas6Z5BJ2koE6dQWJ0gFAKFWYpdDb6uo5Ko3IFVx XDpjfmbfT8ZVwkd375tnbz8suv7A8hDsLHYGN/x2qx/Ouvvp4sR3SNfppTs2v9Slc8CO mDdiRQe3F6AxD9mnCyJDeY+I1EJvD8g/xXNZdGnCibka66lRbRMsTb5ruIzCyvSp0t2p hPhJzRum/do5ao4cF5bMiGL9gFqIS48Cu84GlfPkygKn34/IlgoiNwerDILvxn+bR8Z4 I6LQ== X-Gm-Message-State: AAQBX9cxXEsr5Zze68axAaQQCmZInOBCRrIfD1vYlspmzVGcS945Bw/+ 5D6gt27GQdsvVUyL9qzDrdCDJ4T1b9oNSwysjxQ= X-Google-Smtp-Source: AKy350ZqpLIkI/FMx7ysvL1AuBIvMa77jy5q9i2KZQ2VRYdtWSvUKJZ7aJ4u+n891+0z1RcBach8Rg== X-Received: by 2002:a17:902:d488:b0:19a:9610:b234 with SMTP id c8-20020a170902d48800b0019a9610b234mr12176120plg.1.1681124956396; Mon, 10 Apr 2023 04:09:16 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:09:16 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, Conor Dooley , Nick Alcock Subject: [PATCH v3 07/14] clk: hisilicon: hi3559a: Use helper functions Date: Mon, 10 Apr 2023 19:07:19 +0800 Message-Id: <20230410110733.192151-8-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3559a.c | 232 +++++----------------------- 1 file changed, 37 insertions(+), 195 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/cl= k-hi3559a.c index 8036bd8cbb0a..9844e86ec146 100644 --- a/drivers/clk/hisilicon/clk-hi3559a.c +++ b/drivers/clk/hisilicon/clk-hi3559a.c @@ -11,7 +11,6 @@ #include #include #include -#include =20 #include =20 @@ -452,21 +451,23 @@ static const struct clk_ops hisi_clk_pll_ops =3D { .recalc_rate =3D clk_pll_recalc_rate, }; =20 -static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, - int nums, struct hisi_clock_data *data, struct device *dev) +static int +hisi_clk_register_pll(struct device *dev, const void *clocks, + size_t num, struct hisi_clock_data *data) { + const struct hi3559av100_pll_clock *clks =3D clocks; void __iomem *base =3D data->base; struct hi3559av100_clk_pll *p_clk =3D NULL; struct clk *clk =3D NULL; struct clk_init_data init; int i; =20 - p_clk =3D devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL); + p_clk =3D devm_kzalloc(dev, sizeof(*p_clk) * num, GFP_KERNEL); =20 if (!p_clk) - return; + return -ENOMEM; =20 - for (i =3D 0; i < nums; i++) { + for (i =3D 0; i < num; i++) { init.name =3D clks[i].name; init.flags =3D 0; init.parent_names =3D @@ -494,78 +495,27 @@ static void hisi_clk_register_pll(struct hi3559av100_= pll_clock *clks, devm_kfree(dev, p_clk); dev_err(dev, "%s: failed to register clock %s\n", __func__, clks[i].name); - continue; + return PTR_ERR(clk); } =20 data->clk_data.clks[clks[i].id] =3D clk; p_clk++; } -} - -static struct hisi_clock_data *hi3559av100_clk_register( - struct platform_device *pdev) -{ - struct hisi_clock_data *clk_data; - int ret; - - clk_data =3D hisi_clk_alloc(pdev, HI3559AV100_CRG_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - ret =3D hisi_clk_register_fixed_rate(hi3559av100_fixed_rate_clks_crg, - ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data); - if (ret) - return ERR_PTR(ret); - - hisi_clk_register_pll(hi3559av100_pll_clks, - ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev); - - ret =3D hisi_clk_register_mux(hi3559av100_mux_clks_crg, - ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data); - if (ret) - goto unregister_fixed_rate; - - ret =3D hisi_clk_register_gate(hi3559av100_gate_clks, - ARRAY_SIZE(hi3559av100_gate_clks), clk_data); - if (ret) - goto unregister_mux; - - ret =3D of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3559av100_gate_clks, - ARRAY_SIZE(hi3559av100_gate_clks), clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3559av100_mux_clks_crg, - ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg, - ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data); - return ERR_PTR(ret); -} =20 -static void hi3559av100_clk_unregister(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3559av100_gate_clks, - ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data); - hisi_clk_unregister_mux(hi3559av100_mux_clks_crg, - ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg, - ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data); + return 0; } =20 -static const struct hisi_crg_funcs hi3559av100_crg_funcs =3D { - .register_clks =3D hi3559av100_clk_register, - .unregister_clks =3D hi3559av100_clk_unregister, +static const struct hisi_clocks hi3559av100_clks =3D { + .nr =3D HI3559AV100_CRG_NR_CLKS, + .fixed_rate_clks =3D hi3559av100_fixed_rate_clks_crg, + .fixed_rate_clks_num =3D ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), + .mux_clks =3D hi3559av100_mux_clks_crg, + .mux_clks_num =3D ARRAY_SIZE(hi3559av100_mux_clks_crg), + .gate_clks =3D hi3559av100_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3559av100_gate_clks), + .customized_clks =3D hi3559av100_pll_clks, + .customized_clks_num =3D ARRAY_SIZE(hi3559av100_pll_clks), + .clk_register_customized =3D hisi_clk_register_pll, }; =20 static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[] =3D= { @@ -673,7 +623,7 @@ static struct hisi_gate_clock hi3559av100_shub_gate_clk= s[] =3D { }, }; =20 -static int hi3559av100_shub_default_clk_set(void) +static int hi3559av100_shub_default_clk_set(struct device *dev, struct his= i_clock_data *data) { void __iomem *crg_base; unsigned int val; @@ -696,149 +646,41 @@ static int hi3559av100_shub_default_clk_set(void) return 0; } =20 -static struct hisi_clock_data *hi3559av100_shub_clk_register( - struct platform_device *pdev) -{ - struct hisi_clock_data *clk_data =3D NULL; - int ret; - - hi3559av100_shub_default_clk_set(); - - clk_data =3D hisi_clk_alloc(pdev, HI3559AV100_SHUB_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - ret =3D hisi_clk_register_fixed_rate(hi3559av100_shub_fixed_rate_clks, - ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data); - if (ret) - return ERR_PTR(ret); - - ret =3D hisi_clk_register_mux(hi3559av100_shub_mux_clks, - ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data); - if (ret) - goto unregister_fixed_rate; - - ret =3D hisi_clk_register_divider(hi3559av100_shub_div_clks, - ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data); - if (ret) - goto unregister_mux; - - ret =3D hisi_clk_register_gate(hi3559av100_shub_gate_clks, - ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data); - if (ret) - goto unregister_factor; - - ret =3D of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3559av100_shub_gate_clks, - ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data); -unregister_factor: - hisi_clk_unregister_divider(hi3559av100_shub_div_clks, - ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3559av100_shub_mux_clks, - ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks, - ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data); - return ERR_PTR(ret); -} - -static void hi3559av100_shub_clk_unregister(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3559av100_shub_gate_clks, - ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data); - hisi_clk_unregister_divider(hi3559av100_shub_div_clks, - ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data); - hisi_clk_unregister_mux(hi3559av100_shub_mux_clks, - ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks, - ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data); -} - -static const struct hisi_crg_funcs hi3559av100_shub_crg_funcs =3D { - .register_clks =3D hi3559av100_shub_clk_register, - .unregister_clks =3D hi3559av100_shub_clk_unregister, +static const struct hisi_clocks hi3559av100_shub_clks =3D { + .nr =3D HI3559AV100_SHUB_NR_CLKS, + .prologue =3D hi3559av100_shub_default_clk_set, + .fixed_rate_clks =3D hi3559av100_shub_fixed_rate_clks, + .fixed_rate_clks_num =3D ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), + .mux_clks =3D hi3559av100_shub_mux_clks, + .mux_clks_num =3D ARRAY_SIZE(hi3559av100_shub_mux_clks), + .divider_clks =3D hi3559av100_shub_div_clks, + .divider_clks_num =3D ARRAY_SIZE(hi3559av100_shub_div_clks), + .gate_clks =3D hi3559av100_shub_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hi3559av100_shub_gate_clks), }; =20 static const struct of_device_id hi3559av100_crg_match_table[] =3D { { .compatible =3D "hisilicon,hi3559av100-clock", - .data =3D &hi3559av100_crg_funcs + .data =3D &hi3559av100_clks }, { .compatible =3D "hisilicon,hi3559av100-shub-clock", - .data =3D &hi3559av100_shub_crg_funcs + .data =3D &hi3559av100_shub_clks }, { } }; MODULE_DEVICE_TABLE(of, hi3559av100_crg_match_table); =20 -static int hi3559av100_crg_probe(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg; - - crg =3D devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); - if (!crg) - return -ENOMEM; - - crg->funcs =3D of_device_get_match_data(&pdev->dev); - if (!crg->funcs) - return -ENOENT; - - crg->rstc =3D hisi_reset_init(pdev); - if (!crg->rstc) - return -ENOMEM; - - crg->clk_data =3D crg->funcs->register_clks(pdev); - if (IS_ERR(crg->clk_data)) { - hisi_reset_exit(crg->rstc); - return PTR_ERR(crg->clk_data); - } - - platform_set_drvdata(pdev, crg); - return 0; -} - -static int hi3559av100_crg_remove(struct platform_device *pdev) -{ - struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); - - hisi_reset_exit(crg->rstc); - crg->funcs->unregister_clks(pdev); - return 0; -} - static struct platform_driver hi3559av100_crg_driver =3D { - .probe =3D hi3559av100_crg_probe, - .remove =3D hi3559av100_crg_remove, + .probe =3D hisi_crg_probe, + .remove =3D hisi_crg_remove, .driver =3D { .name =3D "hi3559av100-clock", .of_match_table =3D hi3559av100_crg_match_table, }, }; =20 -static int __init hi3559av100_crg_init(void) -{ - return platform_driver_register(&hi3559av100_crg_driver); -} -core_initcall(hi3559av100_crg_init); - -static void __exit hi3559av100_crg_exit(void) -{ - platform_driver_unregister(&hi3559av100_crg_driver); -} -module_exit(hi3559av100_crg_exit); - +module_platform_driver(hi3559av100_crg_driver); =20 MODULE_DESCRIPTION("HiSilicon Hi3559AV100 CRG Driver"); --=20 2.39.2