From nobody Wed Feb 11 18:21:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8174FC77B70 for ; Mon, 10 Apr 2023 11:11:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229904AbjDJLLE (ORCPT ); Mon, 10 Apr 2023 07:11:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229902AbjDJLLB (ORCPT ); Mon, 10 Apr 2023 07:11:01 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DE395252; Mon, 10 Apr 2023 04:10:37 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id c3so4792813pjg.1; Mon, 10 Apr 2023 04:10:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681125036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eAEODm1kNNhfhQehFrRwXlq3FhwRoxU54wQDsxuZLBY=; b=mneeEP5/S/ifs7vAoq84uXh0uh/1PHr3A6Rlsz4YpVabICVyO58KO8z0pkVTYOO6Vv YPFwZ1G7z6SaeeqYhGd0hI7mt3kfv2bwUxsIIJE1s+ikd4033gOl7n/UNJT7E2IJDSAq kFsOO/c4lU5pwZhOxVaUzM4/50eMvrIu3CXobF75qL8c4N8NJiK+hkqRX1x+uP/ghZeO tIxZVoxZJeDDgzcQ9LeCCG30TjJh9GfT+gaVfJyZlI42UX6iuF6r6I9AihEQTdvUf0F7 Rv5QrwlWnmoWllJ1aeJkyMK0VyY+FgSQpGQB5R8oIjeziyMxWinB2VLknPXe0/Z0wNWw rtyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681125036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eAEODm1kNNhfhQehFrRwXlq3FhwRoxU54wQDsxuZLBY=; b=q4+S11hYOpML72rA1ehDQKNE+J3pDPTKpPyGO3E60NfhQKLVKhRpGmYo3Q/4qW94td VbnVloQ9cVDOu0/XzpFV/jwZijgNtGHolG0noSUGGIUnU63wmn1UYgxN2uBNE8BjFNBG NvYopAFb6AyxivEnMyYa1BMZT1Vm0Jej9uhlKjQOGW9O+QTXg/cFlHUTl4X2uAlDVXtI x90oJA2dF11Ym5qprJ/DLZ20xJ2wmv4/KMb2ESAq4l45nvAxmlH56hrIv5XRdjxbIIQr kmDs8xORffT+Hcop8BaS7vWSyxmRxcK6IO1jDhMVX4Fc+pV85+dnb7Ym/DuvQ1ZJFmDB 63CA== X-Gm-Message-State: AAQBX9dQDQzdztmZHaMKpErH5Glq/n7aj1OoTDYIMojXWjcpgRjM1Y3y JNchRYtLxQ5wpn6NtOwUbnVvVP9D/s9OOURsm7Q= X-Google-Smtp-Source: AKy350b6sZFtdUOnupQ4WVqwXWHjs/igJADJyuqotR+Moyqgsnpxpwl60WoYmf68N6VMf8PM1y5z8A== X-Received: by 2002:a17:902:e749:b0:1a1:e93c:8937 with SMTP id p9-20020a170902e74900b001a1e93c8937mr14101810plf.35.1681125036086; Mon, 10 Apr 2023 04:10:36 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:10:35 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 13/14] clk: hisilicon: hix5hd2: Convert into platform driver module Date: Mon, 10 Apr 2023 19:07:25 +0800 Message-Id: <20230410110733.192151-14-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hix5hd2.c | 85 ++++++++++++++++++----------- 1 file changed, 52 insertions(+), 33 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/cl= k-hix5hd2.c index 64bdd3f05725..fb0f5d2745b2 100644 --- a/drivers/clk/hisilicon/clk-hix5hd2.c +++ b/drivers/clk/hisilicon/clk-hix5hd2.c @@ -4,13 +4,17 @@ * Copyright (c) 2014 Hisilicon Limited. */ =20 -#include #include + #include #include +#include +#include +#include + #include "clk.h" =20 -static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = =3D { +static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] =3D { { HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 1200000000, }, { HIX5HD2_FIXED_400M, "400m", NULL, 0, 400000000, }, { HIX5HD2_FIXED_48M, "48m", NULL, 0, 48000000, }, @@ -43,19 +47,19 @@ static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_= clks[] __initdata =3D { { HIX5HD2_FIXED_83M, "83m", NULL, 0, 83333333, }, }; =20 -static const char *const sfc_mux_p[] __initconst =3D { +static const char *const sfc_mux_p[] =3D { "24m", "150m", "200m", "100m", "75m", }; static u32 sfc_mux_table[] =3D {0, 4, 5, 6, 7}; =20 -static const char *const sdio_mux_p[] __initconst =3D { +static const char *const sdio_mux_p[] =3D { "75m", "100m", "50m", "15m", }; static u32 sdio_mux_table[] =3D {0, 1, 2, 3}; =20 -static const char *const fephy_mux_p[] __initconst =3D { "25m", "125m"}; +static const char *const fephy_mux_p[] =3D { "25m", "125m"}; static u32 fephy_mux_table[] =3D {0, 1}; =20 =20 -static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata =3D { +static struct hisi_mux_clock hix5hd2_mux_clks[] =3D { { HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p), CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, }, { HIX5HD2_MMC_MUX, "mmc_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p), @@ -67,7 +71,7 @@ static struct hisi_mux_clock hix5hd2_mux_clks[] __initdat= a =3D { CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, }, }; =20 -static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata =3D { +static struct hisi_gate_clock hix5hd2_gate_clks[] =3D { /* sfc */ { HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux", CLK_SET_RATE_PARENT, 0x5c, 0, 0, }, @@ -153,7 +157,7 @@ struct hix5hd2_clk_complex { u32 phy_rst_mask; }; =20 -static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata =3D { +static struct hix5hd2_complex_clock hix5hd2_complex_clks[] =3D { {"clk_mac0", "clk_fephy", HIX5HD2_MAC0_CLK, 0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER}, {"clk_mac1", "clk_fwd_sys", HIX5HD2_MAC1_CLK, @@ -249,21 +253,22 @@ static const struct clk_ops clk_complex_ops =3D { .disable =3D clk_complex_disable, }; =20 -static void __init -hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums, +static int +hix5hd2_clk_register_complex(struct device *dev, const void *clocks, size_= t num, struct hisi_clock_data *data) { + const struct hix5hd2_complex_clock *clks =3D clocks; void __iomem *base =3D data->base; int i; =20 - for (i =3D 0; i < nums; i++) { + for (i =3D 0; i < num; i++) { struct hix5hd2_clk_complex *p_clk; struct clk *clk; struct clk_init_data init; =20 p_clk =3D kzalloc(sizeof(*p_clk), GFP_KERNEL); if (!p_clk) - return; + return -ENOMEM; =20 init.name =3D clks[i].name; if (clks[i].type =3D=3D TYPE_ETHER) @@ -289,31 +294,45 @@ hix5hd2_clk_register_complex(struct hix5hd2_complex_c= lock *clks, int nums, kfree(p_clk); pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - continue; + return PTR_ERR(p_clk); } =20 data->clk_data.clks[clks[i].id] =3D clk; } -} =20 -static void __init hix5hd2_clk_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data =3D hisi_clk_init(np, HIX5HD2_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks, - ARRAY_SIZE(hix5hd2_fixed_rate_clks), - clk_data); - hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks), - clk_data); - hisi_clk_register_gate(hix5hd2_gate_clks, - ARRAY_SIZE(hix5hd2_gate_clks), clk_data); - hix5hd2_clk_register_complex(hix5hd2_complex_clks, - ARRAY_SIZE(hix5hd2_complex_clks), - clk_data); + return 0; } =20 -CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init); +static const struct hisi_clocks hix5hd2_clks =3D { + .nr =3D HIX5HD2_NR_CLKS, + .fixed_rate_clks =3D hix5hd2_fixed_rate_clks, + .fixed_factor_clks_num =3D ARRAY_SIZE(hix5hd2_fixed_rate_clks), + .mux_clks =3D hix5hd2_mux_clks, + .mux_clks_num =3D ARRAY_SIZE(hix5hd2_mux_clks), + .gate_clks =3D hix5hd2_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hix5hd2_gate_clks), + .customized_clks =3D hix5hd2_complex_clks, + .customized_clks_num =3D ARRAY_SIZE(hix5hd2_complex_clks), + .clk_register_customized =3D hix5hd2_clk_register_complex, +}; + +static const struct of_device_id hix5hd2_clk_match_table[] =3D { + { .compatible =3D "hisilicon,hix5hd2-clock", + .data =3D &hix5hd2_clks }, + { } +}; +MODULE_DEVICE_TABLE(of, hix5hd2_clk_match_table); + +static struct platform_driver hix5hd2_clk_driver =3D { + .probe =3D hisi_clk_probe, + .remove =3D hisi_clk_remove, + .driver =3D { + .name =3D "hix5hd2-clock", + .of_match_table =3D hix5hd2_clk_match_table, + }, +}; + +module_platform_driver(hix5hd2_clk_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("HiSilicon Hix5hd2 Clock Driver"); --=20 2.39.2