From nobody Wed Feb 11 18:21:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90234C76196 for ; Mon, 10 Apr 2023 11:10:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229881AbjDJLKR (ORCPT ); Mon, 10 Apr 2023 07:10:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229864AbjDJLKP (ORCPT ); Mon, 10 Apr 2023 07:10:15 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 198485FDF; Mon, 10 Apr 2023 04:09:57 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id c3so4791254pjg.1; Mon, 10 Apr 2023 04:09:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681124996; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d8THw7JnJanTYN5Mzg50ak80LMXfCHljznWSdJ2R52o=; b=nQ3uGdQPuHWOy4+3+Bj7HH/gwg3VDoIyru+LSV+JW0wY+eEULQhqjC07pEW79inaUg 5uYYoU9DOCv7YKRVBi8u+N+5HOuHRRKpeehmUrMXOEFuEVI7wKo7WD/gOugYZK4wxp56 KunEZQXR+BdEDEpwGxBNQhYsS5qdzB86K9PdEvPkmPAuJSZwnUez4AAOxcm2EXq+NIr2 BoZPHkszAIBf+5heFtkfnQMlAlOZwbzUjNTCQ+qshyMv8lyUagx59pnvRNdLmYhBh+C9 R4mdBoq9CEasMdvkcspffVN0wzlsJglTefOIY7Yus3gi4MvnjlFKTK504vq1WWhyP5RB ebNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681124996; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d8THw7JnJanTYN5Mzg50ak80LMXfCHljznWSdJ2R52o=; b=I1P30nEfbqa6kN2jRSNNAamU1kr/Wqbw9oX3Kf8y+4PNPDE+rZVyBxJj0Sp1TMMU/i 6NZVIc8NfUSZvSGLHUrGWdDtSqkZJNvUk4xqko1TayAPCubA/U7DuoreiMehNtv7jxKN EM0Qv7E7y5qQZ2jbvXji5lVfmdkyrFqMl2O776Ig4XVp1yvR3EtZ1JKbB/Cc9czXbcRK 47cXjuaLOA1VwfnYPB9X1lyWZcm9dTlLzvd5xofe+2/empFATLBexT3cXPjGOyyCW99U R1tsNeT2wHUTOQj2p4b70tgM8GKtCPoRuKvpFY4N75C0dh6sIkSsafK6kK5uekIJC+73 ysFA== X-Gm-Message-State: AAQBX9deOVrD5y/6gidJL/cfpkH0uFsz2qmDd5kSmmn+dCsiFU/8tv2L 1dLCG176OgiULTi7+fzUcZT9d8QV8LBo19TIquc= X-Google-Smtp-Source: AKy350a/aMn2SI1Bqo6ycoyhOUn2Zs3O3V6hc2dLSWy5fsfi63Qcy3wk+rW+yDNWDm1tRS8deYkwxA== X-Received: by 2002:a17:902:d488:b0:19a:9610:b234 with SMTP id c8-20020a170902d48800b0019a9610b234mr12178694plg.1.1681124996166; Mon, 10 Apr 2023 04:09:56 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm7464728pls.216.2023.04.10.04.09.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 04:09:55 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v3 10/14] clk: hisilicon: hi3620: Convert into platform driver module Date: Mon, 10 Apr 2023 19:07:22 +0800 Message-Id: <20230410110733.192151-11-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410110733.192151-1-mmyangfl@gmail.com> References: <20230410110733.192151-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use common helper functions and register clks with a single of_device_id data. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3620.c | 189 +++++++++++++++-------------- 1 file changed, 96 insertions(+), 93 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk= -hi3620.c index a3d04c7c3da8..464b7887415c 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -22,48 +23,48 @@ #include "clk.h" =20 /* clock parent list */ -static const char *const timer0_mux_p[] __initconst =3D { "osc32k", "timer= clk01", }; -static const char *const timer1_mux_p[] __initconst =3D { "osc32k", "timer= clk01", }; -static const char *const timer2_mux_p[] __initconst =3D { "osc32k", "timer= clk23", }; -static const char *const timer3_mux_p[] __initconst =3D { "osc32k", "timer= clk23", }; -static const char *const timer4_mux_p[] __initconst =3D { "osc32k", "timer= clk45", }; -static const char *const timer5_mux_p[] __initconst =3D { "osc32k", "timer= clk45", }; -static const char *const timer6_mux_p[] __initconst =3D { "osc32k", "timer= clk67", }; -static const char *const timer7_mux_p[] __initconst =3D { "osc32k", "timer= clk67", }; -static const char *const timer8_mux_p[] __initconst =3D { "osc32k", "timer= clk89", }; -static const char *const timer9_mux_p[] __initconst =3D { "osc32k", "timer= clk89", }; -static const char *const uart0_mux_p[] __initconst =3D { "osc26m", "pclk",= }; -static const char *const uart1_mux_p[] __initconst =3D { "osc26m", "pclk",= }; -static const char *const uart2_mux_p[] __initconst =3D { "osc26m", "pclk",= }; -static const char *const uart3_mux_p[] __initconst =3D { "osc26m", "pclk",= }; -static const char *const uart4_mux_p[] __initconst =3D { "osc26m", "pclk",= }; -static const char *const spi0_mux_p[] __initconst =3D { "osc26m", "rclk_cf= gaxi", }; -static const char *const spi1_mux_p[] __initconst =3D { "osc26m", "rclk_cf= gaxi", }; -static const char *const spi2_mux_p[] __initconst =3D { "osc26m", "rclk_cf= gaxi", }; +static const char *const timer0_mux_p[] =3D { "osc32k", "timerclk01", }; +static const char *const timer1_mux_p[] =3D { "osc32k", "timerclk01", }; +static const char *const timer2_mux_p[] =3D { "osc32k", "timerclk23", }; +static const char *const timer3_mux_p[] =3D { "osc32k", "timerclk23", }; +static const char *const timer4_mux_p[] =3D { "osc32k", "timerclk45", }; +static const char *const timer5_mux_p[] =3D { "osc32k", "timerclk45", }; +static const char *const timer6_mux_p[] =3D { "osc32k", "timerclk67", }; +static const char *const timer7_mux_p[] =3D { "osc32k", "timerclk67", }; +static const char *const timer8_mux_p[] =3D { "osc32k", "timerclk89", }; +static const char *const timer9_mux_p[] =3D { "osc32k", "timerclk89", }; +static const char *const uart0_mux_p[] =3D { "osc26m", "pclk", }; +static const char *const uart1_mux_p[] =3D { "osc26m", "pclk", }; +static const char *const uart2_mux_p[] =3D { "osc26m", "pclk", }; +static const char *const uart3_mux_p[] =3D { "osc26m", "pclk", }; +static const char *const uart4_mux_p[] =3D { "osc26m", "pclk", }; +static const char *const spi0_mux_p[] =3D { "osc26m", "rclk_cfgaxi", }; +static const char *const spi1_mux_p[] =3D { "osc26m", "rclk_cfgaxi", }; +static const char *const spi2_mux_p[] =3D { "osc26m", "rclk_cfgaxi", }; /* share axi parent */ -static const char *const saxi_mux_p[] __initconst =3D { "armpll3", "armpll= 2", }; -static const char *const pwm0_mux_p[] __initconst =3D { "osc32k", "osc26m"= , }; -static const char *const pwm1_mux_p[] __initconst =3D { "osc32k", "osc26m"= , }; -static const char *const sd_mux_p[] __initconst =3D { "armpll2", "armpll3"= , }; -static const char *const mmc1_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const mmc1_mux2_p[] __initconst =3D { "osc26m", "mmc1_d= iv", }; -static const char *const g2d_mux_p[] __initconst =3D { "armpll2", "armpll3= ", }; -static const char *const venc_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const vdec_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const vpp_mux_p[] __initconst =3D { "armpll2", "armpll3= ", }; -static const char *const edc0_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const ldi0_mux_p[] __initconst =3D { "armpll2", "armpll= 4", +static const char *const saxi_mux_p[] =3D { "armpll3", "armpll2", }; +static const char *const pwm0_mux_p[] =3D { "osc32k", "osc26m", }; +static const char *const pwm1_mux_p[] =3D { "osc32k", "osc26m", }; +static const char *const sd_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const mmc1_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const mmc1_mux2_p[] =3D { "osc26m", "mmc1_div", }; +static const char *const g2d_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const venc_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const vdec_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const vpp_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const edc0_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const ldi0_mux_p[] =3D { "armpll2", "armpll4", "armpll3", "armpll5", }; -static const char *const edc1_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const ldi1_mux_p[] __initconst =3D { "armpll2", "armpll= 4", +static const char *const edc1_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const ldi1_mux_p[] =3D { "armpll2", "armpll4", "armpll3", "armpll5", }; -static const char *const rclk_hsic_p[] __initconst =3D { "armpll3", "armpl= l2", }; -static const char *const mmc2_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const mmc3_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; +static const char *const rclk_hsic_p[] =3D { "armpll3", "armpll2", }; +static const char *const mmc2_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const mmc3_mux_p[] =3D { "armpll2", "armpll3", }; =20 =20 /* fixed rate clocks */ -static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = =3D { +static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] =3D { { HI3620_OSC32K, "osc32k", NULL, 0, 32768, }, { HI3620_OSC26M, "osc26m", NULL, 0, 26000000, }, { HI3620_PCLK, "pclk", NULL, 0, 26000000, }, @@ -76,13 +77,13 @@ static struct hisi_fixed_rate_clock hi3620_fixed_rate_c= lks[] __initdata =3D { }; =20 /* fixed factor clocks */ -static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] __initdat= a =3D { +static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] =3D { { HI3620_RCLK_TCXO, "rclk_tcxo", "osc26m", 1, 4, 0, }, { HI3620_RCLK_CFGAXI, "rclk_cfgaxi", "armpll2", 1, 30, 0, }, { HI3620_RCLK_PICO, "rclk_pico", "hsic_div", 1, 40, 0, }, }; =20 -static struct hisi_mux_clock hi3620_mux_clks[] __initdata =3D { +static struct hisi_mux_clock hi3620_mux_clks[] =3D { { HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p)= , CLK_SET_RATE_PARENT, 0, 15, 2, 0, }, { HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p)= , CLK_SET_RATE_PARENT, 0, 17, 2, 0, }, { HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p)= , CLK_SET_RATE_PARENT, 0, 19, 2, 0, }, @@ -120,7 +121,7 @@ static struct hisi_mux_clock hi3620_mux_clks[] __initda= ta =3D { { HI3620_MMC3_MUX, "mmc3_mux", mmc3_mux_p, ARRAY_SIZE(mmc3_mux_p), = CLK_SET_RATE_PARENT, 0x140, 9, 1, CLK_MUX_HIWORD_MASK, }, }; =20 -static struct hisi_divider_clock hi3620_div_clks[] __initdata =3D { +static struct hisi_divider_clock hi3620_div_clks[] =3D { { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIV= IDER_HIWORD_MASK, NULL, }, { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIV= IDER_HIWORD_MASK, NULL, }, { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVI= DER_HIWORD_MASK, NULL, }, @@ -130,7 +131,7 @@ static struct hisi_divider_clock hi3620_div_clks[] __in= itdata =3D { { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIV= IDER_HIWORD_MASK, NULL, }, }; =20 -static struct hisi_gate_clock hi3620_separated_gate_clks[] __initdata =3D { +static struct hisi_gate_clock hi3620_separated_gate_clks[] =3D { { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", CLK_SET_RATE_PAREN= T, 0x20, 0, 0, }, { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", CLK_SET_RATE_PAREN= T, 0x20, 1, 0, }, { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PAREN= T, 0x20, 2, 0, }, @@ -192,29 +193,19 @@ static struct hisi_gate_clock hi3620_separated_gate_c= lks[] __initdata =3D { { HI3620_MCU_CLK, "mcu_clk", "acp_clk", CLK_SET_RATE_PAREN= T, 0x50, 24, 0, }, }; =20 -static void __init hi3620_clk_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data =3D hisi_clk_init(np, HI3620_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks, - ARRAY_SIZE(hi3620_fixed_rate_clks), - clk_data); - hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks, - ARRAY_SIZE(hi3620_fixed_factor_clks), - clk_data); - hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks), - clk_data); - hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks), - clk_data); - hisi_clk_register_gate_sep(hi3620_separated_gate_clks, - ARRAY_SIZE(hi3620_separated_gate_clks), - clk_data); -} -CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init); +static const struct hisi_clocks hi3620_clks =3D { + .nr =3D HI3620_NR_CLKS, + .fixed_rate_clks =3D hi3620_fixed_rate_clks, + .fixed_rate_clks_num =3D ARRAY_SIZE(hi3620_fixed_rate_clks), + .fixed_factor_clks =3D hi3620_fixed_factor_clks, + .fixed_factor_clks_num =3D ARRAY_SIZE(hi3620_fixed_factor_clks), + .mux_clks =3D hi3620_mux_clks, + .mux_clks_num =3D ARRAY_SIZE(hi3620_mux_clks), + .divider_clks =3D hi3620_div_clks, + .divider_clks_num =3D ARRAY_SIZE(hi3620_div_clks), + .gate_sep_clks =3D hi3620_separated_gate_clks, + .gate_sep_clks_num =3D ARRAY_SIZE(hi3620_separated_gate_clks), +}; =20 struct hisi_mmc_clock { unsigned int id; @@ -252,7 +243,7 @@ struct clk_mmc { =20 #define to_mmc(_hw) container_of(_hw, struct clk_mmc, hw) =20 -static struct hisi_mmc_clock hi3620_mmc_clks[] __initdata =3D { +static struct hisi_mmc_clock hi3620_mmc_clks[] =3D { { HI3620_SD_CIUCLK, "sd_bclk1", "sd_clk", CLK_SET_RATE_PARENT, 0x1f8, 0, = 0x1f8, 1, 3, 0x1f8, 4, 4, 0x1f8, 8, 4}, { HI3620_MMC_CIUCLK1, "mmc_bclk1", "mmc_clk1", CLK_SET_RATE_PARENT, 0x1= f8, 12, 0x1f8, 13, 3, 0x1f8, 16, 4, 0x1f8, 20, 4}, { HI3620_MMC_CIUCLK2, "mmc_bclk2", "mmc_clk2", CLK_SET_RATE_PARENT, 0x1= f8, 24, 0x1f8, 25, 3, 0x1f8, 28, 4, 0x1fc, 0, 4}, @@ -408,8 +399,9 @@ static const struct clk_ops clk_mmc_ops =3D { .recalc_rate =3D mmc_clk_recalc_rate, }; =20 -static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, - void __iomem *base, struct device_node *np) +static struct clk * +clk_register_hisi_mmc(struct device *dev, const struct hisi_mmc_clock *mmc= _clk, + void __iomem *base) { struct clk_mmc *mclk; struct clk *clk; @@ -445,39 +437,50 @@ static struct clk *hisi_register_clk_mmc(struct hisi_= mmc_clock *mmc_clk, return clk; } =20 -static void __init hi3620_mmc_clk_init(struct device_node *node) +static int hisi_register_clk_mmc(struct device *dev, const void *clocks, + size_t num, struct hisi_clock_data *data) { - void __iomem *base; - int i, num =3D ARRAY_SIZE(hi3620_mmc_clks); - struct clk_onecell_data *clk_data; + const struct hisi_mmc_clock *clks =3D clocks; =20 - if (!node) { - pr_err("failed to find pctrl node in DTS\n"); - return; - } + for (int i =3D 0; i < num; i++) { + struct clk *clk =3D clk_register_hisi_mmc(dev, &clks[i], data->base); =20 - base =3D of_iomap(node, 0); - if (!base) { - pr_err("failed to map pctrl\n"); - return; + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + return PTR_ERR(clk); + } + data->clk_data.clks[clks[i].id] =3D clk; } =20 - clk_data =3D kzalloc(sizeof(*clk_data), GFP_KERNEL); - if (WARN_ON(!clk_data)) - return; + return 0; +} =20 - clk_data->clks =3D kcalloc(num, sizeof(*clk_data->clks), GFP_KERNEL); - if (!clk_data->clks) - return; +static const struct hisi_clocks hi3620_clks_mmc =3D { + .customized_clks =3D hi3620_mmc_clks, + .customized_clks_num =3D ARRAY_SIZE(hi3620_mmc_clks), + .clk_register_customized =3D hisi_register_clk_mmc, +}; =20 - for (i =3D 0; i < num; i++) { - struct hisi_mmc_clock *mmc_clk =3D &hi3620_mmc_clks[i]; - clk_data->clks[mmc_clk->id] =3D - hisi_register_clk_mmc(mmc_clk, base, node); - } +static const struct of_device_id hi3620_clk_match_table[] =3D { + { .compatible =3D "hisilicon,hi3620-clock", + .data =3D &hi3620_clks }, + { .compatible =3D "hisilicon,hi3620-mmc-clock", + .data =3D &hi3620_clks_mmc }, + { } +}; +MODULE_DEVICE_TABLE(of, hi3620_clk_match_table); + +static struct platform_driver hi3620_clk_driver =3D { + .probe =3D hisi_clk_probe, + .remove =3D hisi_clk_remove, + .driver =3D { + .name =3D "hi3620-clock", + .of_match_table =3D hi3620_clk_match_table, + }, +}; =20 - clk_data->clk_num =3D num; - of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); -} +module_platform_driver(hi3620_clk_driver); =20 -CLK_OF_DECLARE(hi3620_mmc_clk, "hisilicon,hi3620-mmc-clock", hi3620_mmc_cl= k_init); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("HiSilicon Hi3620 Clock Driver"); --=20 2.39.2