From nobody Tue Sep 9 17:37:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D26ABC77B6C for ; Fri, 7 Apr 2023 23:11:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229954AbjDGXLg (ORCPT ); Fri, 7 Apr 2023 19:11:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229753AbjDGXLZ (ORCPT ); Fri, 7 Apr 2023 19:11:25 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D116E074 for ; Fri, 7 Apr 2023 16:11:23 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id r7-20020a17090b050700b002404be7920aso42686037pjz.5 for ; Fri, 07 Apr 2023 16:11:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1680909083; x=1683501083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kDOPItMBcGDGaCyHwWBFXtRG6cRjR6r59AeA2F6gyE8=; b=2Ks4nw+MRX/xp8YSNC3vpM/HBh/Y6nlfkySNQnCASuSKBGME8sLEdkjroFi0vQgplk 0CRBSKjMH/xFGPxRrx3x1TIH4WXe4aY9dGLXMOwc/5JdJ0WKxNb6UDpZmvLXp2WmjQJw pCoPBgCl/UHZznbKT1SbvPvF94QMbpqDutjwB5ES5U3rfaKooCC1lI492jT3TVYQtOPs +Uj2CQGNttb44t+cWGGvH1T6L+Gw0Y89ghV0LM2H2H/bbKMb8THIGvBHyR6fMnOAgLxj hBargAVuyOyrg41tKR7ltfPGKTpVcKYGemDm6erfCqNfnXCuftd2cgLvbQmTGwmJXnLx tkNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680909083; x=1683501083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kDOPItMBcGDGaCyHwWBFXtRG6cRjR6r59AeA2F6gyE8=; b=M06ogw+aHJJTPCmMpnVEESWrpOqvf73qI0YDwyV4eqFeor3qEMj6oDwEdLHMu6WebD LiP3DrqcsKjHG7FeC59hOSje8gWZAn23Prf/aKqx6m5QfYdltS2iBMVnoUqRq/x6rxI5 2mmFkYZNNyRZru6pD6ZGf1M797RhBj53gijvdf9uJOfJ7W4y4kSkMgtTuc3C6IZHazRw G6NvJJJ/EU1ni1QVnDD/zwhTTH35bLzDvfLBIXXtwspm3nr3LtKAQcEtjkyMkET/vA5r w/tObmSkAqgH+PXwbr+9GDwKcQYb0ZDgRkxYpBF+ihpo/kMeh4rypFJkaQ3AZFpyfq5o MYWQ== X-Gm-Message-State: AAQBX9eesAN4v7AXP8HEHYKzYzwkECvZdHamdTmdO8aY6/v8pmbqSdXt MdNDwCEvBKnJaxl6k/Krbc/ZiQ== X-Google-Smtp-Source: AKy350baMH2Uf4j5jY2xKKPbUiOb+o5CU818Fvc5qPHDFQj1Gw3vvDZIk+bPqRnQ+p/7T+JqQRm0Kg== X-Received: by 2002:a17:903:2452:b0:19e:748c:ee29 with SMTP id l18-20020a170903245200b0019e748cee29mr4773667pls.55.1680909082768; Fri, 07 Apr 2023 16:11:22 -0700 (PDT) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id r5-20020a170902be0500b001a076568da9sm3361526pls.216.2023.04.07.16.11.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 16:11:22 -0700 (PDT) From: Evan Green To: Palmer Dabbelt Cc: slewis@rivosinc.com, heiko@sntech.de, Conor Dooley , vineetg@rivosinc.com, Evan Green , Conor Dooley , Heiko Stuebner , Albert Ou , Andrew Bresticker , Celeste Liu , Guo Ren , Jonathan Corbet , Palmer Dabbelt , Paul Walmsley , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v6 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Date: Fri, 7 Apr 2023 16:11:00 -0700 Message-Id: <20230407231103.2622178-4-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230407231103.2622178-1-evan@rivosinc.com> References: <20230407231103.2622178-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We have an implicit set of base behaviors that userspace depends on, which are mostly defined in various ISA specifications. Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Reviewed-by: Paul Walmsley --- (no changes since v5) Changes in v5: - Fixed misuse of ISA_EXT_c as bitmap, changed to use riscv_isa_extension_available() (Heiko, Conor) Changes in v4: - More newlines in BASE_BEHAVIOR_IMA documentation (Conor) Changes in v3: - Refactored base ISA behavior probe to allow kernel probing as well, in prep for vDSO data initialization. - Fixed doc warnings in IMA text list, use :c:macro:. Documentation/riscv/hwprobe.rst | 24 ++++++++++++++++++++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++ arch/riscv/kernel/sys_riscv.c | 20 ++++++++++++++++++++ 4 files changed, 50 insertions(+), 1 deletion(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 211828f706e3..945d44683c40 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -39,3 +39,27 @@ The following keys are defined: =20 * :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contains the value of ``mimplid``,= as defined by the RISC-V privileged architecture specification. + +* :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base + user-visible behavior that this kernel supports. The following base use= r ABIs + are defined: + + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or + rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of= the + privileged ISA, with the following known exceptions (more exceptions m= ay be + added, but only if it can be demonstrated that the user ABI is not bro= ken): + + * The :fence.i: instruction cannot be directly executed by userspace + programs (it may still be executed in userspace via a + kernel-controlled mechanism such as the vDSO). + +* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensi= ons + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: + base system behavior. + + * :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported,= as + defined by commit cd20cee ("FMIN/FMAX now implement + minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA man= ual. + + * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defin= ed + by version 2.2 of the RISC-V ISA manual. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index 6184bbc77256..d717c80a64ff 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ =20 #include =20 -#define RISCV_HWPROBE_MAX_KEY 2 +#define RISCV_HWPROBE_MAX_KEY 4 =20 #endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index b79be00920db..398e08f7e083 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -20,6 +20,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_MVENDORID 0 #define RISCV_HWPROBE_KEY_MARCHID 1 #define RISCV_HWPROBE_KEY_MIMPID 2 +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index fe8e833ecb2e..5ca567cef142 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -125,6 +126,25 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pai= r, case RISCV_HWPROBE_KEY_MIMPID: hwprobe_arch_id(pair, cpus); break; + /* + * The kernel already assumes that the base single-letter ISA + * extensions are supported on all harts, and only supports the + * IMA base, so just cheat a bit here and tell that to + * userspace. + */ + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: + pair->value =3D RISCV_HWPROBE_BASE_BEHAVIOR_IMA; + break; + + case RISCV_HWPROBE_KEY_IMA_EXT_0: + pair->value =3D 0; + if (has_fpu()) + pair->value |=3D RISCV_HWPROBE_IMA_FD; + + if (riscv_isa_extension_available(NULL, c)) + pair->value |=3D RISCV_HWPROBE_IMA_C; + + break; =20 /* * For forward compatibility, unknown keys don't fail the whole --=20 2.25.1