From nobody Tue Feb 10 10:54:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 262B7C77B6C for ; Fri, 7 Apr 2023 16:12:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240330AbjDGQMH (ORCPT ); Fri, 7 Apr 2023 12:12:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232540AbjDGQLz (ORCPT ); Fri, 7 Apr 2023 12:11:55 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0239C976D; Fri, 7 Apr 2023 09:11:34 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-211-012.ewe-ip-backbone.de [91.248.211.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2B99966031D7; Fri, 7 Apr 2023 17:11:33 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1680883893; bh=u8kWf7vzNCV/OrSNcuFbv1nesBsKtW9YCzvBUbnkYFI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cB+8up4x1QL4STsGbp0QBfzsGjYCMKPq6PbnMw52Inc3KOxcpLslkSHOw5rcPRKhL H7MZ+TzR30NCJgeIt07+eFbTP72dO34kX418zFqCb0m2Xf8lwO43YDru4Im9Up96U+ Gb5fy4RdHTEQ2GbDbigkL+wgItwKg9/OZSh5SIQ8o7tiw91TVbFFs9dzCL9LyN0uqH AzFonBCMFCjl6k3FnrZECESdcvmMTuJIcPxF3fDfDVtaVAXjBYUkvNp6we2X9WPgFT Oqqi6mhTXFVcsMxj2VUQS/8aXTxBq+c28O3E2kXe7xA9BaXyzdZ/jbDCUMDFm3cJDz 17/0U+x4roplQ== Received: by jupiter.universe (Postfix, from userid 1000) id F303B4807E2; Fri, 7 Apr 2023 18:11:30 +0200 (CEST) From: Sebastian Reichel To: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com, Andrew Lunn Subject: [PATCHv3 1/2] net: ethernet: stmmac: dwmac-rk: rework optional clock handling Date: Fri, 7 Apr 2023 18:11:28 +0200 Message-Id: <20230407161129.70601-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230407161129.70601-1-sebastian.reichel@collabora.com> References: <20230407161129.70601-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The clock requesting code is quite repetitive. Fix this by requesting the clocks via devm_clk_bulk_get_optional. The optional variant has been used, since this is effectively what the old code did. The exact clocks required depend on the platform and configuration. As a side effect this change adds correct -EPROBE_DEFER handling. Suggested-by: Jakub Kicinski Suggested-by: Andrew Lunn Fixes: 7ad269ea1a2b ("GMAC: add driver for Rockchip RK3288 SoCs integrated = GMAC") Signed-off-by: Sebastian Reichel --- .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 183 +++++++----------- 1 file changed, 70 insertions(+), 113 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/e= thernet/stmicro/stmmac/dwmac-rk.c index 4b8fd11563e4..7ac9ca9b4935 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -39,6 +39,24 @@ struct rk_gmac_ops { u32 regs[]; }; =20 +static const char * const rk_clocks[] =3D { + "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed", +}; + +static const char * const rk_rmii_clocks[] =3D { + "mac_clk_rx", "clk_mac_ref", "clk_mac_refout", +}; + +enum rk_clocks_index { + RK_ACLK_MAC =3D 0, + RK_PCLK_MAC, + RK_MAC_CLK_TX, + RK_CLK_MAC_SPEED, + RK_MAC_CLK_RX, + RK_CLK_MAC_REF, + RK_CLK_MAC_REFOUT, +}; + struct rk_priv_data { struct platform_device *pdev; phy_interface_t phy_iface; @@ -51,15 +69,9 @@ struct rk_priv_data { bool clock_input; bool integrated_phy; =20 + struct clk_bulk_data *clks; + int num_clks; struct clk *clk_mac; - struct clk *gmac_clkin; - struct clk *mac_clk_rx; - struct clk *mac_clk_tx; - struct clk *clk_mac_ref; - struct clk *clk_mac_refout; - struct clk *clk_mac_speed; - struct clk *aclk_mac; - struct clk *pclk_mac; struct clk *clk_phy; =20 struct reset_control *phy_reset; @@ -104,10 +116,11 @@ static void px30_set_to_rmii(struct rk_priv_data *bsp= _priv) =20 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { + struct clk *clk_mac_speed =3D bsp_priv->clks[RK_CLK_MAC_SPEED].clk; struct device *dev =3D &bsp_priv->pdev->dev; int ret; =20 - if (IS_ERR(bsp_priv->clk_mac_speed)) { + if (!clk_mac_speed) { dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); return; } @@ -116,7 +129,7 @@ static void px30_set_rmii_speed(struct rk_priv_data *bs= p_priv, int speed) regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, PX30_GMAC_SPEED_10M); =20 - ret =3D clk_set_rate(bsp_priv->clk_mac_speed, 2500000); + ret =3D clk_set_rate(clk_mac_speed, 2500000); if (ret) dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n", __func__, ret); @@ -124,7 +137,7 @@ static void px30_set_rmii_speed(struct rk_priv_data *bs= p_priv, int speed) regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, PX30_GMAC_SPEED_100M); =20 - ret =3D clk_set_rate(bsp_priv->clk_mac_speed, 25000000); + ret =3D clk_set_rate(clk_mac_speed, 25000000); if (ret) dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n", __func__, ret); @@ -1066,6 +1079,7 @@ static void rk3568_set_to_rmii(struct rk_priv_data *b= sp_priv) =20 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) { + struct clk *clk_mac_speed =3D bsp_priv->clks[RK_CLK_MAC_SPEED].clk; struct device *dev =3D &bsp_priv->pdev->dev; unsigned long rate; int ret; @@ -1085,7 +1099,7 @@ static void rk3568_set_gmac_speed(struct rk_priv_data= *bsp_priv, int speed) return; } =20 - ret =3D clk_set_rate(bsp_priv->clk_mac_speed, rate); + ret =3D clk_set_rate(clk_mac_speed, rate); if (ret) dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", __func__, rate, ret); @@ -1371,6 +1385,7 @@ static void rv1126_set_to_rmii(struct rk_priv_data *b= sp_priv) =20 static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int spee= d) { + struct clk *clk_mac_speed =3D bsp_priv->clks[RK_CLK_MAC_SPEED].clk; struct device *dev =3D &bsp_priv->pdev->dev; unsigned long rate; int ret; @@ -1390,7 +1405,7 @@ static void rv1126_set_rgmii_speed(struct rk_priv_dat= a *bsp_priv, int speed) return; } =20 - ret =3D clk_set_rate(bsp_priv->clk_mac_speed, rate); + ret =3D clk_set_rate(clk_mac_speed, rate); if (ret) dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", __func__, rate, ret); @@ -1398,6 +1413,7 @@ static void rv1126_set_rgmii_speed(struct rk_priv_dat= a *bsp_priv, int speed) =20 static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { + struct clk *clk_mac_speed =3D bsp_priv->clks[RK_CLK_MAC_SPEED].clk; struct device *dev =3D &bsp_priv->pdev->dev; unsigned long rate; int ret; @@ -1414,7 +1430,7 @@ static void rv1126_set_rmii_speed(struct rk_priv_data= *bsp_priv, int speed) return; } =20 - ret =3D clk_set_rate(bsp_priv->clk_mac_speed, rate); + ret =3D clk_set_rate(clk_mac_speed, rate); if (ret) dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n", __func__, rate, ret); @@ -1475,68 +1491,50 @@ static int rk_gmac_clk_init(struct plat_stmmacenet_= data *plat) { struct rk_priv_data *bsp_priv =3D plat->bsp_priv; struct device *dev =3D &bsp_priv->pdev->dev; - int ret; + int phy_iface =3D bsp_priv->phy_iface; + int i, j, ret; =20 bsp_priv->clk_enabled =3D false; =20 - bsp_priv->mac_clk_rx =3D devm_clk_get(dev, "mac_clk_rx"); - if (IS_ERR(bsp_priv->mac_clk_rx)) - dev_err(dev, "cannot get clock %s\n", - "mac_clk_rx"); - - bsp_priv->mac_clk_tx =3D devm_clk_get(dev, "mac_clk_tx"); - if (IS_ERR(bsp_priv->mac_clk_tx)) - dev_err(dev, "cannot get clock %s\n", - "mac_clk_tx"); + bsp_priv->num_clks =3D ARRAY_SIZE(rk_clocks); + if (phy_iface =3D=3D PHY_INTERFACE_MODE_RMII) + bsp_priv->num_clks +=3D ARRAY_SIZE(rk_rmii_clocks); =20 - bsp_priv->aclk_mac =3D devm_clk_get(dev, "aclk_mac"); - if (IS_ERR(bsp_priv->aclk_mac)) - dev_err(dev, "cannot get clock %s\n", - "aclk_mac"); + bsp_priv->clks =3D devm_kcalloc(dev, bsp_priv->num_clks, + sizeof(*bsp_priv->clks), GFP_KERNEL); + if (!bsp_priv->clks) + return -ENOMEM; =20 - bsp_priv->pclk_mac =3D devm_clk_get(dev, "pclk_mac"); - if (IS_ERR(bsp_priv->pclk_mac)) - dev_err(dev, "cannot get clock %s\n", - "pclk_mac"); + for (i =3D 0; i < ARRAY_SIZE(rk_clocks); i++) + bsp_priv->clks[i].id =3D rk_clocks[i]; =20 - bsp_priv->clk_mac =3D devm_clk_get(dev, "stmmaceth"); - if (IS_ERR(bsp_priv->clk_mac)) - dev_err(dev, "cannot get clock %s\n", - "stmmaceth"); - - if (bsp_priv->phy_iface =3D=3D PHY_INTERFACE_MODE_RMII) { - bsp_priv->clk_mac_ref =3D devm_clk_get(dev, "clk_mac_ref"); - if (IS_ERR(bsp_priv->clk_mac_ref)) - dev_err(dev, "cannot get clock %s\n", - "clk_mac_ref"); - - if (!bsp_priv->clock_input) { - bsp_priv->clk_mac_refout =3D - devm_clk_get(dev, "clk_mac_refout"); - if (IS_ERR(bsp_priv->clk_mac_refout)) - dev_err(dev, "cannot get clock %s\n", - "clk_mac_refout"); - } + if (phy_iface =3D=3D PHY_INTERFACE_MODE_RMII) { + for (j =3D 0; j < ARRAY_SIZE(rk_rmii_clocks); j++) + bsp_priv->clks[i++].id =3D rk_rmii_clocks[j]; } =20 - bsp_priv->clk_mac_speed =3D devm_clk_get(dev, "clk_mac_speed"); - if (IS_ERR(bsp_priv->clk_mac_speed)) - dev_err(dev, "cannot get clock %s\n", "clk_mac_speed"); + ret =3D devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, + bsp_priv->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get clocks\n"); + + /* "stmmaceth" will be enabled by the core */ + bsp_priv->clk_mac =3D devm_clk_get(dev, "stmmaceth"); + ret =3D PTR_ERR_OR_ZERO(bsp_priv->clk_mac); + if (ret) + return dev_err_probe(dev, ret, "Cannot get stmmaceth clock\n"); =20 if (bsp_priv->clock_input) { dev_info(dev, "clock input from PHY\n"); - } else { - if (bsp_priv->phy_iface =3D=3D PHY_INTERFACE_MODE_RMII) - clk_set_rate(bsp_priv->clk_mac, 50000000); + } else if (phy_iface =3D=3D PHY_INTERFACE_MODE_RMII) { + clk_set_rate(bsp_priv->clk_mac, 50000000); } =20 if (plat->phy_node && bsp_priv->integrated_phy) { bsp_priv->clk_phy =3D of_clk_get(plat->phy_node, 0); - if (IS_ERR(bsp_priv->clk_phy)) { - ret =3D PTR_ERR(bsp_priv->clk_phy); - dev_err(dev, "Cannot get PHY clock: %d\n", ret); - return -EINVAL; - } + ret =3D PTR_ERR_OR_ZERO(bsp_priv->clk_phy); + if (ret) + return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); clk_set_rate(bsp_priv->clk_phy, 50000000); } =20 @@ -1545,77 +1543,36 @@ static int rk_gmac_clk_init(struct plat_stmmacenet_= data *plat) =20 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) { - int phy_iface =3D bsp_priv->phy_iface; + int ret; =20 if (enable) { if (!bsp_priv->clk_enabled) { - if (phy_iface =3D=3D PHY_INTERFACE_MODE_RMII) { - if (!IS_ERR(bsp_priv->mac_clk_rx)) - clk_prepare_enable( - bsp_priv->mac_clk_rx); - - if (!IS_ERR(bsp_priv->clk_mac_ref)) - clk_prepare_enable( - bsp_priv->clk_mac_ref); - - if (!IS_ERR(bsp_priv->clk_mac_refout)) - clk_prepare_enable( - bsp_priv->clk_mac_refout); - } - - if (!IS_ERR(bsp_priv->clk_phy)) - clk_prepare_enable(bsp_priv->clk_phy); - - if (!IS_ERR(bsp_priv->aclk_mac)) - clk_prepare_enable(bsp_priv->aclk_mac); - - if (!IS_ERR(bsp_priv->pclk_mac)) - clk_prepare_enable(bsp_priv->pclk_mac); - - if (!IS_ERR(bsp_priv->mac_clk_tx)) - clk_prepare_enable(bsp_priv->mac_clk_tx); + ret =3D clk_bulk_prepare_enable(bsp_priv->num_clks, + bsp_priv->clks); + if (ret) + return ret; =20 - if (!IS_ERR(bsp_priv->clk_mac_speed)) - clk_prepare_enable(bsp_priv->clk_mac_speed); + ret =3D clk_prepare_enable(bsp_priv->clk_phy); + if (ret) + return ret; =20 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input, true); =20 - /** - * if (!IS_ERR(bsp_priv->clk_mac)) - * clk_prepare_enable(bsp_priv->clk_mac); - */ mdelay(5); bsp_priv->clk_enabled =3D true; } } else { if (bsp_priv->clk_enabled) { - if (phy_iface =3D=3D PHY_INTERFACE_MODE_RMII) { - clk_disable_unprepare(bsp_priv->mac_clk_rx); - - clk_disable_unprepare(bsp_priv->clk_mac_ref); - - clk_disable_unprepare(bsp_priv->clk_mac_refout); - } - + clk_bulk_disable_unprepare(bsp_priv->num_clks, + bsp_priv->clks); clk_disable_unprepare(bsp_priv->clk_phy); =20 - clk_disable_unprepare(bsp_priv->aclk_mac); - - clk_disable_unprepare(bsp_priv->pclk_mac); - - clk_disable_unprepare(bsp_priv->mac_clk_tx); - - clk_disable_unprepare(bsp_priv->clk_mac_speed); - if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input, false); - /** - * if (!IS_ERR(bsp_priv->clk_mac)) - * clk_disable_unprepare(bsp_priv->clk_mac); - */ + bsp_priv->clk_enabled =3D false; } } --=20 2.39.2