From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00BEBC76188 for ; Wed, 5 Apr 2023 20:39:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231393AbjDEUjR (ORCPT ); Wed, 5 Apr 2023 16:39:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231880AbjDEUjJ (ORCPT ); Wed, 5 Apr 2023 16:39:09 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08B0F1B3; Wed, 5 Apr 2023 13:39:08 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id m8so10678653wmq.5; Wed, 05 Apr 2023 13:39:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680727146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Cmc6uDj21KTxpfnQHdrxi7S8XMD1Ra3TJ9amtU9lpl8=; b=eyap6kJYmYkGorPxkfa1WonO/ucZQdyDc1JnlN/4h0NLtEQAAwn+W7hinXTqw7J77l AMMyBK9dqH8DSbRQU1IIPyGrxrSTd/We3KrJNwAMyzY5ZKhsM6k8AxmIqmpZURI6bibu 9hTgmHbxypIO2z3zRM+vfYEHJ+5rzuwbsOApE7pHl4ug9uCjMs6xilXhjTAw2ljPGPyr rY6ff2bpjUDVMT0qORI1UvD4+J5MXDuG2qW+TiF+WulbeXlgShbsLREYId4M7bEIlMko Xo78Skl/pU/h1AJ0TT1A0//GtMLiXpmpGRC+SLHao32uG+1qRikh0QnJTd5nWAiCLWqd 829g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680727146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cmc6uDj21KTxpfnQHdrxi7S8XMD1Ra3TJ9amtU9lpl8=; b=2xOXYjUG/07qD+WGkSKzhHCZodCB1UQLjSwjQe2OnnZF/LIf7bVTSqwe5PR89QHrhw opK93jFlZ0B17sbQ89IGGZ6K5WgblWyXvQRbX96xXFN29Xysm/i9rKwgNlsmBWB5HMQu +HPrOYBG5Sk2aJxy++CW1xezGIxo3NqSVy6ds4Q/KjLbgQti0Uvp/eqtA5IDZ8y9dRMB /PLztprIB2hGHiXJNaZ2JG+efIWujjJEOJOhMc0kpldMBpP11M0wWZvPCwA+6xeqGYV/ 1QKgojzpOyjaz99YVqLht5f76EEShDDMWkJKo+efO/6pY3444MPQIoHembVd1eeVbNLk A+cw== X-Gm-Message-State: AAQBX9c9EEl2Xf9b6OofoWmLfmsFrG7xKnPPQFbTCRZlkC3K7LrZlAyg YATcxgUZRcUsQwILmPGeB+Y= X-Google-Smtp-Source: AKy350a7EIGlBmOTKQnba5+3KX1Ovlm/9yd4X/S8HX4MOqgi9WGExqkdovm1ykfygXIYV5nfYFQKMg== X-Received: by 2002:a1c:7714:0:b0:3ef:67fc:fef1 with SMTP id t20-20020a1c7714000000b003ef67fcfef1mr5933520wmi.26.1680727146266; Wed, 05 Apr 2023 13:39:06 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c469300b003eda46d6792sm3259867wmo.32.2023.04.05.13.39.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 13:39:05 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 01/12] net: dsa: mt7530: fix comments regarding port 5 and 6 for both switches Date: Wed, 5 Apr 2023 23:38:48 +0300 Message-Id: <20230405203859.391267-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There's no logic to numerically order the CPU ports. State the port number and its being a CPU port instead. Remove the irrelevant PHY muxing information from mt7530_mac_port_get_caps(). Explain the supported MII modes instead. Remove the out of place PHY muxing information from mt753x_phylink_mac_config(). The function is for both the MT7530 and MT7531 switches but there's no phy muxing on MT7531. These comments were gradually introduced with the commits below. ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API") 38f790a80560 ("net: dsa: mt7530: Add support for port 5") 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware") c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index e4bb5037d352..31ef70f0cd12 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2506,7 +2506,7 @@ static void mt7530_mac_port_get_caps(struct dsa_switc= h *ds, int port, config->supported_interfaces); break; =20 - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5, a CPU port, supports rgmii, mii, and gmii. */ phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); @@ -2514,7 +2514,7 @@ static void mt7530_mac_port_get_caps(struct dsa_switc= h *ds, int port, config->supported_interfaces); break; =20 - case 6: /* 1st cpu port */ + case 6: /* Port 6, a CPU port, supports rgmii and trgmii. */ __set_bit(PHY_INTERFACE_MODE_RGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_TRGMII, @@ -2539,14 +2539,14 @@ static void mt7531_mac_port_get_caps(struct dsa_swi= tch *ds, int port, config->supported_interfaces); break; =20 - case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ + case 5: /* Port 5, a CPU port, supports rgmii and sgmii/802.3z. */ if (mt7531_is_rgmii_port(priv, port)) { phy_interface_set_rgmii(config->supported_interfaces); break; } fallthrough; =20 - case 6: /* 1st cpu port supports sgmii/8023z only */ + case 6: /* Port 6, a CPU port, supports sgmii/802.3z only. */ __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, @@ -2738,7 +2738,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int = port, unsigned int mode, state->interface !=3D PHY_INTERFACE_MODE_INTERNAL) goto unsupported; break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5, a CPU port. */ if (priv->p5_interface =3D=3D state->interface) break; =20 @@ -2748,7 +2748,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int = port, unsigned int mode, if (priv->p5_intf_sel !=3D P5_DISABLED) priv->p5_interface =3D state->interface; break; - case 6: /* 1st cpu port */ + case 6: /* Port 6, a CPU port. */ if (priv->p6_interface =3D=3D state->interface) break; =20 --=20 2.37.2 From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C09ADC7619A for ; Wed, 5 Apr 2023 20:39:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233917AbjDEUjV (ORCPT ); Wed, 5 Apr 2023 16:39:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232004AbjDEUjL (ORCPT ); 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Wed, 05 Apr 2023 13:39:08 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 02/12] net: dsa: mt7530: fix phylink for port 5 and fix port 5 modes Date: Wed, 5 Apr 2023 23:38:49 +0300 Message-Id: <20230405203859.391267-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There're two code paths for setting up port 5: mt7530_setup() -> mt7530_setup_port5() mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() The first code path is supposed to run when PHY muxing is being used. In this case, port 5 is somewhat of a hidden port. It won't be defined on the devicetree so phylink can't be used to manage the port. The second code path used to call mt7530_setup_port5() directly under case 5 on mt7530_phylink_mac_config() before it was moved to mt7530_mac_config() with 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware"). mt7530_setup_port5() will never run through this code path because the current code on mt7530_setup() bypasses phylink for all cases of port 5. Fix this by leaving it to phylink if port 5 is used as a CPU, DSA, or user port. For the cases of PHY muxing or the port being disabled, call mt7530_setup_port5() directly from mt7530_setup() without involving phylink. Move setting the interface and P5_DISABLED mode to a more specific location. They're supposed to be overwritten if PHY muxing is detected. Add comments which explain the process. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 31ef70f0cd12..a00aabe4987e 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2288,16 +2288,19 @@ mt7530_setup(struct dsa_switch *ds) return ret; =20 /* Setup port 5 */ - priv->p5_intf_sel =3D P5_DISABLED; - interface =3D PHY_INTERFACE_MODE_NA; - if (!dsa_is_unused_port(ds, 5)) { + /* Set the interface selection of port 5 to GMAC5 when it's used + * as a CPU, DSA, or user port. Let phylink handle the rest. + */ priv->p5_intf_sel =3D P5_INTF_SEL_GMAC5; - ret =3D of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); - if (ret && ret !=3D -ENODEV) - return ret; } else { - /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ + /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. + * Set priv->p5_intf_sel to P5_DISABLED first, then overwrite it + * if PHY muxing is detected. + */ + priv->p5_intf_sel =3D P5_DISABLED; + interface =3D PHY_INTERFACE_MODE_NA; + for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, "mediatek,eth-mac")) @@ -2328,6 +2331,8 @@ mt7530_setup(struct dsa_switch *ds) of_node_put(phy_node); break; } + + mt7530_setup_port5(ds, interface); } =20 #ifdef CONFIG_GPIOLIB @@ -2338,8 +2343,6 @@ mt7530_setup(struct dsa_switch *ds) } #endif /* CONFIG_GPIOLIB */ =20 - mt7530_setup_port5(ds, interface); - /* Flush the FDB table */ ret =3D mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); if (ret < 0) --=20 2.37.2 From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D048AC76188 for ; Wed, 5 Apr 2023 20:39:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233961AbjDEUj0 (ORCPT ); Wed, 5 Apr 2023 16:39:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232640AbjDEUjP (ORCPT ); Wed, 5 Apr 2023 16:39:15 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAF37768E; Wed, 5 Apr 2023 13:39:12 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id n9-20020a05600c4f8900b003f05f617f3cso3566206wmq.2; Wed, 05 Apr 2023 13:39:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680727151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TL1ifXOj3OEH5mV418CX1uP5QyBqfV3oBYYgm4r26w8=; b=otBFkFBIeXE2wHUW2NbAADjRIHF+Q3/1CyWyDB0KCBi/bP20rCssC6krJAdujcBH0p vOr+fv+PvHyG2Lh3nHOO205ZyWI4KHjzqT7qsF3NzKvNhRR/N13+PZi6I92fRLV+HIkk NOQtYCDb/jQLRvUEn0+kwXuvwtc5KrH8csK6rRMtSiLHNVb4oFDd/W4dfwZz6ySfih6L 69xhweJmDTMYUUbhYyNiVONmz1b65R5rqaglAir2dBEdPXGc8HaACVDW8lbeidNEyFVt wpNX6ng2AIENabtgAzErMui85//Jr2AgfW1+iBZKRLjyqrByjXAijgkmXD+v1/qnf3z0 V/ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680727151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TL1ifXOj3OEH5mV418CX1uP5QyBqfV3oBYYgm4r26w8=; b=qZwif7RQl8EeXpasrThLq/2Ky5pVf5v9u8gxKNPMQH7JXfkt950Wr1QxbSqQRKh7e7 LDkT6I/TtiPg2DenP0XwITS5JZBIad6S1podt8namHajoeFL1JpMU7/Y8Wsbax7qXVDL hr5ZLaGV0osf+dveOnok9l4Rrb/2dZlrRdWdr9K7WMu8rXnK3rV1vUmhTJXiobqzDW3d 52s8/tyXwwMYkVuyU58gluODIynBcCPInICnnFel1G9POzn++xsePa37ateOLUQ7ffVa fx90zjsk4oRyMpv56SgTN/XYCSrt/7SnvIXhp1qX/i5FLbfVSYBc+aCj1oiQY8i13Jat QUIw== X-Gm-Message-State: AAQBX9eh0NVJzhme7TuAJXWmCo5zNkjLiQMMJukGJjJBcqp5tZZjV1gV 8OdVXK3Gvv2g9FHK7GzglQI= X-Google-Smtp-Source: AKy350apw98pqyG0m2kriMDO9nl7uy8+ve6V4vFItG3nJ/BQRJUCnIASNlPnFi/uFduCYKWZ/rXdtA== X-Received: by 2002:a05:600c:198e:b0:3ed:ad05:5841 with SMTP id t14-20020a05600c198e00b003edad055841mr2488273wmq.17.1680727150993; Wed, 05 Apr 2023 13:39:10 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c469300b003eda46d6792sm3259867wmo.32.2023.04.05.13.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 13:39:10 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 03/12] net: dsa: mt7530: do not run mt7530_setup_port5() if port 5 is disabled Date: Wed, 5 Apr 2023 23:38:50 +0300 Message-Id: <20230405203859.391267-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There's no need to run all the code on mt7530_setup_port5() if port 5 is disabled. The only case for calling mt7530_setup_port5() from mt7530_setup() is when PHY muxing is enabled. That is because port 5 is not defined as a port on the devicetree, therefore, it cannot be controlled by phylink. Because of this, run mt7530_setup_port5() if priv->p5_intf_sel is P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4. Remove the P5_DISABLED case from mt7530_setup_port5(). Stop initialising the interface variable as the remaining cases will always call mt7530_setup_port5() with it initialised. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index a00aabe4987e..9ab2e128b564 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -943,9 +943,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ val &=3D ~MHWTRAP_P5_DIS; break; - case P5_DISABLED: - interface =3D PHY_INTERFACE_MODE_NA; - break; default: dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", priv->p5_intf_sel); @@ -2299,7 +2296,6 @@ mt7530_setup(struct dsa_switch *ds) * if PHY muxing is detected. */ priv->p5_intf_sel =3D P5_DISABLED; - interface =3D PHY_INTERFACE_MODE_NA; =20 for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, @@ -2332,7 +2328,9 @@ mt7530_setup(struct dsa_switch *ds) break; } =20 - mt7530_setup_port5(ds, interface); + if (priv->p5_intf_sel =3D=3D P5_INTF_SEL_PHY_P0 || + priv->p5_intf_sel =3D=3D P5_INTF_SEL_PHY_P4) + mt7530_setup_port5(ds, interface); } =20 #ifdef CONFIG_GPIOLIB --=20 2.37.2 From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9167C7619A for ; Wed, 5 Apr 2023 20:39:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233233AbjDEUji (ORCPT ); Wed, 5 Apr 2023 16:39:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233431AbjDEUjQ (ORCPT ); Wed, 5 Apr 2023 16:39:16 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2336559D5; Wed, 5 Apr 2023 13:39:15 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id v20-20020a05600c471400b003ed8826253aso2756968wmo.0; Wed, 05 Apr 2023 13:39:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680727153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E0IMeO1O4SBYZQwg5+XaETPP4flNHm2gc4lWDzFifZI=; b=mi7PrvZmmvLEO+3MKptjpM80IcUEqSCRCtCJIny9XFduJeLpEnTUAXzOk8cEf6CcPO Xl2gw36OSSAUO8EhYEticwUjDS8haigdxksMlOZzUzmyDZmpfs+OekQlqeOAI0oQFWLx MjbQB7cxX2F1nKtmLFZRB3mx4bdKVzCrIYwIfuYP+nciACktK8ciENNRAqydQwwTpgm3 v+4fkqOv0Ge2UXnMvxQjtTmR6vk6bMC6SMiA7Y+cc4cq4UicGEeVkeSs/6V2OFtExoF7 bznc1ooFPRdTUBXsUnsFyTHh429aJmgPbnOAzOVNqejlTO47eqx+Xv1wtl58/CZPFU51 7gxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680727153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E0IMeO1O4SBYZQwg5+XaETPP4flNHm2gc4lWDzFifZI=; b=bLEJliYhTAwtVP08jx7FpdgBCFUtP975TbIyV+6GOQ+3fsLcyjIu3VbkmNRJXXlo26 k7+LntBKd5rqZ9UwgL0elTgszIkBbAZJocH1Ts1N0F2ncZd8Z+XB0AUOUoMl4dDVZkjK tHHpRK+/1szvgD80OYLQOobauJl1mTLgp29SRP1DPMZaSdZo81dRNajbqERAHG/FYgwF jGMdwcDujqobRy5CunDDhuj6ZR/psog/LF1d2696bxP1FFCDzPLiwXuyzV7Hn80GjZrH yiNMx6NetJ4ME6wLD7VDomuUD+/35sNA9IkpPMMfKir+UETJVYqtF1T2mufGMX1ziErJ qgpw== X-Gm-Message-State: AAQBX9dtWMG4IucF3eIImTfdGzD2IzCEgQJUzCYLlap+i2gK2fWoioX8 3mw5s4rl0kPrqh6Rh2qLDXg= X-Google-Smtp-Source: AKy350Z5iIa4fumSDUmJ7ok3oTLcRfGGebEHh0loZFWOHE06MqRBazTetiRRs+kMSZS76dSAraf2RA== X-Received: by 2002:a05:600c:b51:b0:3ed:2a91:3bc9 with SMTP id k17-20020a05600c0b5100b003ed2a913bc9mr5946344wmr.15.1680727153425; Wed, 05 Apr 2023 13:39:13 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c469300b003eda46d6792sm3259867wmo.32.2023.04.05.13.39.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 13:39:13 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 04/12] net: dsa: mt7530: set priv->p5_interface in correct conditions Date: Wed, 5 Apr 2023 23:38:51 +0300 Message-Id: <20230405203859.391267-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Currently, priv->p5_interface is set on mt7530_setup_port5() even though it's being set on mt753x_phylink_mac_config() after mt7530_setup_port5() is run. The only case for setting priv->p5_interface on mt7530_setup_port5() is when PHY muxing is enabled. That is because port 5 is not defined as a port on the devicetree, therefore, it cannot be controlled by phylink. To address this, set priv->p5_interface only if PHY muxing is enabled. On mt753x_phylink_mac_config, !=3D P5_DISABLED is enough but to be explicit, look for p5_intf_sel being P5_INTF_SEL_GMAC5 or P5_INTF_SEL_GMAC5_SGMII. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- If you think priv->p5_interface should not be set when port 5 is used for PHY muxing, let me know. Ar=C4=B1n=C3=A7 --- drivers/net/dsa/mt7530.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 9ab2e128b564..fccd59564532 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -976,7 +976,9 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) dev_dbg(ds->dev, "Setup P5, HWTRAP=3D0x%x, intf_sel=3D%s, phy-mode=3D%s\n= ", val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); =20 - priv->p5_interface =3D interface; + if (priv->p5_intf_sel =3D=3D P5_INTF_SEL_PHY_P0 || + priv->p5_intf_sel =3D=3D P5_INTF_SEL_PHY_P4) + priv->p5_interface =3D interface; =20 unlock_exit: mutex_unlock(&priv->reg_mutex); @@ -2746,7 +2748,8 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int = port, unsigned int mode, if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; =20 - if (priv->p5_intf_sel !=3D P5_DISABLED) + if (priv->p5_intf_sel =3D=3D P5_INTF_SEL_GMAC5 || + priv->p5_intf_sel =3D=3D P5_INTF_SEL_GMAC5_SGMII) priv->p5_interface =3D state->interface; break; case 6: /* Port 6, a CPU port. */ --=20 2.37.2 From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE99BC7619A for ; Wed, 5 Apr 2023 20:39:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234398AbjDEUjm (ORCPT ); Wed, 5 Apr 2023 16:39:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231886AbjDEUjf (ORCPT ); Wed, 5 Apr 2023 16:39:35 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98FA26E8D; Wed, 5 Apr 2023 13:39:17 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id n19so21596919wms.0; Wed, 05 Apr 2023 13:39:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680727156; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jp4sFg0ojMV8MMU8A9Bkb7JvDbiYw4w687Rv39wQaSk=; b=ogrQ00Dp40q8HszYOjDW7BkHkbDsaeh3gTS3X2D8xEh8EyqwhN2zlRUj4CxUSH53gD bWQ7QRsAkRS8V8byFcM4sAvzSvnh1MmD3JPIiSVk5NcSczRX50Hc9yjKx4J25aXqw1dy Ni/W6LBRqD5VaXUjJiwFb4POV7CM1UqLnj/NucR1ltexeiWhjH7zhWo5vON9+Ts+UDHG xZRMXaxHTU5Q9dx4NKypSpTFdU9AsyV561K2f6u/nj2rqvgnyUxO2RhwCpgs5yoGFjcv Fn//gj1hdEvVhTq28x67GvvPz9Ch2OdhakpzXrF25he58FllBXn8PqXws8ZIwVz2U4My IBjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680727156; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jp4sFg0ojMV8MMU8A9Bkb7JvDbiYw4w687Rv39wQaSk=; b=sJ2YpESFRx/hqM3hxxtwRsArxXLw44RyndoEV5nAfA+lOhjKuiNmx5r9zecmffGvnt y2QRAg1MnhD746pAkyWM0RH6IKSfqd12x1OQXZ8o7EVkxGd/y/k2xfgBKtiu7cm9wMg7 PmdShuFZdt+TNps0x8sx5rv59Tw1XMN03bnwdcLPpEgGY5Ua0Q4UqtS7IKcdY7J/vNF8 TDpOdQ75SE9Bnp3tBKJ90Vi15np8nu4CkMB5gtYhuOdJ/7FeVuBvOzt2Ywi7YrN2k/w8 Ka4Ci8x+kEu0nQhlDZoN7rN6hVLMlmHZqCOtnQ0eL660xLrVXQFEcDADDD0n8TEuoLK+ 9rBg== X-Gm-Message-State: AAQBX9fKKejc/xao7l5UIgcmw5kgA5L5eKJNJAFFPvS2Md0542dSxbDC bT4fTmn7t4Zk37tCzkR92ag= X-Google-Smtp-Source: AKy350ZVk8+Ei+TV+4GGdj0W1xwoZVPnMiI9MhynZB1AsFil19iJwi0XmYRr9kmqdo9q1BV4k/E/1A== X-Received: by 2002:a05:600c:acb:b0:3ed:b6ad:54d with SMTP id c11-20020a05600c0acb00b003edb6ad054dmr5675428wmr.18.1680727155894; Wed, 05 Apr 2023 13:39:15 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c469300b003eda46d6792sm3259867wmo.32.2023.04.05.13.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 13:39:15 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 05/12] net: dsa: mt7530: remove p5_intf_sel default case from mt7530_setup_port5() Date: Wed, 5 Apr 2023 23:38:52 +0300 Message-Id: <20230405203859.391267-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There're two code paths for setting up port 5: mt7530_setup() -> mt7530_setup_port5() mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() On the first code path, priv->p5_intf_sel is either set to P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4 when mt7530_setup_port5() is run. On the second code path, priv->p5_intf_sel is set to P5_INTF_SEL_GMAC5 when mt7530_setup_port5() is run. Remove this default case which will never run. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index fccd59564532..8a47dcb96cdf 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -943,10 +943,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, = phy_interface_t interface) /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ val &=3D ~MHWTRAP_P5_DIS; break; - default: - dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", - priv->p5_intf_sel); - goto unlock_exit; } =20 /* Setup RGMII settings */ @@ -980,7 +976,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) priv->p5_intf_sel =3D=3D P5_INTF_SEL_PHY_P4) priv->p5_interface =3D interface; =20 -unlock_exit: mutex_unlock(&priv->reg_mutex); } =20 --=20 2.37.2 From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AD5BC761AF for ; Wed, 5 Apr 2023 20:39:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231516AbjDEUjv (ORCPT ); Wed, 5 Apr 2023 16:39:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234117AbjDEUjg (ORCPT ); Wed, 5 Apr 2023 16:39:36 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6C986A44; Wed, 5 Apr 2023 13:39:19 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id m6-20020a05600c3b0600b003ee6e324b19so22722327wms.1; Wed, 05 Apr 2023 13:39:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680727158; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ry2z2xzBFl6Ly3vSlf60f+roED9HAgz7ua4fkZgzGE0=; b=B10ji6xoiT0KxNstoIf5OK4ul/y1PldmpWHRRnHJt1TTMY8uy1Ri+rx+FbMG8mP5nx wTD2y33SyfmX093zp8tIpavy1sb+9KEomRXl/FO+f6xxOC/m9jruqhWPxaIQCdu1LVNf uvT/t3r/to1RYojP7TVRl8ook1fgIpCss11RcOxcLXlUurmJsQbXhBALHRSAFxiVVg5f ymEWzmFrLRRgAiYlmWj3C/y8x2kup19rTBLxrMKnHg+Y4h4mBKBFP6Nb/S9p9nmqCFSs KocXGXZdx8t7MCkX7DZ82p2f7imGHXztIQEeRqlIiNfvyu1RFK2Do2NIrLimLMw8Z5ff bpIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680727158; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ry2z2xzBFl6Ly3vSlf60f+roED9HAgz7ua4fkZgzGE0=; b=qWpyjiwgC0OjPptaSUwhq9JuEnu8lum84Nnm8CllOTYCRdlu+2OaUs7c4czK09K/Cn +lB4bVkrL3XUcG42oF0S4ylcuPODEJHyHwt10nX6hR0Lh2CHLpcxQSIRmdfSiJB1Rfd4 YiWnVe5RHV+3x92FcqnpbLBvgxvDXOJo3KXf0m5f1M5glK8mZGOBlf2g1k4jJhTppRFV dpgh3yZCPHyFi0u9X3+YywMHhlN0Rl4+JrXMIbGgUaziXhSapFhYPU6Otjyf3rvCikly /VzQi8hzGLLOABTiecRdCaj5NSO6tM7I3Cld6VTo/x7M8b6/YFuSyz41eJBW2fFg+pss CqAw== X-Gm-Message-State: AAQBX9cDdB2Uo0jOtjIJMcM5p8d/DgFK80kLYNHAky8Nxy1E81nSg419 hy1vYXEPQwv7fToPFF8X2cg= X-Google-Smtp-Source: AKy350bQFfU4n56kkWO8UhzXgxMrHnZq+NNzuA43JcBRFIly5bQiINuogGqFG5ekfNdRs/vk5zwdgA== X-Received: by 2002:a05:600c:ace:b0:3ed:ea48:cd92 with SMTP id c14-20020a05600c0ace00b003edea48cd92mr5970347wmr.15.1680727158320; Wed, 05 Apr 2023 13:39:18 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c469300b003eda46d6792sm3259867wmo.32.2023.04.05.13.39.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 13:39:17 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 06/12] net: dsa: mt7530: do not set CPU port interfaces to PHY_INTERFACE_MODE_NA Date: Wed, 5 Apr 2023 23:38:53 +0300 Message-Id: <20230405203859.391267-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There is no need to set priv->p5_interface and priv->p6_interface to PHY_INTERFACE_MODE_NA on mt7530_setup() and mt7531_setup(). As Vladimir explained, in include/linux/phy.h we have: typedef enum { PHY_INTERFACE_MODE_NA, In lack of other initialiser, the first element of an enum gets the value 0 in C. Then, "priv" is allocated by this driver with devm_kzalloc(), which means that its entire memory is zero-filled. So priv->p5_interface and priv->p6_interface are already set to 0, PHY_INTERFACE_MODE_NA. There is no code path between the devm_kzalloc(), and the position in mt7530_setup() and mt7531_setup() that would change the value of priv->p5_interface or priv->p6_interface from 0. The only place they are modified is mt753x_phylink_mac_config() but mt753x_phylink_mac_config() runs after mt753x_setup(), as can be seen on the code path below. mt7530_probe() -> dsa_register_switch() -> dsa_switch_probe() -> dsa_tree_setup() -> dsa_tree_setup_switches() -> dsa_switch_setup() -> ds->ops->setup(): mt753x_setup() -> dsa_tree_setup_ports() -> dsa_port_setup() [...] -> dsa_port_phylink_create() [...] -> phylink_mac_config() -> pl->mac_ops->mac_config(): dsa_port_phylink_mac_config() -> ds->ops->phylink_mac_config(): mt753x_phylink_mac_config() Therefore, do not put 0 into a variable containing 0. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 8a47dcb96cdf..fc5428baa905 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2247,8 +2247,6 @@ mt7530_setup(struct dsa_switch *ds) val |=3D MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); =20 - priv->p6_interface =3D PHY_INTERFACE_MODE_NA; - /* Enable and reset MIB counters */ mt7530_mib_reset(ds); =20 @@ -2466,10 +2464,6 @@ mt7531_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); =20 - /* Let phylink decide the interface later. */ - priv->p5_interface =3D PHY_INTERFACE_MODE_NA; - priv->p6_interface =3D PHY_INTERFACE_MODE_NA; - /* Enable PHY core PLL, since phy_device has not yet been created * provided for phy_[read,write]_mmd_indirect is called, we provide * our own mt7531_ind_mmd_phy_[read,write] to complete this --=20 2.37.2 From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A68EC7619A for ; Wed, 5 Apr 2023 20:40:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233498AbjDEUkH (ORCPT ); Wed, 5 Apr 2023 16:40:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234364AbjDEUji (ORCPT ); Wed, 5 Apr 2023 16:39:38 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 796D97EC0; Wed, 5 Apr 2023 13:39:22 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id m6-20020a05600c3b0600b003ee6e324b19so22722372wms.1; Wed, 05 Apr 2023 13:39:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680727161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+AqGSZF4EpWmaEiD6n9MEgNnwi2D/MewQMHt7iSnW7E=; b=Ek4DT1TER+RoJE0VsfQfGUf4TZgwsHm6vZmrebh0y/37TnlO2axskmRki1iM9Rg/C6 Ncvk5XpJ9p+m5Pxi9ZZx93nP1zSEkH1wcfoRym+6Iwyhwk1L7f5tgH76DBjSQBSp8LpN qSb7m9Z8L7plkOCrc4oSNVnZ1za0ilyJaXvlf13x8rdgM7H+3hZ8eAI7aVAiCM4FbbFR 91RR+0d5z4RyHnVYjsFzRUE8fJMyJ6vg/Ky8qqckTR/g/mLtr0lyUZW9zQnfWP04eTXa ny7uvNqjYe6xNkC5ckTfcyn/URJtijj/P8smNLm3wi4zSPb2mv1gMDrUMCF70sS6cKiv JOLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680727161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+AqGSZF4EpWmaEiD6n9MEgNnwi2D/MewQMHt7iSnW7E=; b=yK7HLkzhP5wNB2kyMsFLwhmQYLuuiakJ9AGNmEacWXz9rEr9qAyd8fmvSdojpK/ciK P11AbT/ZgSDddnMfiETXS9U7CkVyCyXSacDrxVqRfvp335MalONc9HxDg3FOJA+xdZcF aAS2DLIOBTSfd0J8BAyuc3cfDdGCDHpv6tmfLUNHjjywVaRa7Ggl452+yM4WrU7CRVBC 0nHfTjQxuqj5YuzQg45GGpU8Q7D8WuZdIlM6EF4Kh0h4gIQMe7KNAtqIOkjgIqinLm/9 Z7x0+VJ9lVP8QH8JtyqFOjOdV+NNwTeKhPlfmuino7hQrlNIm9bsozdt5RbGny0QaljH t7nQ== X-Gm-Message-State: AAQBX9eNsFMsLEVIEdmMv+alcFv5V8fANscO07fMlb75LTZwoeO7ydfu JEBU1aD0pRTgcqvkp4erRkY= X-Google-Smtp-Source: AKy350aT4FAqhfC0/9kboD0oQSivbuQDPR5durGHYt0RfNrcuqqS1szFafRfDpofNN9oqxEkHTlIZg== X-Received: by 2002:a05:600c:284:b0:3f0:396b:8b9c with SMTP id 4-20020a05600c028400b003f0396b8b9cmr5639675wmk.9.1680727160653; Wed, 05 Apr 2023 13:39:20 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c469300b003eda46d6792sm3259867wmo.32.2023.04.05.13.39.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 13:39:20 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 07/12] net: dsa: mt7530: call port 6 setup from mt7530_mac_config() Date: Wed, 5 Apr 2023 23:38:54 +0300 Message-Id: <20230405203859.391267-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL mt7530_pad_clk_setup() is called if port 6 is enabled. It used to do more things than setting up port 6. That part was moved to more appropriate locations, mt7530_setup() and mt7530_pll_setup(). Now that all it does is set up port 6, rename it to mt7530_setup_port6(), and move it to a more appropriate location, under mt7530_mac_config(). Leave an empty mt7530_pad_clk_setup() to satisfy the pad_setup function pointer. This is the call path for setting up the ports before: mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() -> mt753x_pad_setup() -> mt7530_pad_clk_setup() This is after: mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() -> mt7530_setup_port6() Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index fc5428baa905..c636a888d194 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -401,7 +401,7 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) =20 /* Setup port 6 interface mode and TRGMII TX circuit */ static int -mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) +mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; u32 ncpo1, ssc_delta, trgint, xtal; @@ -473,6 +473,12 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interf= ace_t interface) return 0; } =20 +static int +mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) +{ + return 0; +} + static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) { u32 val; @@ -2583,12 +2589,15 @@ mt7530_mac_config(struct dsa_switch *ds, int port, = unsigned int mode, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; + int ret; =20 - /* Only need to setup port5. */ - if (port !=3D 5) - return 0; - - mt7530_setup_port5(priv->ds, interface); + if (port =3D=3D 5) { + mt7530_setup_port5(priv->ds, interface); + } else if (port =3D=3D 6) { + ret =3D mt7530_setup_port6(priv->ds, interface); + if (ret) + return ret; + } =20 return 0; } --=20 2.37.2 From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E195DC76188 for ; Wed, 5 Apr 2023 20:40:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234092AbjDEUkT (ORCPT ); Wed, 5 Apr 2023 16:40:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234427AbjDEUjr (ORCPT ); Wed, 5 Apr 2023 16:39:47 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A09476B1; Wed, 5 Apr 2023 13:39:24 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id t4so32196455wra.7; Wed, 05 Apr 2023 13:39:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680727163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a6c6V/5LU1iA96LbQDMn3nYNgJi0pITa7Rc7pXzjwd8=; b=XZPhIj2o/qg1/gyE2R6SPJrBAUKxbIiUIuTX1is2BacHL8r50IEfMUej2/1aeuvtRV FdRSkJedwOlA+GjuTSfYFbO0jbUSHLDwlxNCu1bTXlHHQhMGoKi3v7rzMDhM4Fgw6PxN ugXbeFcxI/o3hHz1ZXOpPUp52OLB69TBFPocWKq4zauwDZzC4/8vWtZEvqrRWRTYH4Bs HS+/Pye0eX11PtDcKNvZqXfYeBlPAy0tDwWnlhJS91qZGTT6rK6pfnH1j/ERxAdhv3s3 it8aETPSNAzlrsqW7Wms//IdIcPSgrzimpzZSIXcQxwhhRA+K8NcFFELmYbbnxlpOyu3 0PeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680727163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a6c6V/5LU1iA96LbQDMn3nYNgJi0pITa7Rc7pXzjwd8=; b=uS4GYhkbmJjV1BLJcf5hNhvhuZ48xi8hqK+WGKt7v3f+ieSKvZtjjn0wp7MOWqZ6Fz 0mI2TND6AwV6n1zqDuZfsBBA+THoIHivQP+Gkx3kCrwXfNWIL5lbWX0UI6fCGUMO36Od CJByANj88Yxg9vGO/VaoeowC7yAXBjLOX5YQXnkkh3OuDClrVJOt4v+VCa0Tz5MqjV6A Z7V0QHVJYIoR6nXFQjEgBQ4mTjsuKc3vCU909O+g64GVO37ldbsi/QEq4xHWnQdCDfqG W1NM28+CJ58+OqCeSpQiLNH5XjLqNKjon9bCv725j224b8KM0QaXB+kGEnwgRvdT7bQK Q7RA== X-Gm-Message-State: AAQBX9dL9FdFjFmx+KPlfPZTMhWZKEeGJDzx9qgDD3CTLjU+Fwj2CZWh 59YrqGPi3hQ2YFZXZ0DeTm0= X-Google-Smtp-Source: AKy350Y6Oh6tCjeg4QzeeYsJD/AXXzE1Hsqg2ZRfWrjUjrNhiARwwu9Gc4MrcPLsHmPZe9yOMswj3w== X-Received: by 2002:a05:6000:14f:b0:2d2:29a4:4457 with SMTP id r15-20020a056000014f00b002d229a44457mr4491825wrx.13.1680727162992; Wed, 05 Apr 2023 13:39:22 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c469300b003eda46d6792sm3259867wmo.32.2023.04.05.13.39.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 13:39:22 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 08/12] net: dsa: mt7530: remove pad_setup function pointer Date: Wed, 5 Apr 2023 23:38:55 +0300 Message-Id: <20230405203859.391267-9-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The pad_setup function pointer was introduced with 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware"). It was being used to set up the core clock and port 6 of the MT7530 switch, and pll of the MT7531 switch. All of these were moved to more appropriate locations, and it was never used for the switch on the MT7988 SoC. Therefore, this function pointer hasn't got a use anymore. Remove it. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 36 ++---------------------------------- drivers/net/dsa/mt7530.h | 3 --- 2 files changed, 2 insertions(+), 37 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index c636a888d194..0a6d1c0872be 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -473,12 +473,6 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interfac= e_t interface) return 0; } =20 -static int -mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) -{ - return 0; -} - static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) { u32 val; @@ -488,12 +482,6 @@ static bool mt7531_dual_sgmii_supported(struct mt7530_= priv *priv) return (val & PAD_DUAL_SGMII_EN) !=3D 0; } =20 -static int -mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) -{ - return 0; -} - static void mt7531_pll_setup(struct mt7530_priv *priv) { @@ -2576,14 +2564,6 @@ static void mt7988_mac_port_get_caps(struct dsa_swit= ch *ds, int port, } } =20 -static int -mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *s= tate) -{ - struct mt7530_priv *priv =3D ds->priv; - - return priv->info->pad_setup(ds, state->interface); -} - static int mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) @@ -2754,8 +2734,6 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int = port, unsigned int mode, if (priv->p6_interface =3D=3D state->interface) break; =20 - mt753x_pad_setup(ds, state); - if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; =20 @@ -3053,11 +3031,6 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds,= int port, return 0; } =20 -static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interfa= ce) -{ - return 0; -} - static int mt7988_setup(struct dsa_switch *ds) { struct mt7530_priv *priv =3D ds->priv; @@ -3119,7 +3092,6 @@ const struct mt753x_info mt753x_table[] =3D { .phy_write_c22 =3D mt7530_phy_write_c22, .phy_read_c45 =3D mt7530_phy_read_c45, .phy_write_c45 =3D mt7530_phy_write_c45, - .pad_setup =3D mt7530_pad_clk_setup, .mac_port_get_caps =3D mt7530_mac_port_get_caps, .mac_port_config =3D mt7530_mac_config, }, @@ -3131,7 +3103,6 @@ const struct mt753x_info mt753x_table[] =3D { .phy_write_c22 =3D mt7530_phy_write_c22, .phy_read_c45 =3D mt7530_phy_read_c45, .phy_write_c45 =3D mt7530_phy_write_c45, - .pad_setup =3D mt7530_pad_clk_setup, .mac_port_get_caps =3D mt7530_mac_port_get_caps, .mac_port_config =3D mt7530_mac_config, }, @@ -3143,7 +3114,6 @@ const struct mt753x_info mt753x_table[] =3D { .phy_write_c22 =3D mt7531_ind_c22_phy_write, .phy_read_c45 =3D mt7531_ind_c45_phy_read, .phy_write_c45 =3D mt7531_ind_c45_phy_write, - .pad_setup =3D mt7531_pad_setup, .cpu_port_config =3D mt7531_cpu_port_config, .mac_port_get_caps =3D mt7531_mac_port_get_caps, .mac_port_config =3D mt7531_mac_config, @@ -3156,7 +3126,6 @@ const struct mt753x_info mt753x_table[] =3D { .phy_write_c22 =3D mt7531_ind_c22_phy_write, .phy_read_c45 =3D mt7531_ind_c45_phy_read, .phy_write_c45 =3D mt7531_ind_c45_phy_write, - .pad_setup =3D mt7988_pad_setup, .cpu_port_config =3D mt7988_cpu_port_config, .mac_port_get_caps =3D mt7988_mac_port_get_caps, .mac_port_config =3D mt7988_mac_config, @@ -3186,9 +3155,8 @@ mt7530_probe_common(struct mt7530_priv *priv) /* Sanity check if these required device operations are filled * properly. */ - if (!priv->info->sw_setup || !priv->info->pad_setup || - !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || - !priv->info->mac_port_get_caps || + if (!priv->info->sw_setup || !priv->info->phy_read_c22 || + !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps || !priv->info->mac_port_config) return -EINVAL; =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 01db5c9724fa..9e5b99b853ba 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -697,8 +697,6 @@ struct mt753x_pcs { * @phy_write_c22: Holding the way writing PHY port using C22 * @phy_read_c45: Holding the way reading PHY port using C45 * @phy_write_c45: Holding the way writing PHY port using C45 - * @pad_setup: Holding the way setting up the bus pad for a certain - * MAC port * @phy_mode_supported: Check if the PHY type is being supported on a cert= ain * port * @mac_port_validate: Holding the way to set addition validate type for a @@ -719,7 +717,6 @@ struct mt753x_info { int regnum); int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, int regnum, u16 val); - int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); int (*cpu_port_config)(struct dsa_switch *ds, int port); void (*mac_port_get_caps)(struct dsa_switch *ds, int port, struct phylink_config *config); --=20 2.37.2 From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 693E3C76188 for ; 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Wed, 05 Apr 2023 13:39:25 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c469300b003eda46d6792sm3259867wmo.32.2023.04.05.13.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 13:39:25 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 09/12] net: dsa: mt7530: move enabling port 6 to mt7530_setup_port6() Date: Wed, 5 Apr 2023 23:38:56 +0300 Message-Id: <20230405203859.391267-10-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Enable port 6 only when port 6 is being used. Read the HWTRAP_XTAL_MASK value from val now that val is equal to the value of MT7530_MHWTRAP. Update the comment on mt7530_setup() with a better explanation. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- Do I need to protect the register from being accessed by processes while this operation is being done? I don't see this on mt7530_setup() but it's being done on mt7530_setup_port5(). There's an oddity here. The XTAL mask is defined on the MT7530_HWTRAP register, but it's being read from MT7530_MHWTRAP instead which is at a different address. HWTRAP_XTAL_MASK and reading HWTRAP_XTAL_MASK from MT7530_MHWTRAP was both added with: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit?= id=3D7ef6f6f8d237fa6724108b57d9706cb5069688e4 I did this to test it: diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 46749aee3c49..7aa3b5828ac3 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -404,7 +404,7 @@ static int mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; - u32 ncpo1, ssc_delta, trgint, xtal, val; + u32 ncpo1, ssc_delta, trgint, xtal, xtal2, val; =20 /* Enable port 6 */ val =3D mt7530_read(priv, MT7530_MHWTRAP); @@ -413,6 +413,21 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interfac= e_t interface) mt7530_write(priv, MT7530_MHWTRAP, val); =20 xtal =3D val & HWTRAP_XTAL_MASK; + xtal2 =3D mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; + + if (xtal =3D=3D HWTRAP_XTAL_20MHZ) + dev_info(priv->dev, "xtal 20 Mhz\n"); + if (xtal =3D=3D HWTRAP_XTAL_25MHZ) + dev_info(priv->dev, "xtal 25 Mhz\n"); + if (xtal =3D=3D HWTRAP_XTAL_40MHZ) + dev_info(priv->dev, "xtal 40 Mhz\n"); + + if (xtal2 =3D=3D HWTRAP_XTAL_20MHZ) + dev_info(priv->dev, "actual xtal 20 Mhz\n"); + if (xtal2 =3D=3D HWTRAP_XTAL_25MHZ) + dev_info(priv->dev, "actual xtal 25 Mhz\n"); + if (xtal2 =3D=3D HWTRAP_XTAL_40MHZ) + dev_info(priv->dev, "actual xtal 40 Mhz\n"); =20 if (xtal =3D=3D HWTRAP_XTAL_20MHZ) { dev_err(priv->dev, Both ended up reporting 40 Mhz so I'm not sure if this is a bug or intended to be done this way. Please advise. Ar=C4=B1n=C3=A7 --- drivers/net/dsa/mt7530.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 0a6d1c0872be..70a673347cf9 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -404,9 +404,13 @@ static int mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; - u32 ncpo1, ssc_delta, trgint, xtal; + u32 ncpo1, ssc_delta, trgint, xtal, val; =20 - xtal =3D mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; + val =3D mt7530_read(priv, MT7530_MHWTRAP); + val &=3D ~MHWTRAP_P6_DIS; + mt7530_write(priv, MT7530_MHWTRAP, val); + + xtal =3D val & HWTRAP_XTAL_MASK; =20 if (xtal =3D=3D HWTRAP_XTAL_20MHZ) { dev_err(priv->dev, @@ -2235,9 +2239,9 @@ mt7530_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_MASK, RD_TAP(16)); =20 - /* Enable port 6 */ + /* Enable PHY access and operate in manual mode */ val =3D mt7530_read(priv, MT7530_MHWTRAP); - val &=3D ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; + val &=3D ~MHWTRAP_PHY_ACCESS; val |=3D MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); =20 --=20 2.37.2 From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDF24C761AF for ; Wed, 5 Apr 2023 20:40:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234549AbjDEUke (ORCPT ); Wed, 5 Apr 2023 16:40:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234504AbjDEUkE (ORCPT ); Wed, 5 Apr 2023 16:40:04 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B8567ECD; Wed, 5 Apr 2023 13:39:29 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id l15-20020a05600c4f0f00b003ef6d684102so19156898wmq.3; Wed, 05 Apr 2023 13:39:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680727168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Wk3K9bbT+tv5kBnVohJcLc2nqRP/uYdhv43DLYVwvrA=; b=Nbp9QixTsTqXq+nlznFJzTPRU25T0EZ9MfYB0i3Bd1kaz5zF7jLHuPO4ztD5MflGWR AN5suyxWvODfN++LkEf+UECj7CDSevmkzrBgi2ZCzKzZ/BV4DYNWV8zJjeenQrSm4KbQ aQIZRGNJMAzD+Omq1Z53JJ9iH6Jah9w3XpnoC0d0WC9bXqgfFK+UtRuDJIBPJzAenZ4S 0JGtpgmFd1p4bI7KdW7XrBjdmn7NVm3SGGDWZP8BDs9IqegGqmd4aQ/WgMsbzzRhJP0E W/WQeSkfeB/wwl9yl+SR4cGk2VknUiNU07J2Ua0LjagY+kM6F+4lA47K4LU7affatRR4 +6tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680727168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wk3K9bbT+tv5kBnVohJcLc2nqRP/uYdhv43DLYVwvrA=; b=p42KtFOS0/pdLZ4QkXu7HCFRQAQT8QN0eOnmqYYq5J23NRPnKrQ56YbRsooY9p0Sz2 +g0qpUcIikCZLTP2ejMIwfn5YWYzBOFX39q0ibfYRQEmdwzvZ5J10Xl1varVK8MmEpHJ r39psTHH0uknZcrosCilSuYUBM0ede7RyLHwU6aD1kcg9KjlGfBypaOEuOyNIeWRsNCp gOw7q2hnBx3UdqwIFVbO6o6VtTWZMJKniDr/RZdoPmeGFYgSu/6Jfl/ZbP6/GaEZ2v+2 4l12ufAE80om6V/1abshnTxYXA+eiHB9zyPrq0EudeVbBxcrgzRT5PQVFPGuW1ztq2eF a7aQ== X-Gm-Message-State: AAQBX9fwgxNrWe83Ee26sf0sbASuoJV+YexnZlF/hg+MuLvoBfkMlCgO zOmUMYIxE+/kuJeIEtjZ3xA= X-Google-Smtp-Source: AKy350aFpJYsbdWGizzfVNQlwDH+aMdywoXrMBy75yzELYvUe4GwnL9XMmWJ89kOSD/km6FgxUxAYg== X-Received: by 2002:a7b:c38a:0:b0:3ed:e715:1784 with SMTP id s10-20020a7bc38a000000b003ede7151784mr6432135wmj.15.1680727167948; Wed, 05 Apr 2023 13:39:27 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c469300b003eda46d6792sm3259867wmo.32.2023.04.05.13.39.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 13:39:27 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 10/12] net: dsa: mt7530: switch to if/else statements on mt7530_setup_port6() Date: Wed, 5 Apr 2023 23:38:57 +0300 Message-Id: <20230405203859.391267-11-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL This code is from before this driver was converted to phylink API. Phylink deals with the unsupported interface cases before mt7530_setup_port6() is run. Therefore, the default case would never run. However, it must be defined nonetheless to handle all the remaining enumeration values, the phy-modes. Switch to if/else statements which simplifies the code. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 70a673347cf9..fe496d865478 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -404,7 +404,7 @@ static int mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; - u32 ncpo1, ssc_delta, trgint, xtal, val; + u32 ncpo1, ssc_delta, xtal, val; =20 val =3D mt7530_read(priv, MT7530_MHWTRAP); val &=3D ~MHWTRAP_P6_DIS; @@ -419,16 +419,18 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interfa= ce_t interface) return -EINVAL; } =20 - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - trgint =3D 0; - break; - case PHY_INTERFACE_MODE_TRGMII: - trgint =3D 1; + if (interface =3D=3D PHY_INTERFACE_MODE_RGMII) { + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, + P6_INTF_MODE(0)); + } else { + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, + P6_INTF_MODE(1)); + if (xtal =3D=3D HWTRAP_XTAL_25MHZ) ssc_delta =3D 0x57; else ssc_delta =3D 0x87; + if (priv->id =3D=3D ID_MT7621) { /* PLL frequency: 150MHz: 1.2GBit */ if (xtal =3D=3D HWTRAP_XTAL_40MHZ) @@ -441,17 +443,7 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interfac= e_t interface) if (xtal =3D=3D HWTRAP_XTAL_25MHZ) ncpo1 =3D 0x1400; } - break; - default: - dev_err(priv->dev, "xMII interface %d not supported\n", - interface); - return -EINVAL; - } - - mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, - P6_INTF_MODE(trgint)); =20 - if (trgint) { /* Disable the MT7530 TRGMII clocks */ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); =20 --=20 2.37.2 From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B0EEC7619A for ; Wed, 5 Apr 2023 20:40:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234641AbjDEUkw (ORCPT ); Wed, 5 Apr 2023 16:40:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234377AbjDEUkP (ORCPT ); Wed, 5 Apr 2023 16:40:15 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 183E765B2; Wed, 5 Apr 2023 13:39:32 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id l15-20020a05600c4f0f00b003ef6d684102so19156961wmq.3; Wed, 05 Apr 2023 13:39:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680727170; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a9BgVJEEYWS/nr7ufBquG0YTtl1dQzZWs/MVrntK8ZE=; b=PkCe8EUwo59MuxO0b6KKI0EmM0HxoC38GvoQCL9HKBu3Pi5g9oGx43peL0MKckQs05 9GTz+/qxJf8/I4YzJWNBHoxaqLYtCgzAi+4f3uduLglyaLnYD8bvZYKoMHf5SSvgNBrV 7ASNECmnIIspbW3qf7+L4jOm3cisQ42pq0C2zRANZt9PBwUTXmU4HV2ZE31zBqtBO7T0 Rnw7v6ZpKZdutrO2fHfH9Hi2hZ5dEftWF2d+Z73dcyXWJ3QsHayuBm8tzTjHTGb+ph/E JzpsdA2CZPlKGb0u5yldIRaZ8s5eu93/BO+XocnBJwc3GTWOQJ/rJXA1295X0tm5hTSs XDtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680727170; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a9BgVJEEYWS/nr7ufBquG0YTtl1dQzZWs/MVrntK8ZE=; b=oINRtDsAlSuUp0EMLSBrfeSObCH5W+TDEx/tom3Qus78lCiS807/KudDhinohB1WG3 KsUtLT0pBvs1WRK8NBv5J2WaV41FC6tgiIpD574OlhVBdxB+rN+VV3n4yKqf53Hfv7BU OoKVxiaoblr69i+ewVVSDufIBAvH/vNOPrmA/6klmqBe5XmYliYpUHxkhoegedYtQbp5 Dc/3xmILoIXVkqmqfSmuo5LKzu0sFAnauMiGjtpIwFNw5z6ie4Q/1g9PvSj1n/+Dihs3 /itZqZRYLmYALo5MMtNlzL04qZXQATISpnU0M/ymgpcXpVhD8FBSYJnsWqAxHttzxDfY U1BQ== X-Gm-Message-State: AAQBX9eGJE6J6m+yA1baDDtTIRVlXAAbf9X2L+JHGyQFYNeTuXgIbc1L +BltphkL5Ypf+OW994W6kdI= X-Google-Smtp-Source: AKy350ak9wGsiF9xXKquHuS6fiWGFlLoT/KizsEmKlqSw6wiiOnCOZh9KwtUQUXE/BoiyAZ5k1Hx1Q== X-Received: by 2002:a1c:7211:0:b0:3ef:7584:9896 with SMTP id n17-20020a1c7211000000b003ef75849896mr5529893wmc.26.1680727170331; Wed, 05 Apr 2023 13:39:30 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c469300b003eda46d6792sm3259867wmo.32.2023.04.05.13.39.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 13:39:29 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 11/12] net: dsa: mt7530: set TRGMII RD TAP if trgmii is being used Date: Wed, 5 Apr 2023 23:38:58 +0300 Message-Id: <20230405203859.391267-12-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL This code sets the Read Data (RD) TAP value to 16 for all TRGMII control registers. The for loop iterates over all the TRGMII control registers, and mt7530_rmw() function is used to perform a read-modify-write operation on each register's RD_TAP field to set its value to 16. This operation is used to tune the timing of the read data signal in TRGMII to match the TX signal of the link partner. Run this if trgmii is being used. Since this code doesn't lower the driving, there's no apparent benefit to run this if trgmii is not being used. Add a comment to explain the code. Thanks to =E8=B6=99=E7=9A=8E=E5=AE=8F (Landen Chao) for pointing out what t= he code does. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index fe496d865478..384e601b2ecd 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -404,7 +404,7 @@ static int mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; - u32 ncpo1, ssc_delta, xtal, val; + u32 ncpo1, ssc_delta, i, xtal, val; =20 val =3D mt7530_read(priv, MT7530_MHWTRAP); val &=3D ~MHWTRAP_P6_DIS; @@ -464,6 +464,11 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interfac= e_t interface) =20 /* Enable the MT7530 TRGMII clocks */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); + + /* Set the Read Data TAP value of the MT7530 TRGMII */ + for (i =3D 0; i < NUM_TRGMII_CTRL; i++) + mt7530_rmw(priv, MT7530_TRGMII_RD(i), + RD_TAP_MASK, RD_TAP(16)); } =20 return 0; @@ -2227,10 +2232,6 @@ mt7530_setup(struct dsa_switch *ds) mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), TD_DM_DRVP(8) | TD_DM_DRVN(8)); =20 - for (i =3D 0; i < NUM_TRGMII_CTRL; i++) - mt7530_rmw(priv, MT7530_TRGMII_RD(i), - RD_TAP_MASK, RD_TAP(16)); - /* Enable PHY access and operate in manual mode */ val =3D mt7530_read(priv, MT7530_MHWTRAP); val &=3D ~MHWTRAP_PHY_ACCESS; --=20 2.37.2 From nobody Fri May 17 06:43:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7119C7619A for ; Wed, 5 Apr 2023 20:40:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234652AbjDEUk4 (ORCPT ); Wed, 5 Apr 2023 16:40:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233939AbjDEUkS (ORCPT ); Wed, 5 Apr 2023 16:40:18 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 199FA83CC; Wed, 5 Apr 2023 13:39:36 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id l15-20020a05600c4f0f00b003ef6d684102so19157009wmq.3; Wed, 05 Apr 2023 13:39:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680727172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L71GAIfC9eueAFpPEM3jN5dqLC94Zw3zCdbNg29s88s=; b=MiTmmxWpXe2fE/0oNn2g7hsWoWsYD9g6VdQBcZ51eEukbBygXXyawyTPJyOfz3Z6p0 cP26KmucIcfZDP9eWNZ9t4k0cF8AUAK7UAY9OotSb13c1HaJt06z/q3qZQG3H7y8HLaZ bblYlI9ka+HOwqFjA9pVrrsTSZ+mydgTe2Sx0GM9vIc7WubqO42qrjM/EisAxYuNoQxO ulZq8U4qvEP4vJ9RYD6CeXD/5+JVKy/ZSTvRATHaZYCwxUHyv29Jp3xr9D3szlzLZN0U 2c+L1zloAfqFXxjfTexsA/ojqOrhJj1rcTmrVEm8yWy7/UCp4/amn+U06U3fmp2bjGYn fMGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680727172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L71GAIfC9eueAFpPEM3jN5dqLC94Zw3zCdbNg29s88s=; b=S0ttEVWXZMLZAAjk4xPPhxxJ1EEeDkzKF/GXnZHU9n5+X1X3ayF0xwWqVAmQji7LGu EtE/Jmnj3rdvOoJd0rH7hfbyAiFIslR6EPPimX6E54nCKifnkIjh7p5gm7Pt6qIj6ULO HvOfdANXyiFv8H2To09klLxuAYRu8VoLGSxtyHYuVhR07U9Dh5nRusRcwmJj9WA1nU4n TCvYHxZLI5fRYlWzqr31grkz3i8gXwsUM6g+RXBxq/IGsQKPaeF4c43U5yDlYd3pr9+u hFWEbF0Wxw88LYkefJHSG1/zjXyL7vGKjjOK0a1R4O6q9nCgpkxXDCgMTWlxNxxV8ZOB Q3CA== X-Gm-Message-State: AAQBX9c0QQtNJ8CGK2ckzSBDvCUlu2fMUOcmYekrjoN17fnsyhXZ5Uyu 0aX83v4OGxJZIIeF3WBTKCI= X-Google-Smtp-Source: AKy350ZfAZeQEKVf1n9tV8rwVhEY06YRX4VGzkFY8HUbcQ7WPJqd971FrD9WXiRCZ7cd2jeZ0sQzUg== X-Received: by 2002:a05:600c:218d:b0:3eb:9822:f0 with SMTP id e13-20020a05600c218d00b003eb982200f0mr5728897wme.30.1680727172707; Wed, 05 Apr 2023 13:39:32 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c469300b003eda46d6792sm3259867wmo.32.2023.04.05.13.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 13:39:32 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 12/12] net: dsa: mt7530: move lowering port 5 RGMII driving to mt7530_setup() Date: Wed, 5 Apr 2023 23:38:59 +0300 Message-Id: <20230405203859.391267-13-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230405203859.391267-1-arinc.unal@arinc9.com> References: <20230405203859.391267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Move lowering Tx driving of rgmii on port 5 to right before lowering of Tx driving of trgmii on port 6 on mt7530_setup(). This way, the switch should consume less power regardless of port 5 being used. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- Emphasise on the "should". Ar=C4=B1n=C3=A7 --- drivers/net/dsa/mt7530.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 384e601b2ecd..6fbbdcb5987f 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -956,10 +956,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, = phy_interface_t interface) /* P5 RGMII TX Clock Control: delay x */ mt7530_write(priv, MT7530_P5RGMIITXCR, CSR_RGMII_TXC_CFG(0x10 + tx_delay)); - - /* reduce P5 RGMII Tx driving, 8mA */ - mt7530_write(priv, MT7530_IO_DRV_CR, - P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); } =20 mt7530_write(priv, MT7530_MHWTRAP, val); @@ -2227,6 +2223,10 @@ mt7530_setup(struct dsa_switch *ds) =20 mt7530_pll_setup(priv); =20 + /* Lower P5 RGMII Tx driving, 8mA */ + mt7530_write(priv, MT7530_IO_DRV_CR, + P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); + /* Lower Tx driving for TRGMII path */ for (i =3D 0; i < NUM_TRGMII_CTRL; i++) mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), --=20 2.37.2