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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT007.mail.protection.outlook.com (10.13.177.109) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6277.28 via Frontend Transport; Wed, 5 Apr 2023 17:10:41 +0000 Received: from BLR5CG134614W.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 5 Apr 2023 12:10:34 -0500 From: K Prateek Nayak To: , , , , , , , , CC: , , , , , Subject: [RFC PATCH v2 3/4] perf: Extract building cache level for a CPU into separate function Date: Wed, 5 Apr 2023 22:39:05 +0530 Message-ID: <20230405170906.2510-4-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405170906.2510-1-kprateek.nayak@amd.com> References: <20230405170906.2510-1-kprateek.nayak@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT007:EE_|DS0PR12MB8368:EE_ X-MS-Office365-Filtering-Correlation-Id: f96774c6-1933-4249-7201-08db35f8af78 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Apr 2023 17:10:41.4812 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f96774c6-1933-4249-7201-08db35f8af78 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8368 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" build_caches() builds the complete cache topology of the system by iterating over all CPU, building and comparing cache levels of each CPU, keeping only the unique ones at the end. Extract the function that build the cache levels for a single CPU into a separate function. Expose this function to be used elsewhere in perf too. Signed-off-by: K Prateek Nayak --- tools/perf/util/header.c | 62 +++++++++++++++++++++++++--------------- tools/perf/util/header.h | 4 +++ 2 files changed, 43 insertions(+), 23 deletions(-) diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c index 2daaee5065ef..357879dd8333 100644 --- a/tools/perf/util/header.c +++ b/tools/perf/util/header.c @@ -1227,38 +1227,54 @@ static void cpu_cache_level__fprintf(FILE *out, str= uct cpu_cache_level *c) fprintf(out, "L%d %-15s %8s [%s]\n", c->level, c->type, c->size, c->map); } =20 -#define MAX_CACHE_LVL 4 - -static int build_caches(struct cpu_cache_level caches[], u32 *cntp) +/* + * Build caches levels for a particular CPU from the data in + * /sys/devices/system/cpu/cpu/cache/ + * The cache level data is stored in caches[] from index at + * *cntp. + */ +int build_caches_for_cpu(u32 cpu, struct cpu_cache_level caches[], u32 *cn= tp) { - u32 i, cnt =3D 0; - u32 nr, cpu; u16 level; =20 - nr =3D cpu__max_cpu().cpu; + for (level =3D 0; level < MAX_CACHE_LVL; level++) { + struct cpu_cache_level c; + int err; + u32 i; =20 - for (cpu =3D 0; cpu < nr; cpu++) { - for (level =3D 0; level < MAX_CACHE_LVL; level++) { - struct cpu_cache_level c; - int err; + err =3D cpu_cache_level__read(&c, cpu, level); + if (err < 0) + return err; =20 - err =3D cpu_cache_level__read(&c, cpu, level); - if (err < 0) - return err; + if (err =3D=3D 1) + break; =20 - if (err =3D=3D 1) + for (i =3D 0; i < *cntp; i++) { + if (cpu_cache_level__cmp(&c, &caches[i])) break; + } =20 - for (i =3D 0; i < cnt; i++) { - if (cpu_cache_level__cmp(&c, &caches[i])) - break; - } + if (i =3D=3D *cntp) { + caches[*cntp] =3D c; + *cntp =3D *cntp + 1; + } else + cpu_cache_level__free(&c); + } =20 - if (i =3D=3D cnt) - caches[cnt++] =3D c; - else - cpu_cache_level__free(&c); - } + return 0; +} + +static int build_caches(struct cpu_cache_level caches[], u32 *cntp) +{ + u32 nr, cpu, cnt =3D 0; + + nr =3D cpu__max_cpu().cpu; + + for (cpu =3D 0; cpu < nr; cpu++) { + int ret =3D build_caches_for_cpu(cpu, caches, &cnt); + + if (ret) + return ret; } *cntp =3D cnt; return 0; diff --git a/tools/perf/util/header.h b/tools/perf/util/header.h index e3861ae62172..94cf2ffb6e60 100644 --- a/tools/perf/util/header.h +++ b/tools/perf/util/header.h @@ -177,7 +177,11 @@ int do_write(struct feat_fd *fd, const void *buf, size= _t size); int write_padded(struct feat_fd *fd, const void *bf, size_t count, size_t count_aligned); =20 +#define MAX_CACHE_LVL 4 + int is_cpu_online(unsigned int cpu); +int build_caches_for_cpu(u32 cpu, struct cpu_cache_level caches[], u32 *cn= tp); + /* * arch specific callback */ --=20 2.34.1