From nobody Wed Feb 11 06:53:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0469C761A6 for ; Wed, 5 Apr 2023 00:45:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236636AbjDEAp3 (ORCPT ); Tue, 4 Apr 2023 20:45:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236610AbjDEAp0 (ORCPT ); Tue, 4 Apr 2023 20:45:26 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6612018E for ; Tue, 4 Apr 2023 17:45:25 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id z16-20020a170902d55000b001a06f9b5e31so20500520plf.21 for ; Tue, 04 Apr 2023 17:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1680655525; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=7DA+p9LgbhVdVl+ZZN2EOFJj3Y+toC812cwG1G1Tydo=; b=NuptfWe+kbxpMI4xsKwwX3YVDMgXaZ48Y3wNEkIDr743/Q757lyf/pOnOzUmRThrUq 65zXsyfaIMgHd3AgFVjMbeNqzFVtITy9vvBN071dZtWEiJNTq10X+JDf/aMndem5ymbD j+fFgjBgOTirtIvdmAic2l7FUDkz7jodobZqdztSLKApS9S4jEE7fxeXP2uaFoz16Cvw JJrpTZ3A8ats7oTsoLcBGJHg68R5EgXNSbnA8OGHVYnEnQnmU6KvmtyW8RBB9lksCtyb TqECMaLutBKQk+nDl5CQiWAwH1KAVdwxeQio5mK3jQNYSMESSjyDxcv6PFgBSqd8Qmc0 ytNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680655525; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7DA+p9LgbhVdVl+ZZN2EOFJj3Y+toC812cwG1G1Tydo=; b=xqfUUWbNVnAQJI2cqzVUp3JrwIdSjizehSXw68V/XyjgMB8GlMxSKPu3pZPbOlkC8K NzxIYKDddOGLbGIePbvxT2mIRjb8HGTxlHYO4og7m9FnpXaPPTA6WHsH0Ci3q51BFWu3 AsbNp3/xUkNKceD66y71l62Z0ncxNQiBbieQukipsMiSCJUeIFFtE3YebdMk+IMXQm3A jwT8a4Q6aX/mmMCpQEBShDtFu/ngYCmt5gBjLNp3cJ2PZ9JiJCCWbcD4bBxW/6k/FniX mev0fRUChio3CwioUCeKwP+VXrce0i6F0ipQVXxirlMr9AwpUwkKAkHIGil/6qzamx5c 0Ilg== X-Gm-Message-State: AAQBX9c4mI353kYiIrhCcc+DU86b0J5lCYOg6gNynQCEbDJA9PKpIJSM vR52oR24Sc8lvqTQxM9xzpjm2wv9lTs= X-Google-Smtp-Source: AKy350a9xMMtKcyXM43Qy4kq9QpFU/MleKPOetKKD30yFWZgJjZ74PVPrD/jtOo6/RYqzYmi+8Mclk8+mak= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:ba94:b0:1a0:48ff:5388 with SMTP id k20-20020a170902ba9400b001a048ff5388mr1806065pls.6.1680655524982; Tue, 04 Apr 2023 17:45:24 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 4 Apr 2023 17:45:15 -0700 In-Reply-To: <20230405004520.421768-1-seanjc@google.com> Mime-Version: 1.0 References: <20230405004520.421768-1-seanjc@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230405004520.421768-2-seanjc@google.com> Subject: [PATCH v4 1/6] KVM: x86: Add a helper to handle filtering of unpermitted XCR0 features From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Lewis , Mingwei Zhang , Jim Mattson Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aaron Lewis Add a helper, kvm_get_filtered_xcr0(), to dedup code that needs to account for XCR0 features that require explicit opt-in on a per-process basis. In addition to documenting when KVM should/shouldn't consult xstate_get_guest_group_perm(), the helper will also allow sanitizing the filtered XCR0 to avoid enumerating architecturally illegal XCR0 values, e.g. XTILE_CFG without XTILE_DATA. No functional changes intended. Signed-off-by: Aaron Lewis Reviewed-by: Mingwei Zhang [sean: rename helper, move to x86.h, massage changelog] Signed-off-by: Sean Christopherson Reviewed-by: Aaron Lewis Tested-by: Aaron Lewis --- arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/x86.c | 4 +--- arch/x86/kvm/x86.h | 13 +++++++++++++ 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 6972e0be60fa..542bcaab3592 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -996,7 +996,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_arra= y *array, u32 function) entry->eax =3D entry->ebx =3D entry->ecx =3D 0; break; case 0xd: { - u64 permitted_xcr0 =3D kvm_caps.supported_xcr0 & xstate_get_guest_group_= perm(); + u64 permitted_xcr0 =3D kvm_get_filtered_xcr0(); u64 permitted_xss =3D kvm_caps.supported_xss; =20 entry->eax &=3D permitted_xcr0; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 2c0ff40e5345..7bac4162cfae 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4567,9 +4567,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, lon= g ext) r =3D 0; break; case KVM_CAP_XSAVE2: { - u64 guest_perm =3D xstate_get_guest_group_perm(); - - r =3D xstate_required_size(kvm_caps.supported_xcr0 & guest_perm, false); + r =3D xstate_required_size(kvm_get_filtered_xcr0(), false); if (r < sizeof(struct kvm_xsave)) r =3D sizeof(struct kvm_xsave); break; diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 203fb6640b5b..b6c6988d99b5 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -315,6 +315,19 @@ extern struct kvm_caps kvm_caps; =20 extern bool enable_pmu; =20 +/* + * Get a filtered version of KVM's supported XCR0 that strips out dynamic + * features for which the current process doesn't (yet) have permission to= use. + * This is intended to be used only when enumerating support to userspace, + * e.g. in KVM_GET_SUPPORTED_CPUID and KVM_CAP_XSAVE2, it does NOT need to= be + * used to check/restrict guest behavior as KVM rejects KVM_SET_CPUID{2} if + * userspace attempts to enable unpermitted features. + */ +static inline u64 kvm_get_filtered_xcr0(void) +{ + return kvm_caps.supported_xcr0 & xstate_get_guest_group_perm(); +} + static inline bool kvm_mpx_supported(void) { return (kvm_caps.supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_= BNDCSR)) --=20 2.40.0.348.gf938b09366-goog From nobody Wed Feb 11 06:53:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40107C6FD1D for ; Wed, 5 Apr 2023 00:45:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236715AbjDEApd (ORCPT ); Tue, 4 Apr 2023 20:45:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236697AbjDEAp2 (ORCPT ); Tue, 4 Apr 2023 20:45:28 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 591AF4693 for ; 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charset="utf-8" Filter out XTILE_CFG from the supported XCR0 reported to userspace if the current process doesn't have access to XTILE_DATA. Attempting to set XTILE_CFG in XCR0 will #GP if XTILE_DATA is also not set, and so keeping XTILE_CFG as supported results in explosions if userspace feeds KVM_GET_SUPPORTED_CPUID back into KVM and the guest doesn't sanity check CPUID. Fixes: 445ecdf79be0 ("kvm: x86: Exclude unpermitted xfeatures at KVM_GET_SU= PPORTED_CPUID") Reported-by: Aaron Lewis Signed-off-by: Sean Christopherson Reviewed-by: Aaron Lewis Tested-by: Aaron Lewis --- arch/x86/kvm/x86.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index b6c6988d99b5..3402d69820da 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -3,6 +3,7 @@ #define ARCH_X86_KVM_X86_H =20 #include +#include #include #include #include "kvm_cache_regs.h" @@ -325,7 +326,22 @@ extern bool enable_pmu; */ static inline u64 kvm_get_filtered_xcr0(void) { - return kvm_caps.supported_xcr0 & xstate_get_guest_group_perm(); + u64 permitted_xcr0 =3D kvm_caps.supported_xcr0; + + BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC !=3D XFEATURE_MASK_XTILE_DATA); + + if (permitted_xcr0 & XFEATURE_MASK_USER_DYNAMIC) { + permitted_xcr0 &=3D xstate_get_guest_group_perm(); + + /* + * Treat XTILE_CFG as unsupported if the current process isn't + * allowed to use XTILE_DATA, as attempting to set XTILE_CFG in + * XCR0 without setting XTILE_DATA is architecturally illegal. + */ + if (!(permitted_xcr0 & XFEATURE_MASK_XTILE_DATA)) + permitted_xcr0 &=3D ~XFEATURE_MASK_XTILE_CFG; + } + return permitted_xcr0; } =20 static inline bool kvm_mpx_supported(void) --=20 2.40.0.348.gf938b09366-goog From nobody Wed Feb 11 06:53:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33488C6FD1D for ; Wed, 5 Apr 2023 00:45:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236705AbjDEAph (ORCPT ); Tue, 4 Apr 2023 20:45:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236610AbjDEAp3 (ORCPT ); Tue, 4 Apr 2023 20:45:29 -0400 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDB124C0C for ; Tue, 4 Apr 2023 17:45:28 -0700 (PDT) Received: by mail-pf1-x44a.google.com with SMTP id y186-20020a62cec3000000b00627df3d6ec4so15517285pfg.12 for ; Tue, 04 Apr 2023 17:45:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1680655528; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=tf25xAl4fSdxFBAk8i0l5aGjOrxXQadDD1CZezPxob4=; b=k3vSRE8uQSYLQ5FHcz/pee6bDiPafNfanLHpLWinnqWSebl9zem+gxu9QQCpk/1Brr 55gJmi5Wx+I48U9ScE+y+g8gHjPKFwfcATMGdcaqLioTN3kx0U6W9NqCr3xKtOt3dqAL 41/V11LD7CC3rDGsHXBIiRdUOer0/+Nyl1JEuiv0BHHyHp2Td/Ok924VfjEFsKwwEojB ywDI8B4uzpOSjrB94WT9uSVf4u9rj6DcnfUdsQZBto5gS3FaVEHCmdVeqFPs+wEtWcbW J26aicb/UNXWJw2I9Yo0vTBRTQr5QMnYiGkS/yGxNxB14JmxviepHPNH3t+5kfJkCixT t8eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680655528; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=tf25xAl4fSdxFBAk8i0l5aGjOrxXQadDD1CZezPxob4=; b=uJTzKBMYF7gMmObmPTpF4T69ohceqXdN1W1xJpScdfXKDd2/FRz8HaDie1sFARzNUq HCcXl3K/KlZVNgY7ZN+HCHvP8ZxtKDYfmWv+2Z9jeegQ6S6FeLm2xt/tJPJb644n3jI/ sVTk0ULFj17S1jcRsu06EpSdXGPCYmEmFerYC0BqD4rA5i10eSMR19hLFAYewytVtwOU N+MkxlbnLrlB+r8s+uywhFz3Xj99s37ZgjbujFMZclI6jdKcYbKiY4PLMS+I3el0yhuw BgPcykeoxs6xEZbopX4yO7+UpCqfEYlGA4B0GQ681T7nBIJ+w0MtxFVlY+EJ9ih6tyoJ Jlfw== X-Gm-Message-State: AAQBX9dbk45QmDMNJgLQHNJdbvrK+K3TBjoMI158NjzaPKpDZGZTzdq3 RElae4iTEqvw/Ew1oQii5VR8im6phEE= X-Google-Smtp-Source: AKy350YQgPiVQ7TtKQ68stor3n0AywFETiUdHnWp6vGFe/hNxqXs6gbyqffX7Pgd+A5LSfaogEOyIqxTAkE= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:b692:b0:19f:3aa9:9ea1 with SMTP id c18-20020a170902b69200b0019f3aa99ea1mr1802510pls.8.1680655528391; Tue, 04 Apr 2023 17:45:28 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 4 Apr 2023 17:45:17 -0700 In-Reply-To: <20230405004520.421768-1-seanjc@google.com> Mime-Version: 1.0 References: <20230405004520.421768-1-seanjc@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230405004520.421768-4-seanjc@google.com> Subject: [PATCH v4 3/6] KVM: selftests: Move XGETBV and XSETBV helpers to common code From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Lewis , Mingwei Zhang , Jim Mattson Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aaron Lewis The instructions XGETBV and XSETBV are useful to other tests. Move them to processor.h to make them more broadly available. No functional change intended. Reviewed-by: Jim Mattson Signed-off-by: Aaron Lewis Reviewed-by: Mingwei Zhang [sean: reword shortlog] Signed-off-by: Sean Christopherson Reviewed-by: Aaron Lewis Tested-by: Aaron Lewis --- .../selftests/kvm/include/x86_64/processor.h | 18 ++++++++++++++ tools/testing/selftests/kvm/x86_64/amx_test.c | 24 +++---------------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index 3538fa6db72d..f6061fe7057f 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -510,6 +510,24 @@ static inline void set_cr4(uint64_t val) __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); } =20 +static inline u64 xgetbv(u32 index) +{ + u32 eax, edx; + + __asm__ __volatile__("xgetbv;" + : "=3Da" (eax), "=3Dd" (edx) + : "c" (index)); + return eax | ((u64)edx << 32); +} + +static inline void xsetbv(u32 index, u64 value) +{ + u32 eax =3D value; + u32 edx =3D value >> 32; + + __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); +} + static inline struct desc_ptr get_gdt(void) { struct desc_ptr gdt; diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/= selftests/kvm/x86_64/amx_test.c index 5c82d7e6f552..af1ef6f79d32 100644 --- a/tools/testing/selftests/kvm/x86_64/amx_test.c +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c @@ -65,24 +65,6 @@ struct xtile_info { =20 static struct xtile_info xtile; =20 -static inline u64 __xgetbv(u32 index) -{ - u32 eax, edx; - - asm volatile("xgetbv;" - : "=3Da" (eax), "=3Dd" (edx) - : "c" (index)); - return eax + ((u64)edx << 32); -} - -static inline void __xsetbv(u32 index, u64 value) -{ - u32 eax =3D value; - u32 edx =3D value >> 32; - - asm volatile("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); -} - static inline void __ldtilecfg(void *cfg) { asm volatile(".byte 0xc4,0xe2,0x78,0x49,0x00" @@ -160,10 +142,10 @@ static void init_regs(void) set_cr4(cr4); GUEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); =20 - xcr0 =3D __xgetbv(0); + xcr0 =3D xgetbv(0); xcr0 |=3D XFEATURE_MASK_XTILE; - __xsetbv(0x0, xcr0); - GUEST_ASSERT((__xgetbv(0) & XFEATURE_MASK_XTILE) =3D=3D XFEATURE_MASK_XTI= LE); + xsetbv(0x0, xcr0); + GUEST_ASSERT((xgetbv(0) & XFEATURE_MASK_XTILE) =3D=3D XFEATURE_MASK_XTILE= ); } =20 static void __attribute__((__flatten__)) guest_code(struct tile_config *am= x_cfg, --=20 2.40.0.348.gf938b09366-goog From nobody Wed Feb 11 06:53:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CB29C6FD1D for ; Wed, 5 Apr 2023 00:45:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236766AbjDEApr (ORCPT ); Tue, 4 Apr 2023 20:45:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236701AbjDEApd (ORCPT ); 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Tue, 04 Apr 2023 17:45:30 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 4 Apr 2023 17:45:18 -0700 In-Reply-To: <20230405004520.421768-1-seanjc@google.com> Mime-Version: 1.0 References: <20230405004520.421768-1-seanjc@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230405004520.421768-5-seanjc@google.com> Subject: [PATCH v4 4/6] KVM: selftests: Rework dynamic XFeature helper to take mask, not bit From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Lewis , Mingwei Zhang , Jim Mattson Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Take the XFeature mask in __vm_xsave_require_permission() instead of the bit so that there's no need to define macros for both the bit and the mask. Asserting that only a single bit is set and retrieving said bit is easy enough via log2 helpers. Opportunistically clean up the error message for the ARCH_REQ_XCOMP_GUEST_PERM sanity check. Signed-off-by: Sean Christopherson Reviewed-by: Aaron Lewis Tested-by: Aaron Lewis --- .../selftests/kvm/include/x86_64/processor.h | 6 +++--- .../selftests/kvm/lib/x86_64/processor.c | 17 ++++++++++------- tools/testing/selftests/kvm/x86_64/amx_test.c | 2 +- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index f6061fe7057f..41d798375570 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -1098,10 +1098,10 @@ uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, ui= nt64_t a1, uint64_t a2, uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1); void xen_hypercall(uint64_t nr, uint64_t a0, void *a1); =20 -void __vm_xsave_require_permission(int bit, const char *name); +void __vm_xsave_require_permission(uint64_t xfeature, const char *name); =20 -#define vm_xsave_require_permission(perm) \ - __vm_xsave_require_permission(perm, #perm) +#define vm_xsave_require_permission(xfeature) \ + __vm_xsave_require_permission(xfeature, #xfeature) =20 enum pg_level { PG_LEVEL_NONE, diff --git a/tools/testing/selftests/kvm/lib/x86_64/processor.c b/tools/tes= ting/selftests/kvm/lib/x86_64/processor.c index a12b21a2ef37..898b30096c80 100644 --- a/tools/testing/selftests/kvm/lib/x86_64/processor.c +++ b/tools/testing/selftests/kvm/lib/x86_64/processor.c @@ -697,7 +697,7 @@ uint64_t kvm_get_feature_msr(uint64_t msr_index) return buffer.entry.data; } =20 -void __vm_xsave_require_permission(int bit, const char *name) +void __vm_xsave_require_permission(uint64_t xfeature, const char *name) { int kvm_fd; u64 bitmask; @@ -705,12 +705,15 @@ void __vm_xsave_require_permission(int bit, const cha= r *name) struct kvm_device_attr attr =3D { .group =3D 0, .attr =3D KVM_X86_XCOMP_GUEST_SUPP, - .addr =3D (unsigned long) &bitmask + .addr =3D (unsigned long) &bitmask, }; =20 TEST_ASSERT(!kvm_supported_cpuid, "kvm_get_supported_cpuid() cannot be used before ARCH_REQ_XCOMP_GUES= T_PERM"); =20 + TEST_ASSERT(is_power_of_2(xfeature), + "Dynamic XFeatures must be enabled one at a time"); + kvm_fd =3D open_kvm_dev_path_or_exit(); rc =3D __kvm_ioctl(kvm_fd, KVM_GET_DEVICE_ATTR, &attr); close(kvm_fd); @@ -720,16 +723,16 @@ void __vm_xsave_require_permission(int bit, const cha= r *name) =20 TEST_ASSERT(rc =3D=3D 0, "KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP= ) error: %ld", rc); =20 - __TEST_REQUIRE(bitmask & (1ULL << bit), + __TEST_REQUIRE(bitmask & xfeature, "Required XSAVE feature '%s' not supported", name); =20 - TEST_REQUIRE(!syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit)); + TEST_REQUIRE(!syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, ilog2(xf= eature))); =20 rc =3D syscall(SYS_arch_prctl, ARCH_GET_XCOMP_GUEST_PERM, &bitmask); TEST_ASSERT(rc =3D=3D 0, "prctl(ARCH_GET_XCOMP_GUEST_PERM) error: %ld", r= c); - TEST_ASSERT(bitmask & (1ULL << bit), - "prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure bitmask=3D0x%lx", - bitmask); + TEST_ASSERT(bitmask & xfeature, + "'%s' (0x%lx) not permitted after prctl(ARCH_REQ_XCOMP_GUEST_PERM) p= errmited=3D0x%lx", + name, xfeature, bitmask); } =20 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid) diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/= selftests/kvm/x86_64/amx_test.c index af1ef6f79d32..a0f74f5121a6 100644 --- a/tools/testing/selftests/kvm/x86_64/amx_test.c +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c @@ -233,7 +233,7 @@ int main(int argc, char *argv[]) * Note, all off-by-default features must be enabled before anything * caches KVM_GET_SUPPORTED_CPUID, e.g. before using kvm_cpu_has(). */ - vm_xsave_require_permission(XSTATE_XTILE_DATA_BIT); + vm_xsave_require_permission(XFEATURE_MASK_XTILEDATA); =20 TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XFD)); TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XSAVE)); --=20 2.40.0.348.gf938b09366-goog From nobody Wed Feb 11 06:53:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76307C76188 for ; Wed, 5 Apr 2023 00:45:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236730AbjDEApv (ORCPT ); Tue, 4 Apr 2023 20:45:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236726AbjDEApj (ORCPT ); Tue, 4 Apr 2023 20:45:39 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD3BC423B for ; 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charset="utf-8" From: Aaron Lewis Add all known XFEATURE masks to processor.h to make them more broadly available in KVM selftests. Relocate and clean up the exiting AMX (XTILE) defines in processor.h, e.g. drop the intermediate define and use BIT_ULL. Signed-off-by: Aaron Lewis Signed-off-by: Sean Christopherson Reviewed-by: Aaron Lewis Tested-by: Aaron Lewis --- .../selftests/kvm/include/x86_64/processor.h | 25 ++++++++---- tools/testing/selftests/kvm/x86_64/amx_test.c | 38 ++++++++----------- 2 files changed, 33 insertions(+), 30 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index 41d798375570..187309f3e7e9 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -60,6 +60,23 @@ struct xstate { u8 extended_state_area[0]; } __attribute__ ((packed, aligned (64))); =20 +#define XFEATURE_MASK_FP BIT_ULL(0) +#define XFEATURE_MASK_SSE BIT_ULL(1) +#define XFEATURE_MASK_YMM BIT_ULL(2) +#define XFEATURE_MASK_BNDREGS BIT_ULL(3) +#define XFEATURE_MASK_BNDCSR BIT_ULL(4) +#define XFEATURE_MASK_OPMASK BIT_ULL(5) +#define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6) +#define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7) +#define XFEATURE_MASK_XTILE_CFG BIT_ULL(17) +#define XFEATURE_MASK_XTILE_DATA BIT_ULL(18) + +#define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \ + XFEATURE_MASK_ZMM_Hi256 | \ + XFEATURE_MASK_Hi16_ZMM) +#define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA | \ + XFEATURE_MASK_XTILE_CFG) + /* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww.= */ enum cpuid_output_regs { KVM_CPUID_EAX, @@ -1138,14 +1155,6 @@ void virt_map_level(struct kvm_vm *vm, uint64_t vadd= r, uint64_t paddr, #define X86_CR0_CD (1UL<<30) /* Cache Disable */ #define X86_CR0_PG (1UL<<31) /* Paging */ =20 -#define XSTATE_XTILE_CFG_BIT 17 -#define XSTATE_XTILE_DATA_BIT 18 - -#define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT) -#define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT) -#define XFEATURE_XTILE_MASK (XSTATE_XTILE_CFG_MASK | \ - XSTATE_XTILE_DATA_MASK) - #define PFERR_PRESENT_BIT 0 #define PFERR_WRITE_BIT 1 #define PFERR_USER_BIT 2 diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/= selftests/kvm/x86_64/amx_test.c index a0f74f5121a6..11329e5ff945 100644 --- a/tools/testing/selftests/kvm/x86_64/amx_test.c +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c @@ -34,12 +34,6 @@ #define MAX_TILES 16 #define RESERVED_BYTES 14 =20 -#define XFEATURE_XTILECFG 17 -#define XFEATURE_XTILEDATA 18 -#define XFEATURE_MASK_XTILECFG (1 << XFEATURE_XTILECFG) -#define XFEATURE_MASK_XTILEDATA (1 << XFEATURE_XTILEDATA) -#define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILECFG | XFEATURE_MASK_XTILE= DATA) - #define XSAVE_HDR_OFFSET 512 =20 struct tile_config { @@ -172,25 +166,25 @@ static void __attribute__((__flatten__)) guest_code(s= truct tile_config *amx_cfg, * After XSAVEC, XTILEDATA is cleared in the xstate_bv but is set in * the xcomp_bv. */ - xstate->header.xstate_bv =3D XFEATURE_MASK_XTILEDATA; - __xsavec(xstate, XFEATURE_MASK_XTILEDATA); - GUEST_ASSERT(!(xstate->header.xstate_bv & XFEATURE_MASK_XTILEDATA)); - GUEST_ASSERT(xstate->header.xcomp_bv & XFEATURE_MASK_XTILEDATA); + xstate->header.xstate_bv =3D XFEATURE_MASK_XTILE_DATA; + __xsavec(xstate, XFEATURE_MASK_XTILE_DATA); + GUEST_ASSERT(!(xstate->header.xstate_bv & XFEATURE_MASK_XTILE_DATA)); + GUEST_ASSERT(xstate->header.xcomp_bv & XFEATURE_MASK_XTILE_DATA); =20 /* xfd=3D0x40000, disable amx tiledata */ - wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILEDATA); + wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILE_DATA); =20 /* * XTILEDATA is cleared in xstate_bv but set in xcomp_bv, this property * remains the same even when amx tiledata is disabled by IA32_XFD. */ - xstate->header.xstate_bv =3D XFEATURE_MASK_XTILEDATA; - __xsavec(xstate, XFEATURE_MASK_XTILEDATA); - GUEST_ASSERT(!(xstate->header.xstate_bv & XFEATURE_MASK_XTILEDATA)); - GUEST_ASSERT((xstate->header.xcomp_bv & XFEATURE_MASK_XTILEDATA)); + xstate->header.xstate_bv =3D XFEATURE_MASK_XTILE_DATA; + __xsavec(xstate, XFEATURE_MASK_XTILE_DATA); + GUEST_ASSERT(!(xstate->header.xstate_bv & XFEATURE_MASK_XTILE_DATA)); + GUEST_ASSERT((xstate->header.xcomp_bv & XFEATURE_MASK_XTILE_DATA)); =20 GUEST_SYNC(6); - GUEST_ASSERT(rdmsr(MSR_IA32_XFD) =3D=3D XFEATURE_MASK_XTILEDATA); + GUEST_ASSERT(rdmsr(MSR_IA32_XFD) =3D=3D XFEATURE_MASK_XTILE_DATA); set_tilecfg(amx_cfg); __ldtilecfg(amx_cfg); /* Trigger #NM exception */ @@ -202,14 +196,14 @@ static void __attribute__((__flatten__)) guest_code(s= truct tile_config *amx_cfg, =20 void guest_nm_handler(struct ex_regs *regs) { - /* Check if #NM is triggered by XFEATURE_MASK_XTILEDATA */ + /* Check if #NM is triggered by XFEATURE_MASK_XTILE_DATA */ GUEST_SYNC(7); GUEST_ASSERT(!(get_cr0() & X86_CR0_TS)); - GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) =3D=3D XFEATURE_MASK_XTILEDATA); - GUEST_ASSERT(rdmsr(MSR_IA32_XFD) =3D=3D XFEATURE_MASK_XTILEDATA); + GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) =3D=3D XFEATURE_MASK_XTILE_DATA); + GUEST_ASSERT(rdmsr(MSR_IA32_XFD) =3D=3D XFEATURE_MASK_XTILE_DATA); GUEST_SYNC(8); - GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) =3D=3D XFEATURE_MASK_XTILEDATA); - GUEST_ASSERT(rdmsr(MSR_IA32_XFD) =3D=3D XFEATURE_MASK_XTILEDATA); + GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) =3D=3D XFEATURE_MASK_XTILE_DATA); + GUEST_ASSERT(rdmsr(MSR_IA32_XFD) =3D=3D XFEATURE_MASK_XTILE_DATA); /* Clear xfd_err */ wrmsr(MSR_IA32_XFD_ERR, 0); /* xfd=3D0, enable amx */ @@ -233,7 +227,7 @@ int main(int argc, char *argv[]) * Note, all off-by-default features must be enabled before anything * caches KVM_GET_SUPPORTED_CPUID, e.g. before using kvm_cpu_has(). */ - vm_xsave_require_permission(XFEATURE_MASK_XTILEDATA); + vm_xsave_require_permission(XFEATURE_MASK_XTILE_DATA); =20 TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XFD)); TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XSAVE)); --=20 2.40.0.348.gf938b09366-goog From nobody Wed Feb 11 06:53:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED417C6FD1D for ; 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Tue, 04 Apr 2023 17:45:33 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 4 Apr 2023 17:45:20 -0700 In-Reply-To: <20230405004520.421768-1-seanjc@google.com> Mime-Version: 1.0 References: <20230405004520.421768-1-seanjc@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230405004520.421768-7-seanjc@google.com> Subject: [PATCH v4 6/6] KVM: selftests: Add test to verify KVM's supported XCR0 From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Lewis , Mingwei Zhang , Jim Mattson Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aaron Lewis Check both architectural rules and KVM's ABI for KVM_GET_SUPPORTED_CPUID to ensure the supported xfeatures[1] don't violate any of them. The architectural rules[2] and KVM's contract with userspace ensure for a given feature, e.g. sse, avx, amx, etc... their associated xfeatures are either all sets or none of them are set, and any dependencies are enabled if needed. [1] EDX:EAX of CPUID.(EAX=3D0DH,ECX=3D0) [2] SDM vol 1, 13.3 ENABLING THE XSAVE FEATURE SET AND XSAVE-ENABLED FEATURES Cc: Mingwei Zhang Signed-off-by: Aaron Lewis [sean: expand comments, use a fancy X86_PROPERTY] Signed-off-by: Sean Christopherson Reviewed-by: Aaron Lewis Tested-by: Aaron Lewis --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/include/x86_64/processor.h | 20 +++ .../selftests/kvm/x86_64/xcr0_cpuid_test.c | 132 ++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 tools/testing/selftests/kvm/x86_64/xcr0_cpuid_test.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests= /kvm/Makefile index 84a627c43795..18cadc669798 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -105,6 +105,7 @@ TEST_GEN_PROGS_x86_64 +=3D x86_64/vmx_tsc_adjust_test TEST_GEN_PROGS_x86_64 +=3D x86_64/vmx_nested_tsc_scaling_test TEST_GEN_PROGS_x86_64 +=3D x86_64/xapic_ipi_test TEST_GEN_PROGS_x86_64 +=3D x86_64/xapic_state_test +TEST_GEN_PROGS_x86_64 +=3D x86_64/xcr0_cpuid_test TEST_GEN_PROGS_x86_64 +=3D x86_64/xss_msr_test TEST_GEN_PROGS_x86_64 +=3D x86_64/debug_regs TEST_GEN_PROGS_x86_64 +=3D x86_64/tsc_msrs_test diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index 187309f3e7e9..70c5469e4023 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -241,8 +241,11 @@ struct kvm_x86_cpu_property { #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX,= 8, 15) #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0= , EAX, 24, 31) =20 +#define X86_PROPERTY_SUPPORTED_XCR0_LO KVM_X86_CPU_PROPERTY(0xd, 0, EAX,= 0, 31) #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EB= X, 0, 31) #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, = 0, 31) +#define X86_PROPERTY_SUPPORTED_XCR0_HI KVM_X86_CPU_PROPERTY(0xd, 0, EDX,= 0, 31) + #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, = 0, 31) #define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX= , 0, 31) #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES KVM_X86_CPU_PROPERTY(0x1d, 0, = EAX, 0, 31) @@ -681,6 +684,15 @@ static inline bool this_pmu_has(struct kvm_x86_pmu_fea= ture feature) !this_cpu_has(feature.anti_feature); } =20 +static __always_inline uint64_t this_cpu_supported_xcr0(void) +{ + if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) + return 0; + + return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | + ((uint64_t)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32= ); +} + typedef u32 __attribute__((vector_size(16))) sse128_t; #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; } #define sse128_lo(x) ({ __sse128_u t; t.vec =3D x; t.as_u64[0]; }) @@ -1104,6 +1116,14 @@ static inline uint8_t wrmsr_safe(uint32_t msr, uint6= 4_t val) return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr)); } =20 +static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value) +{ + u32 eax =3D value; + u32 edx =3D value >> 32; + + return kvm_asm_safe("xsetbv", "a" (eax), "d" (edx), "c" (index)); +} + bool kvm_is_tdp_enabled(void); =20 uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr, diff --git a/tools/testing/selftests/kvm/x86_64/xcr0_cpuid_test.c b/tools/t= esting/selftests/kvm/x86_64/xcr0_cpuid_test.c new file mode 100644 index 000000000000..905bd5ae4431 --- /dev/null +++ b/tools/testing/selftests/kvm/x86_64/xcr0_cpuid_test.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * XCR0 cpuid test + * + * Copyright (C) 2022, Google LLC. + */ + +#include +#include +#include +#include +#include + +#include "test_util.h" + +#include "kvm_util.h" +#include "processor.h" + +/* + * Assert that architectural dependency rules are satisfied, e.g. that AVX= is + * supported if and only if SSE is supported. + */ +#define ASSERT_XFEATURE_DEPENDENCIES(supported_xcr0, xfeatures, dependenci= es) \ +do { \ + uint64_t __supported =3D (supported_xcr0) & ((xfeatures) | (dependencies)= ); \ + \ + GUEST_ASSERT_3((__supported & (xfeatures)) !=3D (xfeatures) || \ + __supported =3D=3D ((xfeatures) | (dependencies)), \ + __supported, (xfeatures), (dependencies)); \ +} while (0) + +/* + * Assert that KVM reports a sane, usable as-is XCR0. Architecturally, a = CPU + * isn't strictly required to _support_ all XFeatures related to a feature= , but + * at the same time XSETBV will #GP if bundled XFeatures aren't enabled and + * disabled coherently. E.g. a CPU can technically enumerate supported for + * XTILE_CFG but not XTILE_DATA, but attempting to enable XTILE_CFG without + * XTILE_DATA will #GP. + */ +#define ASSERT_ALL_OR_NONE_XFEATURE(supported_xcr0, xfeatures) \ +do { \ + uint64_t __supported =3D (supported_xcr0) & (xfeatures); \ + \ + GUEST_ASSERT_2(!__supported || __supported =3D=3D (xfeatures), \ + __supported, (xfeatures)); \ +} while (0) + +static void guest_code(void) +{ + uint64_t xcr0_reset; + uint64_t supported_xcr0; + int i, vector; + + set_cr4(get_cr4() | X86_CR4_OSXSAVE); + + xcr0_reset =3D xgetbv(0); + supported_xcr0 =3D this_cpu_supported_xcr0(); + + GUEST_ASSERT(xcr0_reset =3D=3D XFEATURE_MASK_FP); + + /* Check AVX */ + ASSERT_XFEATURE_DEPENDENCIES(supported_xcr0, + XFEATURE_MASK_YMM, + XFEATURE_MASK_SSE); + + /* Check MPX */ + ASSERT_ALL_OR_NONE_XFEATURE(supported_xcr0, + XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR); + + /* Check AVX-512 */ + ASSERT_XFEATURE_DEPENDENCIES(supported_xcr0, + XFEATURE_MASK_AVX512, + XFEATURE_MASK_SSE | XFEATURE_MASK_YMM); + ASSERT_ALL_OR_NONE_XFEATURE(supported_xcr0, + XFEATURE_MASK_AVX512); + + /* Check AMX */ + ASSERT_ALL_OR_NONE_XFEATURE(supported_xcr0, + XFEATURE_MASK_XTILE); + + vector =3D xsetbv_safe(0, supported_xcr0); + GUEST_ASSERT_2(!vector, supported_xcr0, vector); + + for (i =3D 0; i < 64; i++) { + if (supported_xcr0 & BIT_ULL(i)) + continue; + + vector =3D xsetbv_safe(0, supported_xcr0 | BIT_ULL(i)); + GUEST_ASSERT_3(vector =3D=3D GP_VECTOR, supported_xcr0, vector, BIT_ULL(= i)); + } + + GUEST_DONE(); +} + +int main(int argc, char *argv[]) +{ + struct kvm_vcpu *vcpu; + struct kvm_run *run; + struct kvm_vm *vm; + struct ucall uc; + + TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XSAVE)); + + vm =3D vm_create_with_one_vcpu(&vcpu, guest_code); + run =3D vcpu->run; + + vm_init_descriptor_tables(vm); + vcpu_init_descriptor_tables(vcpu); + + while (1) { + vcpu_run(vcpu); + + TEST_ASSERT(run->exit_reason =3D=3D KVM_EXIT_IO, + "Unexpected exit reason: %u (%s),\n", + run->exit_reason, + exit_reason_str(run->exit_reason)); + + switch (get_ucall(vcpu, &uc)) { + case UCALL_ABORT: + REPORT_GUEST_ASSERT_3(uc, "0x%lx 0x%lx 0x%lx"); + break; + case UCALL_DONE: + goto done; + default: + TEST_FAIL("Unknown ucall %lu", uc.cmd); + } + } + +done: + kvm_vm_free(vm); + return 0; +} --=20 2.40.0.348.gf938b09366-goog