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charset="utf-8" When multiple channels operate simultaneously, the common register shared by all channels could be set to an unexpected value due to race conditions on SMP machines, resulting in a disaster that DMAC cannot work from then on: cpu0 cpu1 dw_axi_dma_interrupt() axi_dma_irq_disable(chip) ... axi_chan_block_xfer_start() axi_dma_enable() val =3D axi_dma_ioread32(chip, DMAC_CFG) axi_dma_irq_enable(chip) axi_dma_iowrite32(chip, DMAC_CFG, val) As a result, the global interrupt enable bit INT_EN in the DMAC_CFG register is eventually cleared and the DMAC will no longer generates interrupts. The error scenario is as follows: [ 63.483688] dmatest: dma0chan1-copy: result #18: 'test timed out' with src_off=3D0xc2 dst_off=3D0x27b len=3D0x3a54 (0) [ 63.483693] dmatest: dma0chan2-copy: result #18: 'test timed out' with src_off=3D0x239 dst_off=3D0xfc9 len=3D0x213a (0) [ 63.483696] dmatest: dma0chan0-copy: result #19: 'test timed out' with src_off=3D0x5d1 dst_off=3D0x231 len=3D0x395e (0) a spinlock is added to fix it up. Signed-off-by: Libing Lei --- Changes since v2: - fix commit message Changes since v1: - an example and more description for this patch --- .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 20 +++++++++++++++++++ drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 + 2 files changed, 21 insertions(+) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/d= w-axi-dmac/dw-axi-dmac-platform.c index bf85aa097..7aa53293c 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -108,37 +108,49 @@ static inline void axi_chan_config_write(struct axi_d= ma_chan *chan, static inline void axi_dma_disable(struct axi_dma_chip *chip) { u32 val; + unsigned long flags; =20 + spin_lock_irqsave(&chip->lock, flags); val =3D axi_dma_ioread32(chip, DMAC_CFG); val &=3D ~DMAC_EN_MASK; axi_dma_iowrite32(chip, DMAC_CFG, val); + spin_unlock_irqrestore(&chip->lock, flags); } =20 static inline void axi_dma_enable(struct axi_dma_chip *chip) { u32 val; + unsigned long flags; =20 + spin_lock_irqsave(&chip->lock, flags); val =3D axi_dma_ioread32(chip, DMAC_CFG); val |=3D DMAC_EN_MASK; axi_dma_iowrite32(chip, DMAC_CFG, val); + spin_unlock_irqrestore(&chip->lock, flags); } =20 static inline void axi_dma_irq_disable(struct axi_dma_chip *chip) { u32 val; + unsigned long flags; =20 + spin_lock_irqsave(&chip->lock, flags); val =3D axi_dma_ioread32(chip, DMAC_CFG); val &=3D ~INT_EN_MASK; axi_dma_iowrite32(chip, DMAC_CFG, val); + spin_unlock_irqrestore(&chip->lock, flags); } =20 static inline void axi_dma_irq_enable(struct axi_dma_chip *chip) { u32 val; + unsigned long flags; =20 + spin_lock_irqsave(&chip->lock, flags); val =3D axi_dma_ioread32(chip, DMAC_CFG); val |=3D INT_EN_MASK; axi_dma_iowrite32(chip, DMAC_CFG, val); + spin_unlock_irqrestore(&chip->lock, flags); } =20 static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq= _mask) @@ -177,7 +189,9 @@ static inline u32 axi_chan_irq_read(struct axi_dma_chan= *chan) static inline void axi_chan_disable(struct axi_dma_chan *chan) { u32 val; + unsigned long flags; =20 + spin_lock_irqsave(&chan->chip->lock, flags); val =3D axi_dma_ioread32(chan->chip, DMAC_CHEN); val &=3D ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT); if (chan->chip->dw->hdata->reg_map_8_channels) @@ -185,12 +199,15 @@ static inline void axi_chan_disable(struct axi_dma_ch= an *chan) else val |=3D BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT; axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); + spin_unlock_irqrestore(&chan->chip->lock, flags); } =20 static inline void axi_chan_enable(struct axi_dma_chan *chan) { u32 val; + unsigned long flags; =20 + spin_lock_irqsave(&chan->chip->lock, flags); val =3D axi_dma_ioread32(chan->chip, DMAC_CHEN); if (chan->chip->dw->hdata->reg_map_8_channels) val |=3D BIT(chan->id) << DMAC_CHAN_EN_SHIFT | @@ -199,6 +216,7 @@ static inline void axi_chan_enable(struct axi_dma_chan = *chan) val |=3D BIT(chan->id) << DMAC_CHAN_EN_SHIFT | BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT; axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); + spin_unlock_irqrestore(&chan->chip->lock, flags); } =20 static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan) @@ -1420,6 +1438,8 @@ static int dw_probe(struct platform_device *pdev) if (ret) return ret; =20 + spin_lock_init(&chip->lock); + dw->chan =3D devm_kcalloc(chip->dev, hdata->nr_channels, sizeof(*dw->chan), GFP_KERNEL); if (!dw->chan) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dma= c/dw-axi-dmac.h index e9d5eb0fd..4a8db437e 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -70,6 +70,7 @@ struct axi_dma_chip { struct clk *core_clk; struct clk *cfgr_clk; struct dw_axi_dma *dw; + spinlock_t lock; }; =20 /* LLI =3D=3D Linked List Item */ --=20 2.17.1