From nobody Sun Sep 14 01:59:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CB03C77B60 for ; Tue, 4 Apr 2023 15:36:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235809AbjDDPg2 (ORCPT ); Tue, 4 Apr 2023 11:36:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235693AbjDDPgL (ORCPT ); Tue, 4 Apr 2023 11:36:11 -0400 Received: from mail-oi1-x22b.google.com (mail-oi1-x22b.google.com [IPv6:2607:f8b0:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A8B84ED0 for ; Tue, 4 Apr 2023 08:35:52 -0700 (PDT) Received: by mail-oi1-x22b.google.com with SMTP id b19so24498434oib.7 for ; Tue, 04 Apr 2023 08:35:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680622552; x=1683214552; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YI338JaQ174nkLqVWr+V6SK8k3Md0go2Oy6ecZq7aOE=; b=cZufMmezK/J3K5t1K+9nvjGAxjSo3wsUgZD4EzIcvmpax4PAxS5DtiHA6Zd6IEZZzY UYym8zYFUa7q2J1DFOBna6w6ggsJI0+T4lnTdz8sJ76K8L0sL+zQ1vNdevrbHTEwF9fp TZsUpuryPx7vSfbyq87QJhRkNeaj/QOP1FoxGZ65ekIZi9M1HKYQR9qgQGp0ZNZHYlHl jUqNOftXtguXH3FWz6W3NSo/UuuTnqSAo8mNpZmcGn01Epo6otC/lXdus4pbEFrXcvWv 6zc4aoygOROkx9s/00XhvfrXeUth6pSiFtnruhCTW8WJaCvkVTB878T9xuftCfRxD5mk BY4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680622552; x=1683214552; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YI338JaQ174nkLqVWr+V6SK8k3Md0go2Oy6ecZq7aOE=; b=sLjII/SPU1WlQK14BqtZva8Jx7ejXiKS34C8nbA4xahQkcR6vWcJ071mcnB3UHmkd5 BxjVVcihcQn5uN1Cfo112gZT8iAE9zwlTtES6h/35nC+XYkzf0ZqQbAr52NXtuYHwFxp 4DVGAfqLFMVplfMJzT+uEn2vEJfRnPWTSOUTN669vxoEUxenA3H5UXlCt23Hg/6anvbz TMmFu13yW9GCltmLVXYB48O2cabO5OfXT/JS2eAmVgVFMcCbAmCMt9KEPmXtYY7I3yAs e+5gGQd8XlyNMUT6tq3HtExemvawqk8DlwAaCNpt5j6rgf7QLJGwJrugHDGzO1PYfDQu lvng== X-Gm-Message-State: AAQBX9cjw+DNZBN7yktS4NVvaYNT1VjG9+m+6I2uxufImbpQmJKilmSS RX2bHDeyhpXPBzmzoSAtT0x1CA== X-Google-Smtp-Source: AKy350Y7jOZU2sRY4GBAOKv6/kTq0ePgKeNcDBlKsSNcfhN1N2WnXjQtQ35toFLBayQrNm19871UCA== X-Received: by 2002:a05:6808:d49:b0:389:4bc5:8094 with SMTP id w9-20020a0568080d4900b003894bc58094mr12549130oik.3.1680622551730; Tue, 04 Apr 2023 08:35:51 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w124-20020acadf82000000b00387384dc768sm5325803oig.9.2023.04.04.08.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Apr 2023 08:35:51 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 7/9] RISC-V: KVM: Use bitmap for irqs_pending and irqs_pending_mask Date: Tue, 4 Apr 2023 21:04:50 +0530 Message-Id: <20230404153452.2405681-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230404153452.2405681-1-apatel@ventanamicro.com> References: <20230404153452.2405681-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To support 64 VCPU local interrupts on RV32 host, we should use bitmap for irqs_pending and irqs_pending_mask in struct kvm_vcpu_arch. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_host.h | 7 ++-- arch/riscv/kvm/vcpu.c | 53 ++++++++++++++++++++----------- 2 files changed, 38 insertions(+), 22 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 3157cf748df1..ee0acccb1d3b 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -204,8 +204,9 @@ struct kvm_vcpu_arch { * in irqs_pending. Our approach is modeled around multiple producer * and single consumer problem where the consumer is the VCPU itself. */ - unsigned long irqs_pending; - unsigned long irqs_pending_mask; +#define KVM_RISCV_VCPU_NR_IRQS 64 + DECLARE_BITMAP(irqs_pending, KVM_RISCV_VCPU_NR_IRQS); + DECLARE_BITMAP(irqs_pending_mask, KVM_RISCV_VCPU_NR_IRQS); =20 /* VCPU Timer */ struct kvm_vcpu_timer timer; @@ -334,7 +335,7 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu,= unsigned int irq); int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq= ); void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu); -bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long ma= sk); +bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, u64 mask); void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); =20 diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 57bdbfc17d48..811c7e9a308c 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -141,8 +141,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) =20 kvm_riscv_vcpu_aia_reset(vcpu); =20 - WRITE_ONCE(vcpu->arch.irqs_pending, 0); - WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); + bitmap_zero(vcpu->arch.irqs_pending, KVM_RISCV_VCPU_NR_IRQS); + bitmap_zero(vcpu->arch.irqs_pending_mask, KVM_RISCV_VCPU_NR_IRQS); =20 kvm_riscv_vcpu_pmu_reset(vcpu); =20 @@ -474,6 +474,7 @@ static int kvm_riscv_vcpu_general_get_csr(struct kvm_vc= pu *vcpu, if (reg_num =3D=3D KVM_REG_RISCV_CSR_REG(sip)) { kvm_riscv_vcpu_flush_interrupts(vcpu); *out_val =3D (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK; + *out_val |=3D csr->hvip & ~IRQ_LOCAL_MASK; } else *out_val =3D ((unsigned long *)csr)[reg_num]; =20 @@ -497,7 +498,7 @@ static inline int kvm_riscv_vcpu_general_set_csr(struct= kvm_vcpu *vcpu, ((unsigned long *)csr)[reg_num] =3D reg_val; =20 if (reg_num =3D=3D KVM_REG_RISCV_CSR_REG(sip)) - WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); + WRITE_ONCE(vcpu->arch.irqs_pending_mask[0], 0); =20 return 0; } @@ -799,9 +800,9 @@ void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *v= cpu) struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; unsigned long mask, val; =20 - if (READ_ONCE(vcpu->arch.irqs_pending_mask)) { - mask =3D xchg_acquire(&vcpu->arch.irqs_pending_mask, 0); - val =3D READ_ONCE(vcpu->arch.irqs_pending) & mask; + if (READ_ONCE(vcpu->arch.irqs_pending_mask[0])) { + mask =3D xchg_acquire(&vcpu->arch.irqs_pending_mask[0], 0); + val =3D READ_ONCE(vcpu->arch.irqs_pending[0]) & mask; =20 csr->hvip &=3D ~mask; csr->hvip |=3D val; @@ -825,12 +826,12 @@ void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *= vcpu) if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) { if (hvip & (1UL << IRQ_VS_SOFT)) { if (!test_and_set_bit(IRQ_VS_SOFT, - &v->irqs_pending_mask)) - set_bit(IRQ_VS_SOFT, &v->irqs_pending); + v->irqs_pending_mask)) + set_bit(IRQ_VS_SOFT, v->irqs_pending); } else { if (!test_and_set_bit(IRQ_VS_SOFT, - &v->irqs_pending_mask)) - clear_bit(IRQ_VS_SOFT, &v->irqs_pending); + v->irqs_pending_mask)) + clear_bit(IRQ_VS_SOFT, v->irqs_pending); } } =20 @@ -843,14 +844,20 @@ void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *= vcpu) =20 int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) { - if (irq !=3D IRQ_VS_SOFT && + /* + * We only allow VS-mode software, timer, and external + * interrupts when irq is one of the local interrupts + * defined by RISC-V privilege specification. + */ + if (irq < IRQ_LOCAL_MAX && + irq !=3D IRQ_VS_SOFT && irq !=3D IRQ_VS_TIMER && irq !=3D IRQ_VS_EXT) return -EINVAL; =20 - set_bit(irq, &vcpu->arch.irqs_pending); + set_bit(irq, vcpu->arch.irqs_pending); smp_mb__before_atomic(); - set_bit(irq, &vcpu->arch.irqs_pending_mask); + set_bit(irq, vcpu->arch.irqs_pending_mask); =20 kvm_vcpu_kick(vcpu); =20 @@ -859,25 +866,33 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcp= u, unsigned int irq) =20 int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) { - if (irq !=3D IRQ_VS_SOFT && + /* + * We only allow VS-mode software, timer, and external + * interrupts when irq is one of the local interrupts + * defined by RISC-V privilege specification. + */ + if (irq < IRQ_LOCAL_MAX && + irq !=3D IRQ_VS_SOFT && irq !=3D IRQ_VS_TIMER && irq !=3D IRQ_VS_EXT) return -EINVAL; =20 - clear_bit(irq, &vcpu->arch.irqs_pending); + clear_bit(irq, vcpu->arch.irqs_pending); smp_mb__before_atomic(); - set_bit(irq, &vcpu->arch.irqs_pending_mask); + set_bit(irq, vcpu->arch.irqs_pending_mask); =20 return 0; } =20 -bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long ma= sk) +bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, u64 mask) { unsigned long ie; =20 ie =3D ((vcpu->arch.guest_csr.vsie & VSIP_VALID_MASK) - << VSIP_TO_HVIP_SHIFT) & mask; - if (READ_ONCE(vcpu->arch.irqs_pending) & ie) + << VSIP_TO_HVIP_SHIFT) & (unsigned long)mask; + ie |=3D vcpu->arch.guest_csr.vsie & ~IRQ_LOCAL_MASK & + (unsigned long)mask; + if (READ_ONCE(vcpu->arch.irqs_pending[0]) & ie) return true; =20 /* Check AIA high interrupts */ --=20 2.34.1