From nobody Wed Feb 11 04:18:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6E60C761A6 for ; Tue, 4 Apr 2023 08:25:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234208AbjDDIZW (ORCPT ); Tue, 4 Apr 2023 04:25:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234166AbjDDIZJ (ORCPT ); Tue, 4 Apr 2023 04:25:09 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82DE21BE8; Tue, 4 Apr 2023 01:25:04 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id cn12so127310846edb.4; Tue, 04 Apr 2023 01:25:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680596703; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H9JMZo+h1Q4ZjhPYRd6OF+eR14aI4rNR3ktfkwOViXk=; b=eKcMH3SCK/MbvXuG3s2Ev/t/hq1VBjng1BsNbovjdYDzWxmh5EvfFbpoGhQSkIs7zd KM9qQGv9dmQ07lGLewPyudXrdyFruzXwvpI2vGdfLjgflmsAhE9oNVznVCB9CjjkQo+X Mvl6VslYs4Yysi7O6tvayCT3OHbAor2EBVaajWAaOf5G7tIlXK9aR69Q9HIkROmcmszi 7zzlVzO+JIbwT4BvHoDFDugx8swq7vYbahcdtmjJ5bjKKkisKjwDcLnCpGfx8mUN6AKH tkoUdxWjKem1Qh8D9bT9a0O9XjT60QV/3PfPJ/36oYkEJ4TQpRYO7tupUgtXLySFhlPU PcNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680596703; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H9JMZo+h1Q4ZjhPYRd6OF+eR14aI4rNR3ktfkwOViXk=; b=mWyomXZOFrqYZrKDrynJYi2MIJzXfU4QwNyzF2S+3SG/4Lhel2EFEoTOHhZvbhhDkw RwoFewucREhBFY2gs+9Jo2Fly/TK7bHpvgYdD4fVmbdVVdB/ddlZ/+MLERWHS6wJ/4V0 LnYPaYrdgX1r1mevJbTqQHUzkrdhZg5kv9soN0RrIGEr2rratT41GnlsaZLZgK4dHtfL 3XhzblGspXrFS6EifeK5rRLfKZjO0yyAIVwcAwi//K/2l44vVwffzlK47s5iBpWqxl25 6jWcsF8V4u9fkVFGCzGpzJJSvDUQCjDwrYQkAjfDuftr9N32BsWX021N4ojnR5BqbcHR KfoQ== X-Gm-Message-State: AAQBX9eipWwl+B+uOKwfI73rvtOIotV8xeuYyfAXaTTfz+vFDc9DodoG FR5aeUWBYRtfWpe+JQ4fmaI= X-Google-Smtp-Source: AKy350Ys42q5uri8bicxqR0N3cA43deEBD9IDcrI3QZ/WfiFn0XzrsmaOfX3iP+K1xydrcXYHOvJtg== X-Received: by 2002:a17:906:f29a:b0:933:816c:abb9 with SMTP id gu26-20020a170906f29a00b00933816cabb9mr18076043ejb.36.1680596703038; Tue, 04 Apr 2023 01:25:03 -0700 (PDT) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id s5-20020a170906454500b008e54ac90de1sm5640652ejq.74.2023.04.04.01.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Apr 2023 01:25:02 -0700 (PDT) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: damien.lemoal@opensource.wdc.com, xxm@rock-chips.com, Rick Wertenbroek , stable@vger.kernel.org, Shawn Lin , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Johan Jonker , Brian Norris , Caleb Connolly , Corentin Labbe , Judy Hsiao , Sascha Hauer , Lin Huang , Arnaud Ferraris , Hugh Cole-Baker , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 02/11] PCI: rockchip: Write PCI Device ID to correct register Date: Tue, 4 Apr 2023 10:24:15 +0200 Message-Id: <20230404082426.3880812-3-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230404082426.3880812-1-rick.wertenbroek@gmail.com> References: <20230404082426.3880812-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Write PCI Device ID (DID) to the correct register. The Device ID was not updated through the correct register. Device ID was written to a read-only register and therefore did not work. The Device ID is now set through the correct register. This is documented in the RK3399 TRM section 17.6.6.1.1 Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe contro= ller") Cc: stable@vger.kernel.org Signed-off-by: Rick Wertenbroek Reviewed-by: Damien Le Moal Tested-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 6 ++++-- drivers/pci/controller/pcie-rockchip.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/contro= ller/pcie-rockchip-ep.c index d5c477020417..9b835377bd9e 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -115,6 +115,7 @@ static void rockchip_pcie_prog_ep_ob_atu(struct rockchi= p_pcie *rockchip, u8 fn, static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vf= n, struct pci_epf_header *hdr) { + u32 reg; struct rockchip_pcie_ep *ep =3D epc_get_drvdata(epc); struct rockchip_pcie *rockchip =3D &ep->rockchip; =20 @@ -127,8 +128,9 @@ static int rockchip_pcie_ep_write_header(struct pci_epc= *epc, u8 fn, u8 vfn, PCIE_CORE_CONFIG_VENDOR); } =20 - rockchip_pcie_write(rockchip, hdr->deviceid << 16, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); + reg =3D rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID); + reg =3D (reg & 0xFFFF) | (hdr->deviceid << 16); + rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID); =20 rockchip_pcie_write(rockchip, hdr->revid | diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controlle= r/pcie-rockchip.h index 32c3a859c26b..51a123e5c0cf 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -133,6 +133,8 @@ #define PCIE_RC_RP_ATS_BASE 0x400000 #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 #define PCIE_RC_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 --=20 2.25.1