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[72.137.118.218]) by smtp.gmail.com with ESMTPSA id v6-20020ad45346000000b005e231177992sm2670207qvs.74.2023.04.03.16.18.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 16:18:13 -0700 (PDT) From: Radu Rendec To: linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Pierre Gondois , Sudeep Holla , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/2] cacheinfo: Add arch specific early level initializer Date: Mon, 3 Apr 2023 19:15:50 -0400 Message-Id: <20230403231551.1090704-2-rrendec@redhat.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230403231551.1090704-1-rrendec@redhat.com> References: <20230403231551.1090704-1-rrendec@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch gives of architecture specific code the ability to initialize the cache level and allocate cacheinfo memory early, when cache level initialization runs on the primary CPU for all possible CPUs. This is part of a patch series that attempts to further the work in commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary CPU"). Previously, in the absence of any DT/ACPI cache info, architecture specific cache detection and info allocation for secondary CPUs would happen in non-preemptible context during early CPU initialization and trigger a "BUG: sleeping function called from invalid context" splat on an RT kernel. More specifically, this patch adds the early_cache_level() function, which is called by fetch_cache_info() as a fallback when the number of cache leaves cannot be extracted from DT/ACPI. In the default generic (weak) implementation, this new function returns -ENOENT, which preserves the original behavior for architectures that do not implement the function. Since early detection can get the number of cache leaves wrong in some cases*, additional logic is added to still call init_cache_level() later on the secondary CPU, therefore giving the architecture specific code an opportunity to go back and fix the initial guess. Again, the original behavior is preserved for architectures that do not implement the new function. * For example, on arm64, CLIDR_EL1 detection works only when it runs on the current CPU. In other words, a CPU cannot detect the cache depth for any other CPU than itself. Signed-off-by: Radu Rendec --- drivers/base/cacheinfo.c | 57 ++++++++++++++++++++++++++------------- include/linux/cacheinfo.h | 2 ++ 2 files changed, 40 insertions(+), 19 deletions(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index f6573c335f4c..7f8ac0cb549f 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -398,6 +398,11 @@ static void free_cache_attributes(unsigned int cpu) cache_shared_cpu_map_remove(cpu); } =20 +int __weak early_cache_level(unsigned int cpu) +{ + return -ENOENT; +} + int __weak init_cache_level(unsigned int cpu) { return -ENOENT; @@ -423,51 +428,65 @@ int allocate_cache_info(int cpu) =20 int fetch_cache_info(unsigned int cpu) { - struct cpu_cacheinfo *this_cpu_ci; + struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); unsigned int levels =3D 0, split_levels =3D 0; int ret; =20 - if (acpi_disabled) { + if (acpi_disabled) ret =3D init_of_cache_level(cpu); - if (ret < 0) - return ret; - } else { + else { ret =3D acpi_get_cache_info(cpu, &levels, &split_levels); - if (ret < 0) + if (!ret) { + this_cpu_ci->num_levels =3D levels; + /* + * This assumes that: + * - there cannot be any split caches (data/instruction) + * above a unified cache + * - data/instruction caches come by pair + */ + this_cpu_ci->num_leaves =3D levels + split_levels; + } + } + + if (ret || !cache_leaves(cpu)) { + ret =3D early_cache_level(cpu); + if (ret) return ret; =20 - this_cpu_ci =3D get_cpu_cacheinfo(cpu); - this_cpu_ci->num_levels =3D levels; - /* - * This assumes that: - * - there cannot be any split caches (data/instruction) - * above a unified cache - * - data/instruction caches come by pair - */ - this_cpu_ci->num_leaves =3D levels + split_levels; + if (!cache_leaves(cpu)) + return -ENOENT; + + this_cpu_ci->early_arch_info =3D true; } - if (!cache_leaves(cpu)) - return -ENOENT; =20 return allocate_cache_info(cpu); } =20 int detect_cache_attributes(unsigned int cpu) { + unsigned int early_leaves =3D cache_leaves(cpu); int ret; =20 /* Since early initialization/allocation of the cacheinfo is allowed * via fetch_cache_info() and this also gets called as CPU hotplug * callbacks via cacheinfo_cpu_online, the init/alloc can be skipped * as it will happen only once (the cacheinfo memory is never freed). - * Just populate the cacheinfo. + * Just populate the cacheinfo. However, if the cacheinfo has been + * allocated early through the arch-specific early_cache_level() call, + * there is a chance the info is wrong (this can happen on arm64). In + * that case, call init_cache_level() anyway to give the arch-specific + * code a chance to make things right. */ - if (per_cpu_cacheinfo(cpu)) + if (per_cpu_cacheinfo(cpu) && !ci_cacheinfo(cpu)->early_arch_info) goto populate_leaves; =20 if (init_cache_level(cpu) || !cache_leaves(cpu)) return -ENOENT; =20 + if (cache_leaves(cpu) <=3D early_leaves) + goto populate_leaves; + + kfree(per_cpu_cacheinfo(cpu)); ret =3D allocate_cache_info(cpu); if (ret) return ret; diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 908e19d17f49..c9d44308fc42 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -76,9 +76,11 @@ struct cpu_cacheinfo { unsigned int num_levels; unsigned int num_leaves; bool cpu_map_populated; + bool early_arch_info; }; =20 struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu); +int early_cache_level(unsigned int cpu); int init_cache_level(unsigned int cpu); int init_of_cache_level(unsigned int cpu); int populate_cache_leaves(unsigned int cpu); --=20 2.39.2 From nobody Sun Apr 19 12:23:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF2D1C76196 for ; Mon, 3 Apr 2023 23:19:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233871AbjDCXTQ (ORCPT ); Mon, 3 Apr 2023 19:19:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233876AbjDCXTM (ORCPT ); Mon, 3 Apr 2023 19:19:12 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE4FC1FD7 for ; Mon, 3 Apr 2023 16:18:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1680563908; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BFLHr8TD8RfqA6eplD+afVyXuh6c0xOW13sUk0OaDso=; b=XQ0vwKe3OvxCpKXD8eDjfoSqdESY+0ISLfc1P9jFib1rIplnPopKDtWOhbUrmPMWw8vNNV au58YYFA7TyCw+wlpTP0jwur/Fwpq7+zP8ZiDKwa7XwB4h/8C+bs9+3l3T5i8k5aS4f59+ Nl7wTRTq1MFfhaPdDXo1txS2oyj0MeQ= Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-571-dWMuBxMjO9mz88oi2bhARQ-1; Mon, 03 Apr 2023 19:18:27 -0400 X-MC-Unique: dWMuBxMjO9mz88oi2bhARQ-1 Received: by mail-qt1-f198.google.com with SMTP id w13-20020ac857cd000000b003e37d3e6de2so20916482qta.16 for ; Mon, 03 Apr 2023 16:18:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680563906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BFLHr8TD8RfqA6eplD+afVyXuh6c0xOW13sUk0OaDso=; b=rAsBOKP6kOHVkRfahG5wTAJsMgozKkCgZpXyM7+EyeqisDkvF4jXKI9fue1rWbzOSM 1rYwM3vkpGPcR7ifxHGt264Yvsi+dBwJ1uNDZWILgutQdCr0GBbmDgZbhMEEa81AJ84u quxSzckvJTjFHitwKc9PIh2vTWw/G31HC9L/L8h1ePnJ48lBSic3kaDK2lL2Ichll4DG m65oNj5E60diLbZMleN7xBdFPUz0FFrhhv3R8kryuFw9TrsA2Wnrus7Ye+qqzHY7Oztq 5lDHpDOaga1m7bLzEeFxzCe11y2OSmEtx81EmLFrEBlmt9VhWqe/3mBB5rrZLUch4Pgi jCDw== X-Gm-Message-State: AAQBX9c/CVvPJG9QpQwgJs9SiDAfNTcVpljdRVse/SoYElKvt0cEc420 kFH4QmPwPWMHSfRRDrnY7HspDFKxVBP+bsZYWT3pS5yVODwxgQtDjJXtgwlIU9vab0W5D9G5FfC B6rebnuGVoLLMWLCvZJ7l6yJzvaCgGKtqGcAqXpL1IGUGNvjAF0oocIFmJFGxm9542pKt973cBN M8HvwOUOo= X-Received: by 2002:ad4:5dcb:0:b0:5b6:eef9:b8f7 with SMTP id m11-20020ad45dcb000000b005b6eef9b8f7mr778708qvh.6.1680563905878; Mon, 03 Apr 2023 16:18:25 -0700 (PDT) X-Google-Smtp-Source: AKy350Z6BgYgGucfGKREPBAxx1VLlrIXk8leHEc8OtAlDEGX+cpBZbJtwN4DICEvNgHx2cM+TfCeSA== X-Received: by 2002:ad4:5dcb:0:b0:5b6:eef9:b8f7 with SMTP id m11-20020ad45dcb000000b005b6eef9b8f7mr778686qvh.6.1680563905606; Mon, 03 Apr 2023 16:18:25 -0700 (PDT) Received: from thinkpad-p1.kanata.rendec.net (cpe00fc8d79db03-cm00fc8d79db00.cpe.net.fido.ca. [72.137.118.218]) by smtp.gmail.com with ESMTPSA id v6-20020ad45346000000b005e231177992sm2670207qvs.74.2023.04.03.16.18.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 16:18:25 -0700 (PDT) From: Radu Rendec To: linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Pierre Gondois , Sudeep Holla , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/2] cacheinfo: Add arm64 early level initializer implementation Date: Mon, 3 Apr 2023 19:15:51 -0400 Message-Id: <20230403231551.1090704-3-rrendec@redhat.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230403231551.1090704-1-rrendec@redhat.com> References: <20230403231551.1090704-1-rrendec@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds an architecture specific early cache level detection handler for arm64. This is basically the CLIDR_EL1 based detection that was previously done (only) in init_cache_level(). This is part of a patch series that attempts to further the work in commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary CPU"). Previously, in the absence of any DT/ACPI cache info, architecture specific cache detection and info allocation for secondary CPUs would happen in non-preemptible context during early CPU initialization and trigger a "BUG: sleeping function called from invalid context" splat on an RT kernel. This patch does not solve the problem completely for RT kernels. It relies on the assumption that on most systems, the CPUs are symmetrical and therefore have the same number of cache leaves. The cacheinfo memory is allocated early (on the primary CPU), relying on the new handler. If later (when CLIDR_EL1 based detection runs again on the secondary CPU) the initial assumption proves to be wrong and the CPU has in fact more leaves, the cacheinfo memory is reallocated, and that still triggers a splat on an RT kernel. In other words, asymmetrical CPU systems *must* still provide cacheinfo data in DT/ACPI to avoid the splat on RT kernels (unless secondary CPUs happen to have less leaves than the primary CPU). But symmetrical CPU systems (the majority) can now get away without the additional DT/ACPI data and rely on CLIDR_EL1 based detection. Signed-off-by: Radu Rendec --- arch/arm64/kernel/cacheinfo.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index c307f69e9b55..520d17e4ebe9 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -38,21 +38,37 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, this_leaf->type =3D type; } =20 -int init_cache_level(unsigned int cpu) +static void detect_cache_level(unsigned int *level, unsigned int *leaves) { - unsigned int ctype, level, leaves; - int fw_level, ret; - struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); + unsigned int ctype; =20 - for (level =3D 1, leaves =3D 0; level <=3D MAX_CACHE_LEVEL; level++) { - ctype =3D get_cache_type(level); + for (*level =3D 1, *leaves =3D 0; *level <=3D MAX_CACHE_LEVEL; (*level)++= ) { + ctype =3D get_cache_type(*level); if (ctype =3D=3D CACHE_TYPE_NOCACHE) { - level--; + (*level)--; break; } /* Separate instruction and data caches */ - leaves +=3D (ctype =3D=3D CACHE_TYPE_SEPARATE) ? 2 : 1; + *leaves +=3D (ctype =3D=3D CACHE_TYPE_SEPARATE) ? 2 : 1; } +} + +int early_cache_level(unsigned int cpu) +{ + struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); + + detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves); + + return 0; +} + +int init_cache_level(unsigned int cpu) +{ + unsigned int level, leaves; + int fw_level, ret; + struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); + + detect_cache_level(&level, &leaves); =20 if (acpi_disabled) { fw_level =3D of_find_last_cache_level(cpu); --=20 2.39.2